Title:
TESTER, ADJUSTMENT METHOD, AND ADJUSTMENT PROGRAM
Document Type and Number:
WIPO Patent Application WO/2008/007636
Kind Code:
A1
Abstract:
Provided is a tester for testing a device to be tested, which has data terminals
and a clock output terminal for outputting a clock signal indicating the timing
to acquire data signals outputted from the data terminals. The tester comprises
a reference clock source for generating the reference clock of the tester, timing
comparators which are provided corresponding to the data terminals and which
acquire the data signals outputted from the data terminals in accordance with
a timing clock acquired by adjusting the phase of the reference clock, and an adjusting
means for adjusting the phase of the timing clock according to the clock signal
and the timing clock.
Inventors:
SATO NAOKI (JP)
CHIBA NORIAKI (JP)
UEMATSU TOMOHIRO (JP)
CHIBA NORIAKI (JP)
UEMATSU TOMOHIRO (JP)
Application Number:
PCT/JP2007/063654
Publication Date:
January 17, 2008
Filing Date:
July 09, 2007
Export Citation:
Assignee:
ADVANTEST CORP (JP)
SATO NAOKI (JP)
CHIBA NORIAKI (JP)
UEMATSU TOMOHIRO (JP)
SATO NAOKI (JP)
CHIBA NORIAKI (JP)
UEMATSU TOMOHIRO (JP)
International Classes:
G01R31/319; G01R31/3183
Domestic Patent References:
| WO2002103379A1 | 2002-12-27 |
Foreign References:
| JP2001201532A | 2001-07-27 | |||
| JP2002042498A | 2002-02-08 |
Attorney, Agent or Firm:
RYUKA, Akihiro (22-1 Nishi-Shinjuku 6-chome,Shinjuku-k, Tokyo 05, JP)
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