Title:
TFT ARRAY SUBSTRATE FULL CONTACT TEST CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/114079
Kind Code:
A1
Abstract:
A TFT array substrate full contact test circuit. A test chip (5) is provided outside of a panel cutting boundary (7), this allows the size of test terminals (51) on the test chip (5) and the distance between adjacent test terminals (51) to increase, thus increasing the success rate of a test device contacting the test terminals (51). The test chip (5) is cut out when cutting a panel, and, wirings (35) connecting the test terminals (51) to driving terminals (31) on a driver chip (3) are made of a semiconductor (S) of a same layer as an active layer of TFT in a TFT array substrate, thus avoiding risks of circuit corrosion and electrostatic discharge when the panel is cut. Because the test chip (5) is cut out when cutting the panel, the need to cover the test terminals (51) with an insulating organic layer is obviated, and testing can be performed when a source/drain electrode of the TFT in the TFT array substrate is manufactured and when manufacturing of the TFT array substrate is entirely completed.
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Inventors:
CHEN CAIQIN (CN)
Application Number:
PCT/CN2018/072300
Publication Date:
June 20, 2019
Filing Date:
January 11, 2018
Export Citation:
Assignee:
WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECH CO LTD (CN)
International Classes:
H01L21/66
Foreign References:
| CN1740881A | 2006-03-01 | |||
| CN102831851A | 2012-12-19 | |||
| CN101359671A | 2009-02-04 | |||
| CN106019672A | 2016-10-12 | |||
| CN101907788A | 2010-12-08 | |||
| JP2013105159A | 2013-05-30 |
Attorney, Agent or Firm:
COMIPS INTELLECTUAL PROPERTY OFFICE (CN)
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