Title:
TFT SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2019/142638
Kind Code:
A1
Abstract:
Provided is a TFT substrate which has improved reliability. A TFT substrate according to the present invention is provided with: a first gate line and a second gate line, which are arranged to extend in a first direction; a signal line which intersects with the first gate line and the second gate line when viewed in plan; a semiconductor film which is connected to the signal line; a drain electrode which is connected to the semiconductor film; a planarization film which covers the signal line and the drain electrode; and a pixel electrode which is connected to the drain electrode. The semiconductor film has: a first straight line part which is arranged to extend parallel to the first gate line; and a second straight line part which is arranged to extend parallel to the second gate line. When viewed in plan, the first gate line and the second gate line are positioned between the first straight line part and the second straight line part. When viewed in plan, a first contact hole of the planarization film, said first contact hole connecting the drain electrode and the pixel electrode to each other, is positioned between the first gate line and the second gate line.
Inventors:
OGAWA AKIHIRO (JP)
Application Number:
PCT/JP2018/047970
Publication Date:
July 25, 2019
Filing Date:
December 26, 2018
Export Citation:
Assignee:
JAPAN DISPLAY INC (JP)
International Classes:
G09F9/30; G02F1/1368; G02F1/167; G09G3/20; G09G3/34; H01L21/336; H01L29/786
Foreign References:
| JP2010239108A | 2010-10-21 | |||
| JPH02178632A | 1990-07-11 | |||
| JP2004241700A | 2004-08-26 | |||
| JP2010085956A | 2010-04-15 |
Attorney, Agent or Firm:
SAKAI INTERNATIONAL PATENT OFFICE (JP)
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