BACKGROUND

[0001] Resistive random access memory (RRAM) devices are a leading choice of embedded non-volatile memory that also is compatible for high temperature retention applications. However, depending on the electrode material, the resistance ratio and/or the filament size participating in the switching process is different-this affects the read/write speeds and peripheral circuit design. Also, RRAM devices typically present higher switching power and time than other solid-state memory devices. Further, bits in RRAM device present severe variability that can result in complicated circuit design and/or error-correcting code (ECC)-intensive, thus increasing peripheral circuit area and/or reducing memory array efficiency— e.g., ratio of actual memory array to total area including peripheral circuitry. Therefore, much remains to be improved in the design of resistive switch devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings are an integral part of the disclosure and are incorporated into the subject specification. The drawings illustrate example embodiments of the disclosure and, in conjunction with the description and claims, serve to explain at least in part various principles, features, or aspects of the disclosure. Certain embodiments of the disclosure are described more fully below with reference to the accompanying drawings. However, various aspects of the disclosure can be implemented in many different forms and should not be construed as limited to the implementations set forth herein. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0003] FIG. 1 illustrates a schematic cross-sectional view of an example of a resistive switch device in accordance with one or more embodiments of the disclosure.

[0004] FIG. 2 illustrates examples of computational simulation results of temperature before formation of a conductive filament in a resistive switch device as a function of distance from the center of the filament, in accordance with one or more embodiments of the disclosure.

[0005] FIG. 3 illustrates a schematic cross-sectional view of another example of a resistive switch device in accordance with one or more embodiments of the disclosure.

[0006] FIG. 4 illustrates a schematic cross-sectional view of yet another example of a resistive switch device in accordance with one or more embodiments of the disclosure. [0007] FIG. 5A illustrates a schematic cross-sectional view of still another example of a resistive switch device in accordance with one or more embodiments of the disclosure.

[0008] FIG. 5B illustrates a schematic perspective view of the example resistive switch device shown in FIG. 5A.

[0009] FIG. 6 illustrates switching voltages as a function of thermal resistivity of a thermal layer in accordance with one or more embodiments of the disclosure.

[0010] FIG. 7 illustrates an example of a process for forming a resistive switch device according to one or more embodiments of the disclosure.

[0011] FIG. 8 illustrates an example of a process for forming a resistive switch device according to one or more embodiments of the disclosure.

[0012] FIG. 9 illustrates an example of a process for forming a resistive switch device according to one or more embodiments of the disclosure.

[0013] FIG. 10 illustrates an example of a system that utilizes solid-state devices in accordance with one or more embodiments of the disclosure.

DETAILED DESCRIPTION

[0014] The present disclosure recognizes and addresses, in at least some embodiments, the issue of switching performance of resistive switch devices. Embodiments of the disclosure can provide a resistive switch device that include one or thermal layers that can permit or otherwise facilitate confining heat within the resistive device, thus reducing a switching voltage to cause the resistive device to transition between a low-resistance state (LR) and a high-resistance state (HR). Other embodiments can provide processes for fabricating resistive switch devices including thermal layers in accordance with aspects of this disclosure. Resistive random access memory devices in accordance with the disclosure can be implemented in, or otherwise integrated into, a system-in-package embedded system, a system on chip, or a standalone configuration.

[0015] As described in greater detail below, in some embodiments, resistive switch devices can include a thermal layer that is thermally resistive and electrically conductive. As such, the thermal layer can be intercalated between an electrode layer and an oxide layer of a resistive switch device. As the oxide layer can constitute a switching medium of the resistive switch device that can be caused to transition between a low-resistance state and a high- resistance state via the application of a defined voltage across the resistive switch device. In the low-resistance state, a conductive or nearly conductive filament (CF) of metal ions can be formed within the oxide layer. As such, an electrical current can be transported across the resistive switch device, which current can cause to the thermal layer to confine heat. The confined heat can increase the temperature of the resistive switch device and/or can produce a temperature gradient in the vicinity of the CF, thus lowering a voltage to be applied in order to cause the resistive switch device to the high-resistance state. The thermal layer can be embodied in or can include, for example, a transparent conductive oxide, an amorphous material, or a porous material. While the disclosure is illustrated in connection with RRAM devices, embodiments described in this disclosure can be utilized or otherwise leveraged in other suitable memory devices including, for example, magnetoresistive random-access memory (MRAM) devices, according to various embodiments.

[0016] Other approaches to thermal confinement in accordance with one or more embodiments of the disclosure also can yield reduced switching voltages and/or switching rates in a resistive switch device. Specifically, in some embodiments, resistive switch devices can include a thermal layer that can be electrically insulating and thermally resistive or, in some embodiments, thermally insulating. As such, instead of the thermal layer being placed along a direction of an electrical field across the resistive switch device (in a HR state) or in the pathway of an electrical current transported across a resistive switch device (in a LR state), the thermal layer can be arranged to cap or otherwise encapsulate a resistive switch element including an oxygen exchange layer and an oxide layer. Similar to other resistive switch devices of this disclosure, the oxide layer can be caused to transition between a low- resistance state and a high-resistance state via the application of a defined voltage across the resistive switch device. An electrical current that can be transported across the resistive switch device in the LR state can cause the thermal layer to confine heat within the resistive switch element. The confined heat can increase the temperature of the resistive switch device, thus lowering a voltage to be applied in order to cause the resistive switch device to transition to the high-resistance state.

[0017] At least some embodiments of the disclosure can provide several advantages over conventional RRAM devices or other types of resistive memory devices, such as MRAM devices. In one example, a thermally resistive electrode (e.g., a low thermal conductivity electrode) can permit or otherwise facilitate lower switching power. In addition or in another example, one or more embodiments of the disclosure can improve the distribution of the memory cells in the array thus improving the sense margin, reducing the need for complex error-correcting code (ECC), thus enabling higher density. Further or in yet another embodiment, one or more embodiments can enable high performance resistive switching device at low switching voltages (e.g., less than about 400 mV). Furthermore or in still another example, one or more embodiments can permit tightening of distribution due to thermal confinement.

[0018] With reference to the drawings, FIG. 1 illustrates a schematic cross-sectional view of an example of a resistive switch device 100 in accordance with one or more embodiments of the disclosure. The resistive switch device 100 can include a first electrode layer 110a and a second electrode layer 110b. In some embodiments, the first electrode 110a can include a first conductive material including tungsten, platinum, silver, gold, palladium, copper, aluminum, titanium, tantalum, zinc, nickel, or an alloy of two or more of the foregoing metals. In other embodiments, the first conductive material can include a conductive ceramic, such as TiN or TaN. In still other embodiments, the first conductive material can include a first doped semiconductor. In addition, the second electrode layer 110b can include a second conductive material including tungsten, platinum, silver, gold, palladium, copper, aluminum, titanium, tantalum, zinc, nickel, or an alloy of two or more of the foregoing metals. Similar to the first conductive material, in some embodiments, the second conductive material can include a conductive ceramic, such as TiN or TaN. In addition or in other embodiments, the second conductive material can be embodied in a second doped semiconductor. As such, in one embodiment, the first conductive material can be essentially the same as the second conductive material. In one example, the first electrode layer 110a can be embodied in a Pt film and the second electrode layer 110b can be embodied in another Pt film. In another example, the first electrode layer 110a can be embodied in a TiN film and the second electrode layer 110b can be embodied in another TiN film. In another embodiment, the first conductive material and the second conductive material can be different. For another example, the second electrode layer 110b can be embodied on a Pt film and the first electrode layer 110a can be embodied in a TiN film.

[0019] A first voltage V _T (a real number in units of voltage) can be applied to the first electrode 110a and a second voltage V _B (a real number in units of voltage) can be applied to the second electrode 110b. In some embodiments, the resistive switch device 100 can be coupled (e.g., electrically coupled) to a field effect transistor (FET) or another type of solid state transistor. Such a coupling can be provided or otherwise facilitate by at least a resistive divider between the FET (or the other type of solid state transistor) and one of the first electrode 110a or the second electrode layer 110b. As such, in one example, V _T can be the voltage drop at the resistive divider and V _B can be grounded by a ground plane of a package that includes the resistive switch device 100. In another example, V _B can be the voltage difference across the resistive divider and VT can be grounded by a ground plane of a package that includes the resistive switch device 100. Regardless of the specific manner in which the voltages V _T and V _B can be supplied, a voltage difference AV = V _T -V _B can be applied across the resistive switch device 100.

[0020] As illustrated in FIG. 1, the first electrode layer 110a and the second electrode layer 110b can be separated by a group of layers including an oxide layer 140, a thermal layer 130, and an oxygen exchange layer 120. The oxide layer 140 can be positioned adjacent to the second electrode layer 110b and further adjacent to the thermal layer 130. As such, the oxide layer 140 can form a first substantially planar interface with the second electrode layer 110b and a second substantially planar interface with the thermal layer 130. The oxide layer 140 can be embodied in or can include a transition metal oxide, a perovskite oxide, or the like. For instance, the oxide layer 140 can include

Cu _x O _y , Co _x O _y , Mo0 ₂ , M0O ₃ , Mo _x O _y , Ta ₂ 0 ₅ , Ta^, Nb ₂ 0 ₅ , Nb^, SrZr0 ₃ , Sr _x Zr ) _z , SrTi0 ₃ , and the like. The indices x, y, and z represent real numbers indicative of the stoichiometry of a compound. In one aspect, the oxide that forms or constitutes the oxide layer 140 can have a defined concentration of oxygen vacancies, such concentration having a defined magnitude within a range from about 0.1 % to about 20 %. As mentioned, the oxide layer 140 can constitute a switching solid medium of the resistive switch device. Thus, in some aspects, the oxide layer 140 can permit or otherwise facilitate forming a conductive filament (CF) (or, in some embodiments, a nearly conductive filament) in response to a first voltage difference AVf _orm across the resistive switch device 100. As such, in one aspect, the resistive switch device can transition from an insulating state to a conductive state (or low-resistance state) in response to AVf _orm . The conductive filament can be formed within the oxide layer 140, along a direction substantially perpendicular to the first substantially planar interface. The oxide layer 140 also can permit or otherwise facilitate breaking the conductive filament in response to a second voltage difference AV _reset across the resistive switch device 100. Thus, the resistive switch device 100 can transition from the low-resistance state to a high-resistance state. In addition, the oxide layer 140 can permit or otherwise facilitate restoring the conductive filament in response to a third voltage difference AV _set across the resistive switch device 100. Thus, the resistive switch device 100 can transition from the high-resistance state to the low-resistance state.

[0021] As mentioned, the thermal layer 130 can be positioned adjacent to the oxide layer 140. The thermal layer 130 also can be positioned adjacent to the oxygen exchange layer (OEL) 120. The thermal layer 130 can be an electrical conductor and also can be thermally resistive. In Thus, in some embodiments, the thermal layer 130 can have an electrical resistivity in a range from about 150 nanoOhm m to about 10 milliOhm m. In addition, the thermal layer 130 can have a defined thermal conductivity κ (a real number in units of watts per meter Kelvin) determined at least in part by phonon excitations within the thermal layer 130. For instance, in some embodiments, κ can have a defined value in a range from about 0.1 W/(mK) to about 10 W/(m K). In some embodiments, the thermal layer 130 can include a transparent conductive oxide (TCO). The TCO can be embodied in or can include, for example, indium tin oxide (ITO), aluminium zinc oxide (AZO), indium gallium oxide (I GO), zinc gallium oxide (ZGO), doped indium gallium zinc oxide (IGZO), or the like. In other embodiments, the thermal layer can include an amorphous material. For instance, the amorphous material can include amorphous carbon (a-C), amorphous silicon (a-Si), amorphous germanium (a-Ge), or the like. In yet other embodiments, the thermal layer can include a porous material. As an illustration, the porous material can include porous silicon, porous germanium, porous SiCOH, porous Si0 ₂ doped with carbon (a porous material which embodies an electrical insulator), carbon doped ITO (a porous material that embodies an electrical conductor), and/or the like. In still other embodiments, the thermal layer can include conductive polymers that are thermally resistive; conductive composite materials that are thermally resistive; and the like. In further embodiments, the thermal layer can include doped semiconductors, such as poly-Si having high doping (e.g., carrier concentration in the range from about 10 ⁸ cm ^"3 to about 10 ²¹ cm ^"3 ), poly-Ge having high doping (e.g., carrier concentration in the range from about 10 ⁸ cm ^"3 to about 10 ²¹ cm ^"3 ), and the like.

[0022] In the resistive switch device 100, the thermal layer 130 can form a first substantially planar interface with the oxide layer 140 and a second substantially planar interface with the oxygen exchange layer 120. In some embodiments, each of the first and second substantially planar interfaces can be substantially perpendicular to the stacking direction of the resistive switch device 100. Thus, in one aspect, the thermal layer 130 can have a substantially uniform thickness t (a real number expressed in units of length) having a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm.

[0023] As mentioned, the oxygen exchange layer 120 can be positioned adjacent to the thermal layer 130. The oxygen exchange layer 120 also can be positioned adjacent to the electrode layer 110a. Thus, in some aspects, the oxygen exchange layer 120 can form a first substantially planar interface with the thermal layer 130 and a second substantially planar interface with the electrode layer 110a. In some embodiments, each of the first and second substantially planar interfaces can be substantially perpendicular to the stacking direction of the resistive switch device 100. In some embodiments, the oxygen exchange layer 120 can be embodied in or can include a metal film that can serve as a source of oxygen vacancies— and, thus, a source of metal ions for the oxide layer 140— by receiving oxygen ions. In one example, the metal film can be formed from a metal (e.g., Ta) that constitutes the oxide (e.g., Ta205) included in the oxide layer 140. The disclosure is not limited in that respect and any suitable oxygen getter material can constitute the oxygen exchange layer 120.

[0024] FIG. 2 illustrates examples of simulation results of temperature before formation of a conductive filament in a resistive switch device as a function of distance from the center of the conductive filament, in accordance with one or more embodiments of the disclosure. As it can be gleaned from the simulation results, a first thermal layer that a first thermal conductivity KA can provide a first temperature increment in the vicinity of the locus of formation of the CF that is greater and more localized than a second temperature increment provided by a second thermal layer that has a second thermal conductivity KB less than KA. More specifically, as an illustration, trace 210 and trace 220 illustrate temperature before formation of the CF as function of distance from the center of the CF for thermal layers having the thermal conductivity KA and κ _Β > KA, respectively.

[0025] Diagram 215 illustrates simulation results for a spatial distribution of temperatures in a first resistive switch device having a thermal layer that is a good thermal conductor (e.g., thermal conductivity of the order of about 100 W/(m K)). For instance, good thermal conductors can have thermal conductivities that range from about 100 W/(mK) to about 500 W/(mK). Diagram 225 illustrates simulation results for a spatial distribution of temperatures in a second resistive switch device having a thermal layer that is a poor thermal conductor. A poor thermal conductor can have, in some embodiments, a thermal conductivity of the order of about 1 W/(mK) or less. For instance, some particularly poor thermal conductors can have thermal conductivities in a range from about 0.1 W/(mK) to about 2 W/(m K), less poor thermal conductors can have thermal conductivities in a range from about 2 W/(m K) to about 10 W/(m K). In other embodiments, a moderately poor thermal conductor can have a thermal conductivity of the order of about 10 W/(m K), such as thermal conductivities in a range from about 10 W/(m K) to about 50 W/(m K). [0026] As mentioned, other approaches to thermal confinement in accordance with one or more embodiments of the disclosure also can yield reduced switching voltages in a resistive switch device. Some of those approaches can include capping or otherwise encapsulating the resistive switch element with one or more thermal layers, each of which can be an electric insulator that is thermally resistive (e.g., a thermal insulator). The capped or otherwise encapsulated resistive switch element can embody or can constitute the resistive switch device having reduced switching voltages.

[0027] The arrangement of thermal layer 130 and the on the stack of layers that constitute a resistive switch device can be reversed while maintaining the thermal activation that can yield a switching voltage that is less than the switching voltage in another resistive switch device that lacks the thermal layer 130. FIG. 3 illustrates an example of a resistive switch device 300 in which the arrangement of the thermal layer 130 and the oxygen exchange layer 120 along the stacking direction z is reversed with respect to the resistive switch device 100. The specific arrangement of such layers can be based at least on the type of material that constitutes the thermal layer 130 and the type of material that constitutes the oxygen exchange layer 120.

[0028] FIG. 4 illustrates a schematic cross-sectional view of an example of a resistive switch device 400 that includes capping thermal layers, in accordance with one or more embodiments of the disclosure. The resistive switch device 400 includes a group of layers that forms a resistive switch element. The group of layers can be stacked along a stacking direction z, and can include the first electrode layer 110a and the first electrode layer 110b, the oxygen exchange layer 120, and the oxide layer 140 disclosed herein. A first thermal layer 410a can cap or otherwise bound the resistive switch device 400 at a first end of such a device, forming a first substantially planar interface 414a with the first electrode layer 110a. A second thermal layer 410b can cap or otherwise bound the resistive switch element 400 at a second end opposite the first end, forming a second substantially planar interface 414b with the second electrode layer 110b. Each of the first thermal layer 410a and the second thermal layer 410b can be embodied in or can include, for example, a respective electrical insulator that is thermally resistive. As mentioned, in some embodiments, a thermally resistive material in accordance with aspects of this disclosure can be a material that has a thermal conductivity of magnitude in a range from about 0.1 W/(mK) to about 10 W/(m K).

Specifically, in some embodiments, the first thermal layer 410 can be embodied in or can include a lead oxide (such as Pb ₂ 03 or Pb ₃ 0 ₄ ) or a metal transition oxide (such as HfC ). In addition, the second thermal layer 410b can be embodied in or can include a second lead oxide or a second transition metal oxide. In other embodiments, the first thermal layer 410a can be embodied in or can include a first ceramic (such as hexagonal boron nitride). In addition, the second thermal layer 410b can be embodied in or can include a second ceramic (such as hexagonal boron nitride). In yet other embodiments, the first thermal layer 410a can be embodied in or can include first Debye mismatch layers (such as yttrium-doped zinc oxide (YZO)). In addition, the second thermal layer 410b can be embodied in or can include second Debye mismatch layers (such as YZO). In still other embodiments, the first thermal layer 410a can be embodied in or can include a first oxygen getter material, and the second thermal layer 410b can be embodied in or can include a second oxygen getter material.

[0029] The first thermal layer 410a can have a substantially uniform thickness t' (a real number expressed in units of length) having a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t' can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm. In some embodiments, the second thermal layer 410b also can have the substantially uniform thickness t The disclosure is not limited in that respect, and, in some embodiments, the thermal layer 410b can have a substantially uniform thickness t" (a real number expressed in units of length) that is different from t The substantially uniform thickness t" can have a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t" can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm.

[0030] FIG. 5A illustrates a schematic cross-sectional view of an example of a resistive switch device 500 that includes a capping or otherwise encapsulating thermal layer, in accordance with one or more embodiments of the disclosure. Similar to other resistive switch devices described herein, the resistive switch device 500 includes a group of layers that forms a resistive switch element. The group of layers can be stacked along a stacking direction z, and can include the first electrode layer 1 10a and the first electrode layer 110b, the oxygen exchange layer 120, and the oxide layer 140 disclosed herein. A conformal thermal layer 510 can cap or otherwise encapsulate the resistive switch device 500. (Also illustrated in FIG. 5B.) As illustrated, in some embodiments, the conformal layer 510 can form several substantially planar interfaces with the first electrode layer 110a and the second electrode layer 1 10b. More specifically, the conformal layer 510 can form a first substantially planar interface 514a, a second substantially planar interface 514b, and a third substantially planar interface 514c with the first electrode layer 110a. In addition, the conformal layer 510 can form a first substantially planar interface 518a and a second substantially planar interface 518b with the second electrode layer 110b. The conformal thermal layer 510 can be embodied in or can include, for example, an electrical insulator that is thermally resistive. As mentioned, such an electrical insulator can have a therma conductivity of a magnitude in a range from about 0.1 W/(mK) to about 50 W/(mK). In some embodiments, the electrical insulator can be nearly thermally insulating, having a thermal conductivity in a range from about 0.1 W/(m K) to about 2 W/(mK). In other embodiments, the electrical insulator can be a poor thermal conductor, having thermal conductivities in a range from about 2 W/(m K) to about 10 W/(m K). In other embodiments, the electrical insulator can be a moderately poor thermal conductor having a thermal conductivity in a range from about 10 W/(mK) to about 50 W/(m K). As an illustration, the conformal thermal layer 510 can be an electrical insulator and also a thermal insulator. In some embodiments, the conformal thermal layer 510 can be embodied in or can include a lead oxide (such as Pb ₂ 03 or Pb ₃ 0 ₄ ) or a metal transition oxide (such as HfC ). In other embodiments, the conformal thermal layer 510 can be embodied in or can include a ceramic (such as h-BN). In yet other embodiments, the conformal thermal layer 510 can be embodied in or can include Debye mismatch layers (such as YZO). In still other embodiments, the conformal thermal layer 510 can be embodied in or can include an oxygen getter material.

[0031] As illustrated in FIG. 5A and FIG. 5B, which figure presents an perspective view of a schematic cross-section of the resistive switch device 500, the conformal thermal layer 510 can have a substantially uniform thickness t' having a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t' can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm.

[0032] FIG. 6 illustrates a diagram 600 of switching voltages as a function of thermal resistivity of a thermal layer that caps or otherwise encapsulates a resistive switch device in accordance with one or more embodiments of the disclosure. The thermal resistivity is indicated as the reciprocal of thermal conductivity (κ ^"1 ) of the thermal layer. As it can be gleaned from the diagram 600, the smaller the thermal conductivity is, the smaller the switching voltage. In one aspect, the magnitude of the observed switching voltages decay (indicated with triangles in FIG. 6) with the magnitude of κ— e.g., as the thermal layer becomes a thermal insulator. Results of simulations of the switching voltage in the resistive switch device are shown as trace 610 and can model the data. Specifically, the results of the simulations present an exponential decay with the magnitude of k, the exponential decay fits the observed decay. As disclosed herein, without intending to be bound by theory, simulation, and/or modeling, the reduction of the switching voltage with thermal conductivity of the thermal layer can be due to the thermal activation afforded by heat confined within the resistive switch element of the resistive switch device.

[0033] In view of the aspects described herein, numerous other processes can be implemented for providing a semiconductor device in accordance with one or more embodiments of this disclosure. Examples of such processes can be better appreciated with reference to the flowchart in FIGS. 7-9. Each block in the illustrated flowchart can represent a process stage or process operation (e.g., etching or removal of an amount of a material, coating of a structure with another amount of another material, epitaxial growth of carrier- doped layer, and the like). Although a particular order of the blocks within an illustrated flowchart is provided, such an ordering is not limiting and the order two or more of the blocks can be altered without affecting the outcome of the process. For the sake of clarity, well-known elements or aspects of a block in the illustrated flowcharts may not be described in full detail. As with any other processes described herein, in some embodiments, the example methods illustrated in FIGS. 7-9 can be implemented in conjunction with other processes.

[0034] FIG. 7 illustrates a flowchart of an example process 700 for forming a resistive switch device according to one or more embodiments of the disclosure. At block 710, a first electrode layer can be formed. Forming the first electrode layer can include, for example, depositing via physical vapor deposition a first conductive material onto a substrate. The first conductive material can include, in some embodiments, a first metal, a first metal alloy, a first conductive ceramic (e.g., TiN or TaN), or a first doped semiconductor. In one example, the first electrode layer can be embodied in or can constitute the electrode layer 1 10b. Thus, as disclosed herein, the first electrode layer can include a substantially planar surface that is essentially perpendicular to a stacking direction (e.g., direction z illustrated in FIG. 1).

[0035] At block 720, an oxide layer can be formed on the first electrode layer. The oxide layer can be embodied in or can constitute a switching solid medium of the resistive switch device formed by implementing the example method 700. As such, in one example, the oxide layer can be embodied in or can constitute the oxide layer 140. The oxide layer can be formed, in one example, on the substantially planar surface of the first electrode layer. In addition, the oxide layer can have a substantially planar surface that is substantially perpendicular to the stacking direction of the resistive switch device. Forming the oxide layer can include depositing an amount of an oxide (such as a transition metal oxide, a perovskite oxide, or the like) on the substantially planar surface of the first electrode layer. In some embodiments, the amount of the oxide can be deposited by treating the oxide layer according to one or a combination of numerous deposition processes, including, for example, chemical vapor deposition (CVD); atomic layer deposition (ALD); physical vapor deposition (PVD); sputtering; chemical solution deposition; spin coating; or the like. Chemical vapor deposition can include, for example, metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0036] At block 730, a thermal layer can be formed on the oxide layer. The thermal layer can be formed, in some embodiments, on the substantially planar surface of the oxide layer formed at block 720. Specifically, in one embodiment, forming the thermal layer can include depositing an amount of a transparent conductive oxide on the substantially planar surface of the oxide layer. As mentioned, the TCO can be selected from a group including, for example, ITO, AZO, IGO, ZGO, and doped IGZO. In another embodiment, forming the thermal layer can include depositing an amount of an amorphous material on the substantially planar surface of the oxide layer. As also mentioned, the amorphous material can be selected from a group including amorphous carbon, amorphous silicon, and amorphous germanium. In yet another embodiment, forming the thermal layer can include depositing an amount of a porous material on the substantially planar surface of the oxide layer. As further mentioned, the porous material can include, for example, porous silicon, porous germanium, porous SiCOH, porous SiG-2 doped with carbon (a porous material which embodies an electrical insulator), carbon doped ITO (a porous material that embodies an electrical conductor), and the like. In a further embodiment, forming the thermal layer can include depositing one or more of a first amount of a conductive ceramic; a second amount of a conductive polymer; a third amount of a conductive composite material; or the like. Each of the amount of the TCO, the amount of the amorphous material, and amount of the porous material, the first amount of the conductive ceramic, the second amount of the conductive polymer, and the third amount of the conductive composite material can be deposited by treating the oxide layer according to one or a combination of numerous deposition processes, including, for example, CVD; ALD; PVD; sputtering; chemical solution deposition; spin coating; or the like. As mentioned, CVD can include, for example, MOCVD, LPCVD, or PECVD.

[0037] In one example, the thermal layer can be embodied in or can constitute the thermal layer 130 illustrated in FIG. 1. The thermal layer also can have a substantially planar surface that is substantially perpendicular to the stacking direction of the resistive switch device formed by implementing the example method 700. As disclosed herein, in some embodiments, the thermal layer can have a substantially uniform thickness t having a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm.

[0038] At block 740, an oxygen exchange layer (OEL) can be formed on the thermal layer. As mentioned, in some embodiments, the OEL can be embodied in or can include a metal film that can serve as a source of oxygen vacancies— and, thus, a source of metal ions on the oxide layer formed at block 720— by receiving oxygen ions. In some embodiments, the metal film can be formed from a metal (e.g., Ta) that constitutes the oxide (e.g., Ta ₂ 0 ₅ ) included in the oxide layer formed at block 720. The disclosure is not limited in that respect, and any suitable OEL can be formed on the thermal layer. The OEL also can have a substantially planar surface that is substantially parallel to the other substantially planar surface included in the thermal layer.

[0039] At block 750, a second electrode layer can be formed on the oxygen exchange layer. The second electrode layer can be formed, in some embodiments, on the substantially planar surface of the OEL formed at block 740. Forming the second electrode layer can include, for example, depositing via physical vapor deposition a second conductive material. The second conductive material can include, in some embodiments, a first metal, a first metal alloy, or a first conductive ceramic (e.g., TiN or TaN). Numerous combinations of the second conductive material and the first conductive material that constitutes the first electrode formed at block 710 can be implemented. Thus, in one embodiment, the second conductive material can be different from the first conductive material. In another embodiment, the second conductive material can be the same as the first conductive material. In some implementations, the second electrode layer can be embodied in or can constitute the electrode layer 110a.

[0040] In some embodiments, the order in which block 730 and block 740 are implemented can be reversed, forming the OEL on the oxide layer and forming the thermal layer on the OEL. Thus, the resistive switch device that can be formed by implementing the example method 700 can have the OEL forming an interface with the oxide layer. For instance, such a resistive switch device can be embodied in device 200 illustrated in FIG. 2. The order can be based at least on the type of material that constitutes the thermal layer and the type of material that constitutes the OEL. [0041] FIG. 8 illustrates a flowchart of an example process 800 for forming a resistive switch device according to one or more embodiments of the disclosure. As described herein, implementing the example process 800 can result in a resistive switch device that includes a resistive switch region encapsulated or otherwise bound by the electrical insulators that are thermally resistive. At block 810, a first thermal layer can be formed. The thermal layer can be formed, in some embodiments, on a substrate. Specifically, in one embodiment, forming the first thermal layer can include depositing an amount of an oxide on the substrate. As mentioned, the oxide can be selected from a group including, for example, Pb ₂ 03, Vb^On, and HfC>2. In another embodiment, forming the first thermal layer can include depositing an amount of a ceramic on the substrate. In one example, the ceramic includes hexagonal boron nitride (h-BN). In yet another embodiment, forming the first thermal layer can include depositing an amount of Debye mismatch layers. In one example, the Debye mismatch layers can include yttrium-doped zinc oxide (YZO). In still another embodiment, forming the first thermal layer can include depositing an amount of an oxygen getter material, such as Ta, Mg, Zr, Ba, P, or the like. Each of the amount of the oxide, the amount of the ceramic, the amount of the Debye mismatch layers, and the amount of the oxygen getter material can be deposited by implementing one or a combination of numerous deposition processes, including, for example, CVD; ALD; PVD; sputtering; chemical solution deposition; spin coating; or the like. As mentioned, CVD can include, for example, MOCVD, LPCVD, or PECVD.

[0042] In one example, the first thermal layer can be embodied in or can constitute the thermal layer 410a illustrated in FIG. 4. The first thermal layer also can have a substantially planar surface that is substantially perpendicular to a stacking direction (e.g., direction z illustrated in FIG. 4) of the resistive switch device formed by implementing the example method 800. As disclosed herein, in some embodiments, the first thermal layer can have a substantially uniform thickness t' having a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm.

[0043] At block 820, a first electrode layer can be formed on the first thermal layer. Forming the first electrode layer can include, for example, physical vapor deposition of a first conductive material onto a substrate. The first conductive material can include, in some embodiments, a first metal, a first metal alloy, a first conductive ceramic (e.g., TiN or TaN), or a first doped semiconductor. In one example, the first electrode layer can be embodied in or can constitute the electrode layer 110b. Thus, as disclosed herein, the first electrode layer can include a substantially planar surface that is essentially perpendicular to the stacking direction of the resistive switch device formed by implementing the example method 800.

[0044] At block 830, an oxide layer can be formed on the first electrode layer. Similar to other processes disclosed herein, the oxide layer can be embodied in or can constitute a switching solid medium of the resistive switch/device formed by implementing the example process 800. As such, in one example, the oxide layer can be embodied in or can constitute the oxide layer 140. The oxide layer can be formed, in one example, on the substantially planar surface of the first electrode layer. In addition, the oxide layer can have a substantially planar surface that is substantially perpendicular to the stacking direction of the resistive switch device. Forming the oxide layer can include depositing an amount of an oxide (such as a transition metal oxide, a perovskite oxide, or the like) on the substantially planar surface of the first electrode layer. As disclosed herein, in some embodiments, the amount of the oxide can be deposited by treating the first electrode layer according to one or a combination of numerous deposition processes, including, for example, CVD; ALD; PVD; sputtering; chemical solution deposition; spin coating; or the like. As mentioned, chemical vapor deposition can include, for example, MOCVD, LPCVD, or PECVD.

[0045] At block 840, an oxygen exchange layer can be formed on the oxide layer. As mentioned, in some embodiments, the OEL can be embodied in or can include a metal film that can serve as a source of oxygen vacancies— and, thus, a source of metal ions on the oxide layer formed at block 820— by receiving oxygen ions. In some embodiments, the metal film can be formed from a metal (e.g., Ta) that constitutes the oxide (e.g., Ta ₂ 0s) included in the oxide layer formed at block 820. The disclosure is not limited in that respect, and any suitable OEL can be formed on the thermal layer. Similar to other OELs formed according to processes of this disclosure, the OEL also can have a substantially planar surface that is substantially parallel to the other substantially planar surface included in the first electrode layer.

[0046] At block 850, a second electrode layer can be formed on the oxygen exchange layer. The second electrode layer can be formed, in some embodiments, on the substantially planar surface of the OEL formed at block 840. Forming the second electrode layer can include, for example, depositing via physical vapor deposition a second conductive material. The second conductive material can include, in some embodiments, a first metal, a first metal alloy, a first conductive ceramic (e.g., TiN or TaN), or a doped semiconductor. Numerous combinations of the second conductive material and the first conductive material that constitutes the first electrode formed at block 810 can be implemented. Thus, in one embodiment, the second conductive material can be different from the first conductive material. In another embodiment, the second conductive material can be the same as the first conductive material. In some implementations, the second electrode layer can be embodied in or can constitute the electrode layer 110a illustrated in FIG. 4.

[0047] At block 860, a second thermal layer can be formed. The thermal layer can be formed on the second electrode layer. Forming the second thermal layer can be

accomplished in a similar fashion to forming the first thermal layer at block 810. Thus, in one embodiment, forming the second thermal layer can include depositing an amount of an oxide on the substrate. As mentioned, the oxide can be selected from a group including, for example, lead oxides (such as Pb ₂ 03 and Pb ₃ 0 ₄ ), HfC^, and other types of oxides. In another embodiment, forming the second thermal layer can include depositing an amount of a ceramic on the substrate. In one example, the ceramic includes hexagonal boron nitride (h- BN). In yet another embodiment, forming the second thermal layer can include depositing an amount of Debye mismatch layers. In one example, the Debye mismatch layers can include yttrium-doped zinc oxide (YZO). Each of the amount of the oxide, the amount of the ceramic, the amount of the Debye mismatch layers, and the amount of the oxygen getter material can be deposited by implementing one or a combination of numerous deposition processes, including, for example, CVD; ALD; PVD; sputtering; chemical solution deposition; spin coating; or the like. As mentioned, CVD can include, for example,

MOCVD, LPCVD, or PECVD.

[0048] In one example, the second thermal layer can be embodied in or can constitute the thermal layer 410b illustrated in FIG. 4. The second thermal layer also can have a substantially planar surface that is substantially perpendicular to the stacking direction of the resistive switch device formed by implementing the example method 800. Similar to the first thermal layer formed at block 610, in some embodiments, the second thermal layer also can have the substantially uniform thickness t The disclosure is not limited in that respect and, in some embodiments, the second thermal layer can have a substantially uniform thickness t" that is different from t The substantially uniform thickness t" can have a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t" can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm.

[0049] Implementation of the example process 800 results in a resistive switch device that includes a resistive switch element capped or otherwise bound by the electrical insulators that are thermally resistive. The resistive switch element includes the OEL and the oxide layer. The first thermal layer and the second thermal layer embody the electrical insulators.

[0050] FIG. 9 illustrates a flowchart of an example process 900 for forming a resistive switch device according to one or more embodiments of the disclosure. At block 910, a first electrode layer can be formed. Forming the first electrode layer can include, for example, depositing via physical vapor deposition a first conductive material onto a substrate. The first conductive material can include, in some embodiments, a first metal, a first metal alloy, a first conductive ceramic (e.g., TiN or TaN), or a first doped semiconductor. In one example, the first electrode layer can be embodied in or can constitute the electrode layer 1 10b. Thus, as disclosed herein, the first electrode layer can include a substantially planar surface that is essentially perpendicular to a stacking direction (e.g., direction z illustrated in FIG. 1). At block 920, an oxide layer can be formed on the first electrode layer. The oxide layer can be embodied in or can constitute a switching solid medium of the resistive switch device formed by implementing the example method 900. As such, in one example, the oxide layer can be embodied in or can constitute the oxide layer 140. The oxide layer can be formed, in one example, on the substantially planar surface of the first electrode layer. In addition, the oxide layer can have a substantially planar surface that is substantially perpendicular to the stacking direction of the resistive switch device. Forming the oxide layer can include depositing an amount of an oxide (such as a transition metal oxide, a perovskite oxide, or the like) on the substantially planar surface of the first electrode layer. In some embodiments, the amount of the oxide can be deposited by treating the oxide layer according to one or a combination of numerous deposition processes, including, for example, CVD; ALD; PVD; sputtering;

chemical solution deposition; spin coating; or the like. As mentioned, chemical vapor deposition can include, for example, MOCVD, LPCVD, or PECVD.

[0051] At block 930, an oxygen exchange layer can be formed on the oxide layer. As mentioned, in some embodiments, the OEL can be embodied in or can include a metal film that can serve as a source of oxygen vacancies— and, thus, a source of metal ions on the oxide layer formed at block 920— by receiving oxygen ions. In some embodiments, the metal film can be formed from a metal (e.g., Ta) that constitutes the oxide (e.g., Ta20s) included in the oxide layer formed at block 920. The disclosure is not limited in that respect and any suitable OEL can be formed on the thermal layer. Similar to other OELs formed according to processes of this disclosure, the OEL also can have a substantially planar surface that is substantially parallel to the other substantially planar surface included in the first electrode layer. In one example, the OEL can be embodied in or can constitute the oxygen exchange layer 420 illustrated in FIG. 4.

[0052] At block 940, a second electrode layer can be formed on the oxygen exchange layer. The second electrode layer can be formed, in some embodiments, on the substantially planar surface of the OEL formed at block 930. Forming the second electrode layer can include, for example, depositing via physical vapor deposition a second conductive material. The second conductive material can include, in some embodiments, a first metal, a first metal alloy, a first conductive ceramic (e.g., TiN or TaN), or a doped semiconductor. Numerous combinations of the second conductive material and the first conductive material that constitutes the first electrode formed at block 910 can be implemented. Thus, in one embodiment, the second conductive material can be different from the first conductive material. In another embodiment, the second conductive material can be the same as the first conductive material. In some implementations, the second electrode layer can be embodied in or can constitute the electrode layer 1 10a, as is illustrated in FIG. 4.

[0053] At block 950, a conformal thermal layer can be formed on the resistive switch element formed by implementing blocks 910-940. In one embodiment, forming the conformal thermal layer can include depositing an amount of an oxide on the resistive switching element. As mentioned, the oxide can be selected from a group including, for example, lead oxides (such as Pb ₂ 03 and Pb ₃ 0 ₄ ), HfC>2, and other types of oxides. In another embodiment, forming the conformal thermal layer can include depositing an amount of a ceramic on the substrate. In one example, the ceramic includes hexagonal boron nitride (h- BN). In yet another embodiment, forming the conformal thermal layer can include depositing an amount of Debye mismatch layers. In one example, the Debye mismatch layers can include yttrium-doped zinc oxide (YZO). Each of the amount of the oxide, the amount of the ceramic, the amount of the Debye mismatch layers, and the amount of the oxygen getter material can be deposited by treating the resistive switch element according to a deposition processes, such as ALD, that can permit or otherwise facilitate conformal deposition of an amount of the material that constitutes the conformal thermal layer. Other deposition processes may be utilized to treat the resistive switch element, including CVD; PVD;

sputtering; chemical solution deposition; spin coating; or the like.

[0054] In one example, the conformal thermal layer can be embodied in or can constitute the thermal layer 510 illustrated in FIG. 5A. In some embodiments, the conformal thermal layer can have the substantially uniform thickness t' having a magnitude in a range from about 0.5 nm to about 5.0 nm. For instance, t" can be equal to about 0.5 nm, about 1.0 nm, about 1.5 nm, about 2.0 nm, about 2.5 nm, about 3.0 nm, about 3.5 nm, about 4.0 nm, about 4.5 nm, or about 5.0 nm.

[0055] Similar to other thermal layers described herein (e.g., thermal layer 410a and thermal layer 410b), the conformal thermal layer formed at block 750 can encapsulate or otherwise bound the resistive switch element formed by implementing blocks 910-940. As such, in some embodiments, the resistive switch element can be capped or otherwise encapsulated by an electrical insulator that also is a thermal insulator.

[0056] FIG. 10 depicts an example of a system 1000 according to one or more embodiments of the disclosure. In one embodiment, system 1000 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 1000 can include a system on a chip (SOC) system or a system-in-package (SiP).

[0057] In one embodiment, system 1000 includes multiple processors including processor 1010 and processor N 1005, where processor 1005 has logic similar or identical to the logic of processor 1010. In one embodiment, processor 1010 has one or more processing cores (represented here by processing core 1012 and processing core 1012N, where 1012N represents the Nth processor core inside processor 1010, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 10). In some embodiments, processing core 1012 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 1010 has a cache memory 1016 to cache instructions and/or data for system 1000. Cache memory 1016 may be organized into a hierarchical structure including one or more levels of cache memory.

[0058] In some embodiments, processor 1010 includes a memory controller (MC) 1014, which is configured to perform functions that enable the processor 1010 to access and communicate with memory 1030 that includes a volatile memory 1032 and/or a non-volatile memory 1034. In some embodiments, processor 1010 can be coupled with memory 1030 and chipset 1020. Processor 1010 may also be coupled to a wireless antenna 1078 to

communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface 1078 operates in accordance with, but is not limited to, the IEEE 802.1 1 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. [0059] In some embodiments, volatile memory 1032 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 1034 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of nonvolatile memory device.

[0060] Memory device 1030 stores information and instructions to be executed by processor 1010. In one embodiment, memory 1030 may also store temporary variables or other intermediate information while processor 1010 is executing instructions. In the illustrated embodiment, chipset 1020 connects with processor 1010 via Point-to-Point (PtP or P-P) interface 1017 and P-P interface 1022. Chipset 1020 enables processor 1010 to connect to other elements in system 900. In some embodiments of the disclosure, P-P interface 1017 and P-P interface 1022 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0061] In some embodiments, chipset 1020 can be configured to communicate with processor 1010, 1005N, display device 1040, and other devices 1072, 1076, 1074, 1060, 1062, 1064, 1066, 1077, etc. Chipset 1020 may also be coupled to the wireless antenna 1078 to communicate with any device configured to transmit and/or receive wireless signals.

[0062] Chipset 1020 connects to display device 1040 via interface 1026. Display 1040 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 1010 and chipset 1020 are integrated into a single SOC. In addition, chipset 1020 connects to bus 1050 and/or bus 1055 that interconnect various elements 1074, 1060, 1062, 1064, and 1066. Bus 1050 and bus 1055 may be interconnected via a bus bridge 1072. In one embodiment, chipset 1020 couples with a non-volatile memory 1060, a mass storage device(s) 1062, a keyboard/mouse 1064, and a network interface 1066 via interface 1024 and/or 1004, smart TV 1076, consumer electronics 1077, etc.

[0063] In one embodiment, mass storage device(s) 1062 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 1066 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0064] While the modules shown in FIG. 10 are depicted as separate blocks within the system 900, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 1016 is depicted as a separate block within processor 1010, cache memory 1016 or selected elements thereof can be incorporated into processor core 1012.

[0065] It is noted that the system 1000 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor devices (for example, the semiconductor device described in connection with FIG. 1) or other types of semiconductor devices, as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0066] The semiconductor devices or other types of solid-state devices, as described herein, may be embody or may constitute one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products

(ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (e.g., Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0067] Additionally or alternatively, the semiconductor devices, as described herein, may embody or may constitute one or more memory chips or other types of memory devices. The memory chips may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0068] In example embodiments, the electronic device in which the semiconductor devices in accordance with this disclosure are provided may be a computing device. Such a computing device may house one or more boards on which the semiconductor package connections may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the semiconductor package. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0069] The semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0070] Additionally or alternatively, semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure may be used in connection with one or more memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0071] In example embodiments, an electronic device in which the semiconductor devices and other types of solid assemblies in accordance with aspects of the disclosure can be used and/or provided may be a computing device. Such a computing device may house one or more boards on which the interconnects may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the interconnects. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi- Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0072] Further Examples.— The following example embodiments pertain to further embodiments of this disclosure. Example 1 is a solid-state device including at least one thermal layer, each of the at least one thermal layer being electrically insulating and thermally resistive; a first electrode layer positioned adjacent a first thermal layer of the at least one thermal layer, the first electrode layer forming a first substantially planar interface with the first thermal layer; an oxygen exchange layer positioned adjacent the first electrode layer and forming a second substantially planar interface with the first electrode layer; an oxide layer positioned adjacent the oxygen exchange layer, the oxide layer to form a conductive filament along a direction substantially perpendicular to the first substantially planar interface; and a second electrode layer positioned adjacent the oxide layer and forming a third substantially planar interface with the oxide layer.

[0073] In Example 2, the subject matter of Example 1 can optionally include the at least one thermal layer including a second thermal layer, the first thermal layer having a thermal conductivity of a first magnitude in a range from about 0.1 W/(m K) to about 50 W/(m K), and the second thermal layer having a thermal conductivity of a second magnitude in the range from about 0.1 W/(m K) to about 50 W/(mK).

[0074] In Example 3, the subject matter of Example 1 and/or Example 2 can optionally include the at least one thermal layer including a second thermal layer positioned adjacent the second electrode layer and forming a fourth substantially planar interface with the second electrode layer, the fourth substantially planar interface is opposite to the third substantially planar interface with the oxide layer.

[0075] In Example 4, the subject matter of Example 1 and/or Example 2 can optionally include the at least one thermal layer including a second thermal layer and a third thermal layer substantially parallel to the second thermal layer, each of the second thermal layer and the third thermal layer is positioned adjacent the first electrode layer and the second electrode layer.

[0076] In Example 5, the subject matter of Example 4 can optionally include the second thermal layer and the third thermal layer being in contact with the first electrode layer, the second electrode layer, the oxygen exchange layer, and the oxide layer.

[0077] In Example 6, the subject matter of Example 4 can optionally include the second thermal layer forming respective fourth substantially planar interfaces with the first electrode layer and the second electrode layer.

[0078] In Example 7, the subject matter of Example 6 can optionally include the third thermal layer forming respective fifth substantially planar interfaces with the first electrode layer and the second electrode layer. [0079] In Example 8, the subject matter of Example 1, Example 2, Example 3, Example 4, Example 5, and/or Example 6 can optionally include the first thermal layer including at least one of an oxygen getter material, an oxide, a ceramic, a composite material, or a group of Debye mismatch layers.

[0080] In Example 9, the subject matter of Example 8 can optionally include the oxide being selected from a group including Pb ₂ 03, Pb3C>4, and HfC>2.

[0081] In Example 10, the subject matter of Example 8 can optionally include the ceramic including hexagonal boron nitride (h-BN).

[0082] In Example 11, the subject matter of Example 8 can optionally include the group of Debye mismatch layers including yttrium-doped zinc oxide (YZO).

[0083] In Example 12, the subject matter of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, and/or Example 11 can optionally include each of the at least one thermal layer having a substantially uniform thickness having a magnitude in a range from about 0.5 nm to about 5.0 nm.

[0084] In Example 13, the subject matter of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, Example 11, and/or Example 12 can optionally include the first electrode layer including one or more of tungsten, platinum, silver, gold, palladium, copper, aluminum, titanium, tantalum, zinc, nickel, and wherein the second electrode layer comprises one or more of tungsten, platinum, silver, gold, palladium, copper, aluminum, titanium, tantalum, zinc, nickel.

[0085] In Example 14, the subject matter of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, Example 11, and/or Example 12, wherein the first electrode layer comprises a first conductive material including one or more of tungsten, platinum, silver, gold, palladium, copper, aluminum, titanium, tantalum, zinc, nickel, and wherein the second electrode layer comprises a second conductive material including one or more of tungsten, platinum, silver, gold, palladium, copper, aluminum, titanium, tantalum, zinc, nickel, the first conductive material being different from the second conductive material.

[0086] In Example 15, the subject matter of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Example 10, Example 11, and/or Example 12 can optionally include the first electrode layer including a doped semiconductor, and the second electrode layer including a metal, and wherein the second electrode layer comprises a metal, and the second electrode layer including a doped semiconductor. [0087] Example 16 is a method for a resistive switch device, the method including forming a first thermal layer that is electrically insulating and thermally resistive; forming a first electrode layer adjacent the first thermal layer, the first electrode layer having a first substantially planar interface with the first thermal layer; forming an oxide layer adjacent the first electrode layer, the oxide layer to form a conductive filament along a direction substantially perpendicular to the first substantially planar interface; forming an oxygen exchange layer adjacent the oxide layer, the oxygen exchange layer having a second substantially planar interface with the oxide layer; forming a second electrode layer adjacent the oxygen exchange layer, the second electrode layer having a third substantially planar interface with the oxygen exchange layer; and forming a second thermal layer adjacent the second electrode layer, the second thermal layer is electrically insulating and thermally resistive.

[0088] In Example 17, the subject matter of Example 16 can optionally include the forming the first thermal layer including depositing an amount of a conductive material on a substrate, the conductive material having an electrical resistivity in a first range from about 150 nfi'm to about 10 mQ m, the conductive material further having a thermal conductivity in a second range from about 0.1 W/(m K) to about 50 W/(mK).

[0089] In Example 18, the subject matter of Example 16 and/or Example 17 can optionally include the forming the second thermal layer comprises depositing an amount of a second conductive material on a surface of the second electrode layer, the second conductive material having an electrical resistivity in a third range from about 150 nQ m to about 10 mQ m, the second conductive material further having a thermal conductivity in a fourth range from about 0.1 W/(m K) to about 50 W/(m K).

[0090] In Example 19, the subject matter of Example 18 can optionally include the depositing the amount of the conductive material including implementing a physical deposition process to form a film of the conductive material, the film having a substantially uniform thickness of a magnitude in a range from about 0.5 nm to about 5 nm.

[0091] In Example 20, the subject matter of Example 18 can optionally include the depositing the amount of the second conductive material including implementing a physical deposition process to form a film of the second conductive material, the film having a second substantially uniform thickness of a second magnitude in a second range from about 0.5 nm to about 5 nm.

[0092] In Example 21, the subject matter of Example 16, Example 17, Example 18, Example 19, and/or Example 20 can optionally include the wherein the forming the first thermal layer comprises depositing at least one of a first amount of an oxygen getter material, a second amount of an oxide, a third amount of a ceramic, a fourth amount of a composite material, or a fifth amount of a group of Debye mismatch layers.

[0093] In Example 22, the subject matter of Example 16, Example 17, Example 18, Example 19, Example 20, and/or Example 21 can optionally include the forming the second thermal layer including depositing at least one of a first amount of an oxygen getter material, a second amount of an oxide, a third amount of a ceramic, a fourth amount of a composite material, or a fifth amount of a group of Debye mismatch layers.

[0094] Example 23 is a method for a resistive switch device, the method including forming a first electrode layer having a substantially planar surface; forming an oxide layer adjacent the first electrode layer, the oxide layer to form a conductive filament along a direction substantially perpendicular to the first substantially planar surface; forming an oxygen exchange layer adjacent the oxide layer, the oxygen exchange layer having a first substantially planar interface with the oxide layer; forming a second electrode layer adjacent the oxygen exchange layer, the second electrode layer having a second substantially planar interface with the oxygen exchange layer, resulting in a resistive switch assembly; and forming a conformal thermal layer on the resistive switch assembly.

[0095] In Example 24, the subject matter of Example 23 can optionally include the forming the conformal thermal layer including depositing an amount of a conductive material on a surface of the resistive switch assembly, the conductive material having an electrical resistivity in a first range from about 150 nQ m to about 10 mQ m, the conductive material further having a thermal conductivity in a second range from about 0.1 W/(m K) to about 50 W/(m K).

[0096] In Example 25, the subject matter of Example 24 can optionally include the depositing the amount of the conductive material including implementing an atomic layer deposition process to form a conformal film of the conductive material, the film having a substantially uniform thickness of a magnitude in a range from about 0.5 nm to about 5 nm.

[0097] In Example 26, the subject matter of Example 23, Example 24, and/or Example 25 can optionally include the forming the conformal thermal layer including depositing at least one of an amount of an oxygen getter material, an amount of an oxide, an amount of a ceramic, an amount of a composite material, or an amount of a group of Debye mismatch layers.

[0098] Example 27 is an electronic device including at least one semiconductor die having circuitry assembled therein, the circuitry comprising a plurality of solid-state devices, at least one of the plurality of solid-state devices comprising, at least one thermal layer, each of the at least one thermal layer being electrically insulating and thermally resistive; a first electrode positioned adjacent a first thermal layer of the at least one thermal layer, the first electrode forming a first substantially planar interface with the first thermal layer; an oxygen exchange layer positioned adjacent the first electrode and forming a second substantially planar interface with the first electrode; an oxide layer positioned adjacent the oxygen exchange layer, the oxide layer to form a conductive filament along a direction substantially perpendicular to the first substantially planar interface; and a second electrode positioned adjacent the oxide layer and forming a third substantially planar interface with the oxide layer.

[0099] In Example 28, the subject matter of Example 27 can optionally include at least one thermal layer including a second thermal layer, the first thermal layer having a thermal conductivity of a first magnitude in a range from about 0.1 W/(m K) to about 50 W/(m K), and the second thermal layer having a thermal conductivity of a second magnitude in the range from about 0.1 W/(m K) to about 50 W7(mK).

[0100] In Example 29, the subject matter of Example 27 and/or Example 28 can optionally include the at least one thermal layer including a second thermal layer positioned adjacent the second electrode and forming a fourth substantially planar interface with the second electrode, the fourth substantially planar interface is opposite to the third substantially planar interface with the oxide layer.

[0101] In Example 30, the subject matter of Example 27 and/or Example 28 can optionally include the at least one thermal layer comprises a second thermal layer and a third thermal layer substantially parallel to the second thermal layer, each of the second thermal layer and the third thermal layer is positioned adjacent the first electrode layer and the second electrode.

[0102] In Example 31, the subject matter of Example 30 can optionally include the second thermal layer and the third thermal layer both being in contact with the first electrode, the second electrode, the oxygen exchange layer, and the oxide layer.

[0103] In Example 32, the subject matter of Example 30 and/or Example 31 can optionally include the second thermal layer forming respective fourth substantially planar interfaces with the first electrode and the second electrode.

[0104] In Example 33, the subject matter of Example 30, Example 31, and/or Example 32 can optionally include the third thermal layer forms respective fifth substantially planar interfaces with the first electrode and the second electrode. [0105] In Example 34, the subject matter of Example 27 and/or Example 28 can optionally include the first thermal layer including at least one of a first oxygen getter material, a first oxide, a first ceramic, a first composite material, or a first group of Debye mismatch layers, and the second thermal layer including at least one of a second oxygen getter material, a second oxide, a second ceramic, a second composite material, or a second group of Debye mismatch layers.

[0106] In Example 35, the subject matter of Example 27, Example 28, and/or Example 34 can optionally include the at least one thermal layer including a second thermal layer including at least one of a second oxygen getter material, a second oxide, a second ceramic, a second composite material, or a second group of Debye mismatch layers.

[0107] In Example 36, the subject matter of Example 35 can optionally include the first oxide and the second oxide each being selected from a group including Pb203, Pb ₃ C>4, and Hf0 ₂ .

[0108] In Example 37, the subject matter of Example 35 can optionally include the first ceramic including hexagonal boron nitride (h-BN), and wherein the second ceramic comprises hexagonal boron nitride (h-BN).

[0109] In Example 38, the subject matter of Example 35 can optionally include the first group of Debye mismatch layers including yttrium-doped zinc oxide (YZO), and wherein the second group of Debye mismatch layers comprise yttrium-doped zinc oxide (YZO).

[0110] In Example 39, the subject matter of Example 27 can optionally include each of the at least one thermal layer having a substantially uniform thickness having a magnitude in a range from about 0.5 nm to about 5.0 nm.

[0111] As mentioned, unless otherwise expressly stated, it is in no way intended that any protocol, procedure, process, or method set forth herein be construed as requiring that its acts or steps be performed in a specific order. Accordingly, where a process or method claim does not actually recite an order to be followed by its acts or steps or it is not otherwise specifically recited in the claims or descriptions of the subject disclosure that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps or operational flow; plain meaning derived from grammatical organization or punctuation; the number or type of embodiments described in the specification or annexed drawings, or the like.

[0112] Conditional language, such as, among others, "can," "could," "might," or "may," unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain implementations could include, while other implementations do not include, certain features, elements, and/or operations. Thus, such conditional language generally is not intended to imply that features, elements, and/or operations are in any way required for one or more implementations or that one or more implementations necessarily include logic for deciding, with or without user input or prompting, whether these features, elements, and/or operations are included or are to be performed in any particular implementation.

[0113] As used herein, the term "substantially" indicates that each of the described dimensions is not a strict boundary or parameter and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the term "substantially" in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.

[0114] Further, certain relationships between dimensions of layers of a semiconductor device in accordance with this disclosure and between other elements of the semiconductor device are described herein using the term "substantially equal." As used herein, the term "substantially equal" indicates that the equal relationship is not a strict relationship and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the term "substantially equal" in connection with two or more described dimensions indicates that the equal relationship between the dimensions includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit of the dimensions. As used herein, the term "substantially constant" indicates that the constant relationship is not a strict relationship and does not exclude functionally similar variations therefrom.

[0115] As used herein, the term "substantially parallel" indicates that the parallel relationship is not a strict relationship and does not exclude functionally similar variations therefrom. As used herein the term "substantially perpendicular" indicates that the perpendicular relationship between two or more elements of a semiconductor device in accordance with this disclosure are not a strict relationship and does not exclude functionally similar variations therefrom.

[0116] The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (e.g., surface of a substrate), regardless of its orientation. The term "vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side"

(as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to the horizontal plane. The term "processing" as used herein is generally intended to include deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as

required in forming a described structure.

[0117] What has been described herein in the present specification and annexed drawings includes examples of resistive switch devices that include thermal layers and techniques for providing such devices. Some thermal layers can be embodied in or can include a material that is electrically conductive and thermally resistive. Other thermal layers can be electrically insulating and thermally resistive. It is, of course, not possible to describe every conceivable combination of elements and/or methodologies for purposes of describing the various features of the disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of the claimed subject matter are possible. Accordingly, it may be apparent that various modifications can be made to the disclosure without departing from the scope or spirit thereof. In addition or in the alternative, other embodiments of the disclosure may be apparent from consideration of the specification and annexed drawings, and practice of the disclosure as presented herein. It is intended that the examples put forward in the specification and annexed drawings be considered, in all respects, as illustrative and not restrictive. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.