Technical Field

[0001] This disclosure relates generally to the field of ferroelectricity, and more specifically, to thin film ferroelectric materials and methods of fabrication thereof.

Background

[0002] Dense low power embedded memory is used in many different computer products. Nonvolatile operation by embedded memory is a desirable attribute to reduce standby power.

However, known memories do not provide non-volatility, low power, and high switching speeds in one type of memory. For example, Static Random Access Memory (SRAM) is a high speed volatile memory but it consumes leakage power from an always-on power supply. Embedded Dynamic Random Access Memory (E-DRAM) is another high speed volatile memory that consumes dynamic power from refresh operations.

[0003] Lower standby power is exhibited by some non-volatile memories. For example, embedded Flash (eFlash), Magnetic Random Access Memory (MRAM), and Resistive Random Access Memory (RRAM) are non-volatile memories that exhibit low standby power but are unlikely to reach the performance level (i.e., SRAM-comparable fast read and write operations at low power) required for many applications. Further, endurance of current non-volatile memories is low and write energy too high.

[0004] Thin film ferroelectric (FE) materials, such as e.g. hafnium zirconium oxide (Hf _x Zr _y O _z ), also referred to as HZO or barium titanium oxide (BaTi0 ₃ , also referred to as BTO), have recently been considered for improving on at least some of these issues. However, improvements in ferroelectric behavior of such materials, e.g. higher remnant polarization, endurance cycles, and retention times, are still desirable.

Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIGS. 1A-1F provide schematic illustrations of different ferroelectric cells including an electrode and a ferroelectric stack having a templating layer, according to various embodiments of the present disclosure.

[0007] FIG. 2 is a flow diagram of an example method of manufacturing a memory device with a ferroelectric stack having a templating layer, in accordance with various embodiments. [0008] FIG. 3 is a schematic illustration of a ferroelectric cell that includes an electrode and a ferroelectric layer with network stabilizers, according to some embodiments of the present disclosure.

[0009] FIG. 4 is a flow diagram of an example method of manufacturing a memory device with a ferroelectric layer having network stabilizers, in accordance with various embodiments.

[0010] FIGS. 5A and 5B is a flow diagram of an example method of providing a ferroelectric layer with network stabilizers, in accordance with various embodiments.

[0011] FIG. 6 is a block diagram illustration of a 1T-1FE-CAP memory cell, according to some embodiments of the present disclosure.

[0012] FIG. 7 is a block diagram illustration of a 1T-1FE-FET memory cell, according to some embodiments of the present disclosure.

[0013] FIGS. 8A and 8B are top views of a wafer and dies that include one or more ferroelectric cells in accordance with any of the embodiments disclosed herein.

[0014] FIG. 9 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more ferroelectric cells in accordance with any of the embodiments disclosed herein.

[0015] FIG. 10 is a cross-sectional side view of an IC device assembly that may include one or more ferroelectric cells in accordance with any of the embodiments disclosed herein.

[0016] FIG. 11 is a block diagram of an example computing device that may include one or more ferroelectric cells in accordance with any of the embodiments disclosed herein.

Detailed Description

[0017] Described herein are ferroelectric materials for use in memory cells and corresponding methods and devices. Ferroelectric memory refers to a memory technology employing ferroelectric materials. A ferroelectric material is a material that exhibits, over some range of temperatures, a spontaneous electric polarization, i.e. displacement of positive and negative charges from their original position, which can be reversed or reoriented by application of an electric field. Because the displacement of the charges in ferroelectric materials can be maintained for some time even in the absence of an electric field, such materials may be used to implement memory cells. The term "ferroelectric" is said to be adopted to convey the similarity of ferroelectric memories to conventional ferromagnetic memories, despite the fact that there is no iron (Fe) in ferroelectric materials.

[0018] Ferroelectric memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high speed writing. In addition, ferroelectric memories have the advantage of being manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology used e.g. to manufacture logic devices, improving the integration of logic and memory devices on a single semiconductor substrate. Therefore, over the last few years, these types of memories have emerged as promising candidates for many growing applications such as e.g. digital cameras and contactless smart cards.

[0019] The performance of a ferroelectric memory device may depend on the number of factors. One factor is the ability of the device to prevent or minimize detrimental effects of voltages which may unintentionally disturb a polarization state that the device is supposed to hold. One approach to address this issue could include employing creative circuit architectures, e.g. by using access transistors to control access to ferroelectric cells, in order to overcome the shortcoming of the ferroelectric materials being used. Another approach is to improve ferroelectric behavior of the ferroelectric materials themselves.

[0020] Ferroelectric layer arrangements disclosed herein aim to improve the ferroelectric behavior, e.g. in terms of higher remnant polarization, endurance cycles, and retention times, of the ferroelectric materials used by improving the orthorhombic crystal structure of these materials. As is well-known, orthorhombic crystal system refers to one of the several crystal systems which differ in their crystallographic arrangement of crystal lattices. Having a larger percentage of a material with orthorhombic crystal structure is believed to result in an improved ferroelectric behavior. To that end, two approaches for providing thin film ferroelectric materials of ferroelectric cells for use in ferroelectric memory devices are proposed, where the term "ferroelectric cell" is used to describe a structure having at least one electrode and a layer of one or more ferroelectric materials

(hereafter: a "FE layer"). The first approach is based on using a templating layer in contact with the FE layer, the material of the templating layer being such that it imparts stress or strain, and/or provides nucleation sites that result in a conversion of the material(s) of the FE layer to the orthorhombic crystal structure, possibly upon annealing. The second approach is based on including network stabilizing materials (hereafter: "network stabilizers") within the FE layer to modify the overall crystallinity and crystalline phases of the FE layer. Both approaches may improve the orthorhombic crystal structure of the resulting FE layer (e.g. increase the percentage of the material that has orthorhombic crystal structure in the FE layer, decrease the amount of defects, etc.), leading to an improved ferroelectric behavior. In various embodiments, these approaches may be used in combination, as well as individually (i.e. in isolation, where only one of the two approaches is used).

[0021] The ferroelectric cells disclosed herein may be included in any type of devices which include ferroelectric memory cells. For example, the ferroelectric cells disclosed herein may be included in memory cells which employ ferroelectric cells in combination with access transistors, and may employ, or be used in combination with, either conventional planar or non-planar transistor architectures (examples of the latter including tri-gate or all-around gate transistors).

[0022] Furthermore, the ferroelectric cells described herein may be implemented in one or more components associated with an integrated circuit (IC) or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc.

Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

[0023] For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0024] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. The accompanying drawings are not necessarily drawn to scale. For example, to clarify various layers, structures, and regions, the thickness of some layers may be enlarged. Furthermore, while drawings illustrating various structures/assemblies of exemplary devices may be drawn with precise right angles and straight lines, real world process limitations may prevent implementations of devices exactly as shown. Therefore, it is understood that such drawings revised to reflect example real world process limitations, in that the features may not have precise right angles and straight lines, are within the scope of the present disclosure. Drawings revised in this manner may be more representative of real world structure/assemblies as may be seen on images using various characterization tools, such as e.g. scanning electron microscopy (SEM) or transmission electron microscopy (TEM). In addition, the various structures/assemblies of the present drawings may further include possible processing defects, such as e.g. the rounding of corners, the drooping of the layers/lines, unintentional gaps and/or discontinuities, uneven surfaces and volumes, etc., although these possible processing defects may not be specifically shown in the drawings. It is to be understood that other embodiments may be utilized and structural or logical changes to the drawings and descriptions may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0025] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0026] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0027] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. Furthermore, stating in the present disclosure that any part (e.g. a layer, film, area, or plate) is in any way positioned on or over (e.g. positioned on/over, provided on/over, located on/over, disposed on/over, formed on/over, etc.) another part means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located

therebetween. On the other hand, stating that any part is in contact with another part means that there is no intermediate part between the two parts.

[0028] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0029] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, as used herein, a "logic state" of a ferroelectric memory cell refers to one of a finite number of states that the cell can have, e.g. logic states "1" and "0," each state represented by a different polarization of the ferroelectric material of the cell. In another example, as used herein, a "READ" and "WRITE" memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell. In other examples, the term "connected" means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. In yet another example, a "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide. The terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc.

[0030] Each of FIGS. 1A-1F is a schematic illustration of a FE cell 100 that includes an electrode 102 and a FE stack 104 with a templating layer 106, according to various embodiments of the present disclosure. As shown in each of FIGS. 1A-1F, in addition to the templating layer 106, the stack 104 also includes a FE layer 108 of one or more ferroelectric materials (hence the names "FE stack 104" and "FE cell 100").

[0031] In general, implementations of the present disclosure may be formed or carried out on a substrate, such as a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the

semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on- insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V, group ll-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure. In various embodiments, the FE cell 100 of each of FIGS. 1A-1F may be provided on any such substrate that provides a suitable surface.

[0032] For each of FIGS. 1A-1F, the electrode 102 may include any material, or a stack of materials, which can serve as an electrode in a semiconductor device in which the FE cell 100 is used, e.g. as an electrode of a ferroelectric capacitor in which the FE stack 104 replaces, or is provided in addition to, a non-ferroelectric dielectric material provided between two electrodes of the capacitor, or as a gate electrode of a memory transistor in which the FE stack 104 replaces, or is provided in addition to, a non-ferroelectric gate insulator material used in logic transistors. Thus, in various embodiments, the electrode 102 may include one or more of metals which may include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), nitrides of these metals (e.g. hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, and aluminum nitride), and conductive metal oxides (e.g., ruthenium oxide). Further layers (not specifically shown in FIG. 1) may be included in contact with the electrode 102 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.

[0033] For each of FIGS. 1A-1F, the FE layer 108 may include any one or more of the materials exhibiting ferroelectric behavior at thin dimensions, such as e.g. hafnium zirconium oxide (Hf _x Zr _y O _z , also referred to as HZO, which is a material that includes hafnium, zirconium, and oxygen), silicon- doped (Si-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and silicon), germanium-doped (Ge-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and germanium), aluminum-doped (Al-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and aluminum), yttrium-doped (Y-doped) hafnium oxide (which is a material that includes hafnium, oxygen, and yttrium), and barium titanium oxide (BaTi0 ₃ , also referred to as BTO, which is a material that includes barium, titanium, and oxygen).

[0034] For each of FIGS. 1A-1F, the templating layer 106 may include any material that imparts stress or strain, and/or provides nucleation sites that result in a conversion of the material(s) of the FE layer 108 to an orthorhombic crystal structure, possibly upon annealing.

[0035] In some embodiments of each of FIGS. 1A-1F, the templating layer 106 may include or be a highly crystalline material, e.g. a material at least 80% of which is in a single crystal/monocrystalline form. Materials in a single crystal form are also referred to as "monocrystalline solids," i.e. materials in which the crystal lattice of the entire sample is continuous and unbroken to the edges of the sample, with no grain boundaries. An opposite of a monocrystalline solid is a fully amorphous material (i.e. no crystallinity at all). In between fully amorphous (no crystallinity) and single crystalline materials (100% single phase single orientation long range order with zero imperfections) there is a wide spectrum of materials with varying level of crystallinity. As used herein, the term "highly crystalline" refers to the materials at least 80% of which is in a single crystal/monocrystalline form but which may also include some defects (e.g. dislocations, grain boundaries, etc.), polycrystals, or other imperfections/issues which make the materials short of being single crystalline. Some examples of highly crystalline materials include crystalline oxides, such as e.g. magnesium oxide (MgO) (i.e. a material that includes magnesium and oxygen). Other examples of highly crystalline materials include two-dimensional (2D) materials (also referred to as "2D topological materials" or "single layer materials," i.e. crystalline materials which may be grown to be just a single layer of atoms due to all of the chemical bonding being directed in the plane of the atoms), such as e.g. graphene, graphite, or hexagonal boron nitride (hBN). The 2D materials may be advantageous because, due to the 2D nature of such materials, all bonds may be directed in the plane of the templating layer 106 and no dangling bonds may be left to interact and degrade the neighboring electrode 102 and the FE layer 108, and, additionally, a layer of a 2D material may act as a diffusion batter and is a non-reactive material, thus enabling increased stability of the FE cell 100 to thermal processing that may otherwise degrade a typical cell. Still other examples of highly crystalline materials which could be used as the templating layer 106 include transition metal dichalcogenides (TMDs), such as e.g. molybdenum disulfide (M0S2), molybdenum diselenide (MoSe2), molybdenum dite!luride (MoTe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), tungsten(IV) telluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), hafnium diteliuride (HfTe2), rhenium disulfide ( eS2), and rhenium diselenide ( eSe2). Some, but not all, of the TMDs may be 2D materials, while some, but not all, 2D materials may be TMDs.

[0036] In other embodiments of each of FIGS. 1A-1F, the templating layer 106 may include or be a polycrystalline material (also referred to as a "multicrystalline material" or a "polycrystal," i.e. a solid that is composed of many crystallites of varying size and orientation). Some examples of such materials include metals, metal nitrides, and metal carbides noted above, or various conducting or non-conducting metal oxides such as e.g. zirconium oxide, hafnium oxide, aluminum oxide, or yttrium oxide.

[0037] For each of FIGS. 1A-1F, in some embodiments, a thickness 116 of the templating layer 106 may be less than about 100 nanometers (nm), e.g. less than about 80 nm, or less than about 50 nm. In some embodiments, the thickness 116 may be as small as on a sub-nm scale, e.g. in case the templating layer 106 is made of a single layer of a 2D material. However, it is believed that it is not so much the thickness of the templating layer as it is the ability of its material(s) to impart stress, strain, and/or nucleation sites that result in a conversion of the FE layer to an orthorhombic crystal structure that is important for improving the FE properties of the resulting FE materials. Therefore, the thickness of the templating layer 106 may be in any range suitable for the functionality of the final device in which the FE cell 100 may be included. [0038] For each of FIGS. 1A-1F, in some embodiments, a thickness 118 of the FE layer 108 may be between about 1 and 30 nm, e.g. between about 1 and 20 nm, or between about 1 and 10 nm, as needed to achieve desired ferroelectric functionality of the FE cell 100.

[0039] What differentiates embodiments of FIGS. 1A-1F is the relative arrangement of the electrode 102, the templating layer 106, the FE layer 108, and additional layers 110 and 120, which differences will now be described.

[0040] In the embodiment shown in FIG. 1A, the FE cell 100 is such that the templating layer 106 separates the electrode 102 and the FE layer 108. Inventors of the present application realized that a bottom electrode, e.g. the electrode 102, plays an important role in the quality of crystalline material grown on top of it. Providing a highly crystalline, preferably a single crystalline or close thereto, layer over such an electrode as the templating layer 106 ensures that the ferroelectric material(s) of the FE layer 108 grown on top of it will adopt that crystallinity to a certain degree, resulting in an increased amount of orthorhombic crystallinity in the FE layer 108 and, therefore, improved ferroelectric behavior of the FE cell 100. In such an embodiment, after the deposition of the templating layer 106, an annealing operation may need to be carried out, to enable the change of the crystalline structure of the FE layer 108 through a high-temperature process. Such an annealing operation may e.g. include heating the structure to a temperature of 450 to 950 degrees Celsius, for a time period between 1 millisecond (ms) and 10 minutes.

[0041] On the other hand, FIG. IB illustrates an embodiment of the FE cell 100 where the templating layer 106 is provided as a top layer, over the FE layer 108. In such an embodiment, after the deposition of the templating layer 106, an annealing operation may need to be carried out, to enable the change of the crystalline structure of the FE layer 108 through a high-temperature process. The anneal would ensure that the ferroelectric material(s) of the FE layer 108 provided below the templating layer 106 will adopt the crystallinity of the top templating layer 106, resulting in an increased amount of orthorhombic crystallinity in the FE layer 108 and, therefore, improved ferroelectric behavior of the FE cell 100.

[0042] In other embodiments, the templating layer 106 as described above may be provided both below and above the FE layer 108, as is illustrated in FIG. 1C with a FE stack 104 including two such templating layers 106. The application of both top and bottom templating layers 106 may enable lower temperature thermal processing due to simultaneous change of the FE layer 108 upon thermal anneal.

[0043] Each of FIGS. 1A-1C further illustrates a layer 110 provided over the FE stack 104. In case the FE cell 100 of FIGS. 1A-1C is a part of a ferroelectric capacitor, the layer 110 could be a top electrode. In various embodiments, the top electrode of the layer 110 could include any of the materials described above for the electrode 102. In some embodiments, material composition of the top and bottom electrodes could be the same. In other embodiments, these electrodes could be of different materials.

[0044] While FIGS. 1A-1C illustrate the electrode 102 as a bottom electrode (i.e. the FE stack 104 is provided over such an electrode), FIGS. 1D-1F illustrate embodiments in which the electrode 102 as described above is a top electrode (i.e. the electrode 102 of each of the ferroelectric cells 100 shown in FIGS. 1D-1F is provided over the FE stack 104). In such embodiments, as shown in FIGS. 1D-1F, the FE stack 104 could be provided over a layer 120.

[0045] In some embodiments, the layer 120 could be a bottom electrode, e.g. in case the FE cell 100 of FIGS. 1D-1F is a part of a ferroelectric capacitor. In various embodiments, the bottom electrode of the layer 120 could include any of the materials described above for the electrode 102. Similar to FIGS. 1A-1C, for FIGS. 1D-1F, in some embodiments, material composition of the top and bottom electrodes could be the same, while, in other embodiments, these electrodes could be of different materials.

[0046] In other embodiments, the layer 120 could be a substrate, e.g. any of the substrates as described above, or any of the layers provided over the substrate.

[0047] In some embodiments, the layer 120 could include one or more semiconductor materials in which a channel of a metal-oxide-semiconductor (MOS) transistor will be formed during operation (these one or more semiconductor materials referred to in the following as a "channel material"), e.g. in case the FE cell 100 of FIGS. 1D-1F is a part of a ferroelectric transistor.

[0048] The channel material of the layer 120 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material may be formed of a substantially monocrystalline semiconductor. In some embodiments, the channel material may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may be a binary, ternary, or quaternary lll-V compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

[0049] For exemplary N-type transistor embodiments, the channel material of the layer 120 may advantageously be a lll-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary lll-V alloy, such as InGaAs or GaAsSb. For some ln _x Gai- _x As fin embodiments, In content in the channel material may be between 0.6 and 0.9, and advantageously at least 0.7 (e.g., lno.7Gao.3As). [0050] For exemplary P-type transistor embodiments, the channel material of the layer 120 may advantageously be a group IV material having a high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some exemplary embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously is at least 0.7.

[0051] In some embodiments, the channel material of the layer 120 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.

[0052] In some embodiments, the channel material of the layer 120 is an intrinsic lll-V or IV semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity- doped embodiments however, impurity dopant level within the channel material may be relatively low, for example below about 10 ¹⁵ cm ^"3 , and advantageously below 10 ¹³ cm ^"3 .

[0053] FE stacks having one or more templating layers disclosed herein, as well as memory devices including such stacks, may be manufactured using any suitable techniques. For example, FIG. 2 is a flow diagram of an example method 200 of manufacturing a memory device with a FE stack having at least one templating layer, in accordance with various embodiments. Although the operations of the method 200 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel e.g. to manufacture multiple memory devices substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a memory device in which a FE stack having at least one templating layer will be included.

[0054] At 202, a bottom electrode or a channel material is provided over a substrate. The bottom electrode provided at 202 may take the form of any of the embodiments of the bottom electrode 102 which is provided below the FE stack 104 (e.g. the embodiments shown in FIGS. 1A-1C).

Alternatively, the channel material provided at 202 may take the form of any of the embodiments of the channel material of the layer 120 which is provided below the FE stack 104 (e.g. the

embodiments shown in FIGS. 1D-1F). The bottom electrode or the channel material may be provided at 202 using any suitable deposition and/or patterning techniques known in the art, such as e.g. atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxial growth, various lithographic techniques such as e.g. photolithography or electron- beam lithography, and various etching techniques (e.g. to form the channel material to be of a desired shape - e.g. form the channel material as a fin extending away from a base in case the memory device is a ferroelectric FinFET, or to form the channel material as a wire in case the memory device is a ferroelectric all-around-gate FET).

[0055] At 204, a FE stack having one or more templating layers is provided over the bottom electrode or the channel material, whichever was provided at 202. The FE stack provided at 204 may take the form of any of the embodiments of the FE stack 104 described herein (e.g. the embodiments shown in FIGS. 1A-1F).

[0056] In case the FE stack provided at 204 is a FE stack that includes a bottom templating layer (i.e. a templating layer below the FE layer, as e.g. shown with the templating layer 106 of FIGS. 1A, 1C, ID, and IF), 204 may begin with providing such a templating layer over the bottom electrode or the channel material, whichever was provided at 202. To that end, various deposition techniques as known in the art may be used to provide a particular material, or a combination of materials, out of those described above with reference to the templating layer 106.

[0057] Continuing with the case that the FE stack provided at 204 is a FE stack that includes a bottom templating layer, once the bottom templating layer has been deposited over the bottom electrode or the channel material provided at 202, the FE layer of one or more ferroelectric materials may be provided. The templating layer provided below the deposition of the FE layer begins will now act as a template to promote an increase in the amount of orthorhombic crystal structure in the FE layer grown on top of it. It appears that the presence of stress/strain or uniform nucleation sites may be directly responsible for the change of the FE layer to higher orthorhombic concentrations.

[0058] A particular deposition technique for providing the FE layer at 204 would depend on a particular material, or a combination of materials, chosen to be used for that layer, and may include any of the techniques as known in the art for depositing thin film ferroelectrics. In case the approach of using one or more templating layers is used in combination with the second approach described later (i.e. the one using network stabilizers), then deposition of the FE layer at 204 may be performed as described below with reference to FIG. 4, where network stabilizing materials are included. Otherwise, deposition of the FE layer at 204 may also be performed as described below with reference to FIG. 4, but omitting operations of including the network stabilizing materials.

[0059] In case the FE stack provided at 204 is a FE stack that includes both a bottom and a top templating layers (i.e. templating layers both below and above the FE layer, as e.g. shown with the templating layer 106 of FIGS. 1C and IF), 204 may then proceed with providing a top templating layer over the FE layer, which may be done as described above for the bottom templating layer.

[0060] In case the FE stack provided at 204 is a FE stack that includes only a top templating layer (i.e. a templating layer above the FE layer, as e.g. shown with the templating layer 106 of FIGS. IB and IE), then, at 204, the deposition of the bottom layer as described above is omitted and 204 begins with providing the FE layer, as described above, followed by providing the top templating layer over the FE layer, which may be done as described above for the bottom templating layer.

[0061] As described above, in case a top templating layer is used, an annealing operation may need to be carried out, e.g. as a part of operation 204, after the top templating layer has been deposited, to enable the change the crystalline structure of the FE layer through a high-temperature process. Such an annealing operation may e.g. include heating the structure of 204 to a temperature of 450 to 950 degrees Celsius, for a time period between 1 millisecond (ms) and 10 minutes, to ensure that the ferroelectric material(s) of the FE layer provided below the top templating layer will adopt the crystallinity of the top templating layer. The same annealing conditions apply to ensure that the FE layer grown over a bottom templating layer adopts the crystalline structure of the bottom templating layer.

[0062] In the embodiments where a templating layer is used both below and above a FE layer, the same annealing conditions as those described above apply. The application of both top and bottom templating layers 106 may enable lower temperature thermal processing due to simultaneous change of the FE layer 108 upon thermal anneal. In various embodiments, the bottom and top templating materials may be the same or different.

[0063] Once the FE stack has been provided, at 206, a top electrode is provided over the FE stack. The top electrode provided at 206 may take the form of any of the embodiments of the top electrode 102 which is provided above the FE stack 104 (e.g. the embodiments shown in FIGS. 1D- 1F), and may be provided using any suitable deposition and/or patterning techniques known in the art for providing electrodes.

[0064] In various embodiments, various other operations as known in the art for semiconductor manufacturing processes may be performed before, after, or in between operations of the method 200 as shown in FIG. 2. Although these operations are not specifically described here, method 200 including such operations is within the scope of the present disclosure. For example, in some embodiments, a substrate, as well as a structure at each operation shown in FIG. 2 may be cleaned, e.g. to remove surface-bound organic and metallic contaminants, as well as subsurface

contamination. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with UV radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using HF). In another example, the substrate or/and a structure at each operation shown in FIG. 2 may be planarized/polished to make sure that the upper surface is sufficiently flat. In various embodiments, planarization/polishing may be performed using either wet or dry planarization processes. In some embodiments, planarization/polishing may be performed using chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

[0065] The templating layers 106 disclosed herein may be detectable in various devices using appropriate characterization tools. For example, Transmission Electron Microscopy (TEM) may be used to detect a templating layer 106 as a highly crystalline layer of one of the templating layer materials disclosed herein, and a second layer of the FE material (i.e. the FE layer 108) that is mostly in the orthorhombic phase. Visual observation of a cross sectional TEM will allow a trained user to observe continuous crystallinity across the FE layer and templating layer. When further combined with Energy-Dispersive X-ray spectroscopy (EDX) maps and line scans (capabilities present on TEMs), such an analysis will allow for the detection of dissimilar materials (i.e. the elements comprising the FE layer versus the templating layer).

[0066] Turning now to the second approach for providing thin film ferroelectric materials for use in ferroelectric memory devices, FIG. 3 is a schematic illustration of a ferroelectric cell 300 that includes a ferroelectric layer that makes use of network stabilizers, according to some embodiments of the present disclosure. The FE cell 300 is similar to the FE cell 100 as shown e.g. in FIGS. 1D-1F in that it includes the top electrode 102 and the bottom layer 120, as described above (which descriptions, in the interests of brevity, are not repeated here). In between the bottom layer 120 (which may be any of a substrate, a channel material, or a bottom electrode material) and the top electrode 102, a FE layer 308 is provided. The FE layer 308 may include any one or more of the materials exhibiting ferroelectric behavior at thin dimensions, as described above with reference to the FE layer 108, and may have a thickness as described above with reference to the thickness 118. Unlike the FE layer 108 described above, the FE layer 308 further includes network stabilizers 315 provided within the layer (as is schematically illustrated in FIG. 3 with white circles distributed through the FE layer 308), and is not necessarily used in combination with one or more templating layers 106 (although it may be used as the FE layer 108 in the first approach described above).

[0067] While FIG. 3 only labels one circle as a network stabilizer 315, all white circles shown in FIG. 3 represent such elements. Furthermore, while FIG. 3 illustrates a particular distribution of the network stabilizers 315 throughout the FE layer 308, this is only one illustrative example and, in various embodiments, any distribution of the network stabilizers 315 may be implemented, e.g. network stabilizers provided in more or less layers than what is shown in FIG. 3, or network stabilizers provided not in layers at all, but in a more random arrangement. In various embodiments, the network stabilizers 315 may include any materials/elements, or any combination of materials, which, when provided within the FE layer 308, allow to modify the crystallinity and crystalline phases of the FE layer 308 as to promote increased amount of orthorhombic orientation in the layer. With selection of proper network stabilizers and processing conditions (e.g. particular ways for adding the network stabilizers 315 during the deposition process for depositing the FE layer 308), it is possible to isolate the creation of and promote the orthorhombic crystalline phase which is credited for the ferroelectric behavior in thin film ferroelectric materials. In general, "network stabilizers" refer to molecules or compounds which create cross linked bonds within an amorphous or crystalline matrix, thus modifying that matrixes response to additional processing (e.g. thermal processing). In some embodiments, network stabilizers 315 may include network stabilizing materials from columns 1 and 2 of the periodic table, such as e.g. one or more of calcium (Ca), sodium (Na), potassium (K), and magnesium (Mg). In other embodiments, transition metals such as e.g. yttrium (Y), cerium (Ce), or scandium (Sc); group IV semiconductors such as e.g. silicon (Si) or germanium (Ge); or materials of lanthanide series such as e.g. gadolinium (Gd). In various embodiments, network stabilizers 315 may include more than one type of these exemplary elements, and may be used in their elemental form as well as in a form of various compounds of two or more of these elements, such as e.g. yttrium (Y), silicon (Si), and oxygen (O) to form a yttrium silicate interdispersed within the FE layer. Out of these elements, one or more of Mg, Y, Sc, Gd, and Si may be particularly advantageous due to their ability to incorporate into the FE layer with readily known deposition techniques (described above) and thermodynamic properties suitable to create strong network modifying bonds.

[0068] The amount of the network stabilizers used in the FE layer 308 may be selected based on the deposition equipment's ability to incorporate the modifiers (e.g. implanters will be a very low "dosage" whereas ALD/CVD can provide anywhere from <1% to >20%). In some embodiments, the FE layer 308 may contain anywhere between less than about 1% to about 20% or more of network stabilizers 315.

[0069] In some embodiments, the network stabilizers may be included within the FE layer 308 in layers, as shown with the example of FIG. 3, e.g. layers of about 1 nm thick (e.g. layers of about 0.3-3 nm thick), which may be controlled by e.g. controlling the amounts and the lengths of time various precursors are provided during e.g. an ALD growth of the FE layer 308 (some examples of which are described in greater detail below with reference to FIG. 4).

[0070] FE layers having one or more network stabilizing materials disclosed herein, as well as memory devices including such layers, may be manufactured using any suitable techniques. For example, FIG. 4 is a flow diagram of an example method 400 of manufacturing a memory device with a FE layer with network stabilizers, in accordance with various embodiments. Although the operations of the method 400 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel e.g. to manufacture multiple memory devices substantially

simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a memory device in which a FE layer with network stabilizers will be included.

[0071] At 402, a bottom electrode or a channel material is provided over a substrate. Descriptions provided above with reference to 202 are applicable to 402 and, therefore, in the interests of brevity, are not repeated.

[0072] At 404, a FE layer arrangement with network stabilizers therein is provided over the bottom electrode or the channel material, whichever was provided at 402. The FE layer arrangement provided at 404 may take the form of any of the embodiments of the FE layer 308 described herein (e.g. the embodiment shown in FIG. 3).

[0073] In the embodiments where one or more templating layers are also used, these layers may be provided at 404 as described above with reference to 204, where, in operation 404 of the method 400, the FE layer 308 replaces the FE layer 108 described above with reference to operation 204 of the method 200. Since descriptions related to providing the templating layers are applicable to such embodiments where the FE layer 308 is used instead of the FE layer 108, in the interests of brevity, these descriptions are not repeated.

[0074] As described above, particular deposition techniques for providing the FE layers would depend on a particular material, or a combination of materials, chosen to be used for that layer. One exemplary deposition technique is described below, but all of the deposition techniques which would result in deposition of the FE layer 308 with network stabilizers are within the scope of the present disclosure.

[0075] In some embodiments, ALD may be used to grow the FE layer 308. In general, ALD is a chemical process in which one or more reactive precursor gases (also referred to simply as

"precursors") are introduced into a reaction chamber and directed towards a substrate in order to induce controlled chemical reactions that result in growth of a desired material on the substrate. The one or more reactive gases may be provided to the chamber at a flow rate of e.g. 5 seem to 1000 seem, including all values and ranges therein. The reactive gas may be provided with a carrier gas, such as an inert gas, which may include, for example, argon. In some embodiments, the chamber may be maintained at a pressure in the range of 1 milliTorr to 100 Torr, including all values and ranges therein, and a temperature in the range of 60° C to 500° C, including all values and ranges therein. The substrate itself may also be heated. In some embodiments, the process may be plasma assisted where electrodes are provided within the process chamber and are used to ionize the gases. Alternatively, plasma may be formed outside of the chamber and then supplied into the chamber. In the chamber, a layer of solid thin film material is deposited on the surface of the substrate due to reaction of the gas/gasses.

[0076] For the example of the FE layer 308 to include HZO as the ferroelectric material stabilized with one of the network stabilizers described above, e.g. stabilized with yttrium (Y), four precursors may be used: 1) a hafnium (Hf) based precursor, 2) a zirconium (Zr) based precursor, 3) a network stabilizer based precursor (e.g. consider an example of using an yttrium (Y) network stabilizers 315, in which case an yttrium (Y) based precursor is used), and 4) water (H2O) or another appropriate oxidant. The ALD process of depositing the FE layer 308 may then be carried out as a method 500 shown in FIGS. 5A and 5B.

[0077] As shown in FIG. 5A, at 502, Hf-based precursor is provided to the ALD chamber. At 504, Hf- based precursor is purged from the ALD chamber. At 506, oxidant (e.g. water) is provided to the ALD chamber. At 508, the oxidant is purged from the ALD chamber. At 510, Zr-based precursor is provided to the ALD chamber. At 512, Zr-based precursor is purged from the ALD chamber. At 514, oxidant (e.g. water) is provided again o the ALD chamber. At 516, oxidant is purged from the ALD chamber. As shown with 518, operations 502-516 may be repeated a desired number of times to achieve a desired thickness of HZO layer grown as a result of these operations.

[0078] The method 500 may then continue as shown in FIG. 5B, where, at 520, Y-based precursor is provided to the ALD chamber. At 522, Y-based precursor is purged from the ALD chamber. At 524, oxidant (e.g. water) is provided to the ALD chamber. At 526, the oxidant is purged from the ALD chamber. As shown with 526, operations 520-526 may be repeated a desired number of times to achieve a desired amount of network stabilizer elements as a result of these operations. As shown with 530, operations 502-528 may be repeated a desired number of times to achieve a desired total thickness of the HZO layer with network stabilizers (i.e. thickness of the FE layer 318) grown as a result of these operations.

[0079] The relative ratios of the precursor gases provided to the ALD chamber, as well as the number of times the operations described above are performed may be selected depending on the desired proportions of the FE materials and network stabilizers present within the FE layer 308. For example, in some embodiments, about 80% of the FE layer 308 may be one or more FE materials, while the remaining about 20% may be the network stabilizers 315. In other embodiments, these values may be different, as suitable for a particular application, and depending on the actual materials used. In some embodiments, at least about 5% of the FE layer 308 may be the network stabilizers 315. In some embodiments, the network stabiliziers 315 may be provided in one or more layers, with each layer being between about 0.3 nm and a few nm (e.g. about 1-5 nm) thick. [0080] Operations similar to those shown in FIG. 5A may be used to grow a FE layer without network stabilizers, e.g. the FE layer 108 described above, where any suitable precursors may be used to deposit different FE materials as described herein.

[0081] Once the FE layer 308 is provided at 404, the substrate with the FE layer may be annealed in order to assist conversion of the deposited FE precursors to crystalline orthorhombic ferroelectric form. In some embodiments, the anneal may include heating the substrate with the FE layer to temperatures between about 450 and 1100 degrees Celsius, including all values and ranges therein. In various embodiments, such anneal may be a rapid thermal anneal (e.g. 1-3 seconds), or a flash anneal (e.g. for the time period on the order of sub-milliseconds to a few milliseconds). In some embodiments, such an anneal may be performed after the top electrode is provided at 406. In other embodiments, such an anneal may be performed before the top electrode is provided at 406.

[0082] At 406, a top electrode is provided over the FE layer 308. Descriptions provided above with reference to 206 are applicable to 406 and, therefore, in the interests of brevity, are not repeated.

[0083] In various embodiments, various other operations as known in the art for semiconductor manufacturing processes may be performed before, after, or in between operations of the method 400 as shown in FIG. 4. Although these operations are not specifically described here, method 400 including such operations is within the scope of the present disclosure. For example, in some embodiments, a substrate, as well as a structure at each operation shown in FIG. 4 may be cleaned or/and planarized/polished, as described above with reference to the method 200 of FIG. 2.

[0084] The network stabilizers 315 disclosed herein may be detectable in various devices using appropriate characterization tools. For example, the network stabilizers 315 may be detectable within a matrix of polycrystalline orthorhombic material of the FE layer 308 using Transmission Electron Microscopy (TEM) or Energy-Dispersive X-ray spectroscopy (EDX). Other methods such as e.g. X-ray Photoelectron Spectroscopy (XPS), Auger Electron Spectroscopy (AES), or Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIM) may also be used to detect presence, location, and/or amount of the network stabilizers present.

[0085] The FE cells disclosed herein, e.g. the FE cells 100 or 300 or a combination of these two types of FE cells, may be included in any suitable memory cells. FIGS. 6 and 7 illustrate two examples of such memory cells which may include one or more of the FE cells disclosed herein.

[0086] FIG. 6 is a block diagram illustration of a memory cell 600, according to some embodiments of the present disclosure. As shown, the memory cell 600 may include an access transistor 602 and a FE capacitor 604, and, hence, may be referred to as a "one transistor (T) and one ferroelectric capacitor (FE-CAP)" (1T-1FE-CAP) memory cell. [0087] The FE capacitor 604 may include any one of the FE cells 100 and 300 as described herein, or any combination thereof (i.e. any FE cell that includes both the one or more templating layers and network stabilizers). In particular, the FE capacitor 604 may be provided as two electrodes separated by a FE layer, where the electrodes may be provided as the electrode 102 and the electrode of the layer 120, and the FE layer sandwiched between the two capacitor electrodes may be provided as the FE stack 104 or the FE layer 308 (possibly with the one or more templating layers) described herein.

[0088] The access transistor 602 may be any metal oxide semiconductor (MOS) transistor which includes a drain, a source, and a gate terminals. In some embodiments, the access transistor 602 may be a field-effect transistor (FET). However, in other embodiments, other transistors, for example, bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used as the access transistor 602 without departing from the scope of the disclosure. The term "MN" may be used to indicate an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" may be used to indicate a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0089] Furthermore, in various embodiments, the access transistor 602 can have any planar or non- planar architecture, as suitable for a particular implementation. Recently, transistors with non- planar architecture, such as e.g. tri-gate and all-around gate transistors, have been extensively explored as promising alternatives to transistors with planar architecture.

[0090] Tri-gate transistors (also known as "FinFET transistors") refer to transistors having a non- planar architecture where a fin, formed of one or more semiconductor materials, extends away from a base. The name "tri-gate" originates from the fact that, in use, such a transistor may form conducting channels on three "sides" of the fin. Tri-gate transistors potentially improve

performance relative to single-gate transistors and double-gate transistors. In a tri-gate transistor, sides of a portion of a fin that is closest to a base are enclosed by a dielectric material, typically an oxide, commonly referred to as a "shallow trench isolation" (STI). The STI material may be a high-k dielectric including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the STI material may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. A gate stack that includes a stack of one or more gate electrode metals and a stack of one or more gate dielectrics is provided over the top and sides of the remaining upper portion of the fin (i.e. the portion above the STI), thus wrapping around the upper portion of the fin and forming a three-sided gate of a tri-gate transistor. The portion of the fin that is enclosed by the STI is referred to as a "sub-fin" while the portion of the fin over which the gate stack wraps around is referred to as a "channel" or a "channel portion." A semiconductor material of which the channel portion of the fin is formed is commonly referred to as a "channel material." A source region and a drain region are provided on the opposite ends of the fin, on either side of the gate stack, forming, respectively, a source and a drain of such a transistor.

[0091] All-around-gate transistors refer to transistors having a non-planar architecture where a wire (or nanoribbon), formed of a semiconductor material, is provided over a substrate. The semiconductor material of the wire is commonly referred to as a "channel material" because conducting channels of an all-around-gate transistor are formed within the wire. All-around-gate transistors potentially improve performance relative to tri-gate transistors because such transistors may form conducting channels on more than three "sides" of the wire. In an all-around-gate transistor, a gate stack that includes a stack of gate electrode metal(s) and a stack of gate dielectric(s) wraps around the wire, e.g. forming a four-sided gate of an all-around-gate transistor in case the wire has a rectangular cross-section. In various embodiments, a cross-section of a wire can have any shape besides a rectangular shape. A source region and a drain region are provided on the opposite ends of the wire, on either side of the gate stack, forming, respectively, a source and a drain of such a transistor.

[0092] Even though not specifically shown in FIG. 6, in some embodiments, the access transistor 602 may be a ferroelectric transistor, i.e. it may include the ferroelectric material layer such as the FE layer 308 or/and the FE stack 104 described herein. In some embodiments, such a ferroelectric layer/stack may be included in the gate stack of the access transistor 602, replacing or being provided in addition to the gate dielectric.

[0093] The access transistor 602 is used to control access to ferroelectric cell of the FE capacitor 604. To that end, one or more terminals of the access transistor 602 may be coupled to one or more electrodes of the FE capacitor 604. Furthermore, one or more terminals of the access transistor 602 and/or one or more electrodes of the FE capacitor 604 may be coupled to various control lines used for reading of data from and writing (i.e. programming) of data to the memory cell 600. Such control lines may e.g. include one or more word-lines (WL), one or more bit-lines (BL), and/or one or more ferroelectric-lines (FL). As known in the art, WL, BL, and FL may be used together to read and program the FE capacitor 604.

[0094] FIG. 7 is a block diagram illustration of a memory cell 700, according to some embodiments of the present disclosure. As shown, the memory cell 700 may include an access transistor 702 and a FE transistor 704, and, hence, may be referred to as a "one [access] transistor (T) and one ferroelectric transistor (FE-T)" (1T-1FE-T) memory cell.

[0095] Unless otherwise specified, descriptions provided with respect to the access transistor 602 are applicable to the access transistor 702 and, therefore, in the interests of brevity, are not repeated.

[0096] The FE transistor 704 may include any one of the FE cells 100 and 300 as described herein, or any combination thereof (i.e. any FE cell that includes both the one or more templating layers and network stabilizers). In particular, the FE transistor 704 may be a transistor similar to the access transistor 702, except that instead of the conventional non-ferroelectric gate dielectric typically included in a gate stack of such a transistor, the FE transistor 704 may include a FE layer, e.g. the FE stack 104 or the FE layer 308 (possibly with the one or more templating layers) described herein. Thus, the FE transistor 704 may include a gate electrode provided as the electrode 102 described herein and a channel material provided as the layer 120 described herein, with the FE layer/stack provided therebetween as a part of the gate stack of the transistor.

[0097] Similar to the access transistor 702, in various embodiments, the FE transistor 704 can have any planar or non-planar architecture, as suitable for a particular implementation. For example, the FE transistor 704 may be a tri-gate or an all-around gate transistor as described above.

[0098] Similar to the access transistor 602, even though not specifically shown in FIG. 7, in some embodiments, the access transistor 702 may be a ferroelectric transistor, i.e. it may include the ferroelectric material layer such as the FE layer 308 or/and the FE stack 104 described herein. In some embodiments, such a ferroelectric layer/stack may be included in the gate stack of the access transistor 702, replacing or being provided in addition to the gate dielectric.

[0099] The access transistor 702 is used to control access to ferroelectric cell of the FE transistor 704. To that end, one or more terminals of the access transistor 702 may be coupled to one or more terminals of the FE transistor 704. Furthermore, one or more terminals of the access transistor 702 and/or one or more terminals of the FE transistor 704 may be coupled to various control lines used for reading of data from and writing (i.e. programming) of data to the memory cell 700, such as e.g. one or more of WL, BL, and FL as described above, used together to read and program the FE transistor 704.

[0100] While descriptions presented herein refer to embodiments where the ferroelectric material 108 or 308 replaces a dielectric material provided between the two electrodes of a capacitor or a gate electrode and a channel material of a transistor, in other embodiments, such a material may be provided in addition to the conventional dielectric used between two electrodes of a capacitor or as a gate dielectric of a transistor, all of which embodiments being within the scope of the present disclosure.

[0101] Ferroelectric cells that include one or more templating layer(s) or/and network stabilizers included within a FE layer as disclosed herein may be included in any suitable electronic device. FIGS. 8-11 illustrate various examples of apparatuses that may include one or more of such FE cells.

[0102] FIGS. 8A-B are top views of a wafer 2000 and dies 2002 that may include one or more FE cells, or memory cells which include such FE cells, in accordance with any of the embodiments disclosed herein. The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more FE cells 100, one or more FE cells 300, or any other FE cells as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more FE cells 100, one or more FE cells 300, or any other FE cells as described herein, or after manufacture of any memory devices including such FE cells, such as e.g. after manufacture of one or more memory cells 600 or 700), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more FE cells as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include one or more transistors (e.g., one or more of the transistors 2140 of FIG. 9, discussed below, which may include any of the FE cells as described herein) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2302 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0103] FIG. 9 is a cross-sectional side view of an IC device 2100 that may include one or more FE cells, or memory cells which include such FE cells, in accordance with any of the embodiments disclosed herein. The IC device 2100 may be formed on a substrate 2102 (e.g., the wafer 2000 of FIG. 8A) and may be included in a die (e.g., the die 2002 of FIG. 8B). The substrate 2102 may be a semiconductor substrate composed of semiconductor material systems including, for example, N- type or P-type materials systems. The substrate 2102 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the semiconductor substrate 2102 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 2102. Although a few examples of materials from which the substrate 2102 may be formed are described here, any material that may serve as a foundation for an IC device 2100 may be used. The substrate 2102 may be part of a singulated die (e.g., the dies 2002 of FIG. 8B) or a wafer (e.g., the wafer 2000 of FIG. 8A).

[0104] The IC device 2100 may include one or more device layers 2104 disposed on the substrate 2102. The device layer 2104 may include features of one or more transistors 2140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2102. The device layer 2104 may include, for example, one or more source and/or drain (S/D) regions 2120, a gate 2122 to control current flow in the transistors 2140 between the S/D regions 2120, and one or more S/D contacts 2124 to route electrical signals to/from the S/D regions 2120. The transistors 2140 may include one or more FE cells as described herein. The transistors 2140 may further include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 2140 are not limited to the type and configuration depicted in FIG. 9 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or FinFETs, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. In particular, at least some of the one or more of the transistors 2140 may take the form of any of the transistors 602, 702, or 704 disclosed herein.

[0105] Each transistor 2140 may include a gate 2122 formed of at least two layers, a gate dielectric layer and a gate electrode layer. Generally, the gate dielectric layer of a transistor 2140 may include one layer or a stack of layers, and the one or more layers may include non-ferroelectric dielectrics such as e.g. silicon oxide, silicon dioxide, and/or a high-k dielectric material such as e.g. hafnium oxide. Additionally or alternatively, the gate dielectric layer of the transistor 2140 may take the form of any of the embodiments of the FE layer 308 or the FE layer 108 disclosed herein.

[0106] In some embodiments, when viewed as a cross section of the transistor 2140 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is

substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may include a V- shaped structure (e.g., when the fin of a FinFET does not have a "flat" upper surface, but instead has a rounded peak).

[0107] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0108] The S/D regions 2120 may be formed within the substrate 2102, e.g. adjacent to the gate 2122 of each transistor 2140 described herein. The S/D regions 2120 may be formed within the substrate 2102 using any suitable processes known in the art. For example, the S/D regions 2120 may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion- implanted into the substrate 2102 to form the S/D regions 2120. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 2102 may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D regions 2120. In some implementations, the S/D regions 2120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some

embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 2120 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 2120. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the substrate 2102 in which the material for the S/D regions 2120 is deposited.

[0109] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 2140 of the device layer 2104 through one or more interconnect layers disposed on the device layer 2104 (illustrated in FIG. 9 as interconnect layers 2106-2110). For example, electrically conductive features of the device layer 2104 (e.g., the gate 2122 and the S/D contacts 2124) may be electrically coupled with the interconnect structures 2128 of the interconnect layers 2106-2110. The one or more interconnect layers 2106-2110 may form an interlayer dielectric (ILD) stack 2119 of the IC device 2100.

[0110] The interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2128 depicted in FIG. 9). Although a particular number of interconnect layers 2106-1210 is depicted in FIG. 9, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0111] In some embodiments, the interconnect structures 2128 may include trench structures 2128a (sometimes referred to as "lines") and/or via structures 2128b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal. The trench structures 2128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2102 upon which the device layer 2104 is formed. For example, the trench structures 2128a may route electrical signals in a direction in and out of the page from the perspective of FIG. 9. The via structures 2128b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2102 upon which the device layer 2104 is formed. In some embodiments, the via structures 2128b may electrically couple trench structures 2128a of different interconnect layers 2106-2110 together.

[0112] The interconnect layers 2106-2110 may include a dielectric material 2126 disposed between the interconnect structures 2128, as shown in FIG. 9. In some embodiments, the dielectric material 2126 disposed between the interconnect structures 2128 in different ones of the interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the dielectric material 2126 between different interconnect layers 2106-2110 may be the same.

[0113] A first interconnect layer 2106 (referred to as Metal 1 or "M l") may be formed directly on the device layer 2104. In some embodiments, the first interconnect layer 2106 may include trench structures 2128a and/or via structures 2128b, as shown. The trench structures 2128a of the first interconnect layer 2106 may be coupled with contacts (e.g., the S/D contacts 2124) of the device layer 2104.

[0114] A second interconnect layer 2108 (referred to as Metal 2 or " M2") may be formed directly on the first interconnect layer 2106. In some embodiments, the second interconnect layer 2108 may include via structures 2128b to couple the trench structures 2128a of the second interconnect layer 2108 with the trench structures 2128a of the first interconnect layer 2106. Although the trench structures 2128a and the via structures 2128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2108) for the sake of clarity, the trench structures 2128a and the via structures 2128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0115] A third interconnect layer 2110 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2108 according to similar techniques and configurations described in connection with the second interconnect layer 2108 or the first interconnect layer 2106.

[0116] The IC device 2100 may include a solder resist material 2134 (e.g., polyimide or similar material) and one or more bond pads 2136 formed on the interconnect layers 2106-2110. The bond pads 2136 may be electrically coupled with the interconnect structures 2128 and configured to route the electrical signals of the transistor(s) 2140 to other external devices. For example, solder bonds may be formed on the one or more bond pads 2136 to mechanically and/or electrically couple a chip including the IC device 2100 with another component (e.g., a circuit board). The IC device 2100 may have other alternative configurations to route the electrical signals from the interconnect layers 2106-2110 than depicted in other embodiments. For example, the bond pads 2136 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

[0117] FIG. 10 is a cross-sectional side view of an IC device assembly 2200 that may include components having one or more FE cells, or memory cells which include such FE cells, in accordance with any of the embodiments disclosed herein. The IC device assembly 2200 includes a number of components disposed on a circuit board 2202 (which may be, e.g., a motherboard). The IC device assembly 2200 includes components disposed on a first face 2240 of the circuit board 2202 and an opposing second face 2242 of the circuit board 2202; generally, components may be disposed on one or both faces 2240 and 2242. In particular, any suitable components of the IC device assembly 2200 may include any of the FE cells in accordance with any of the embodiments disclosed herein.

[0118] In some embodiments, the circuit board 2202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2202. In other embodiments, the circuit board 2202 may be a non-PCB substrate.

[0119] The IC device assembly 2200 illustrated in FIG. 10 includes a package-on-interposer structure 2236 coupled to the first face 2240 of the circuit board 2202 by coupling components 2216. The coupling components 2216 may electrically and mechanically couple the package-on-interposer structure 2236 to the circuit board 2202, and may include solder balls (as shown in FIG. 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0120] The package-on-interposer structure 2236 may include an IC package 2220 coupled to an interposer 2204 by coupling components 2218. The coupling components 2218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2216. Although a single IC package 2220 is shown in FIG. 10, multiple IC packages may be coupled to the interposer 2204; indeed, additional interposers may be coupled to the interposer 2204. The interposer 2204 may provide an intervening substrate used to bridge the circuit board 2202 and the IC package 2220. The IC package 2220 may be or include, for example, a die (the die 2002 of FIG. 8B), an IC device (e.g., the IC device 2100 of FIG. 9), or any other suitable component. Generally, the interposer 2204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2204 may couple the IC package 2220 (e.g., a die) to a ball grid array (BGA) of the coupling components 2216 for coupling to the circuit board 2202. In the embodiment illustrated in FIG. 10, the IC package 2220 and the circuit board 2202 are attached to opposing sides of the interposer 2204; in other embodiments, the IC package 2220 and the circuit board 2202 may be attached to a same side of the interposer 2204. In some

embodiments, three or more components may be interconnected by way of the interposer 2204.

[0121] The interposer 2204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 2204 may include metal interconnects 2208 and vias 2210, including but not limited to through-silicon vias (TSVs) 2206. The interposer 2204 may further include embedded devices 2214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (M EMS) devices may also be formed on the interposer 2204. The package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.

[0122] The IC device assembly 2200 may include an IC package 2224 coupled to the first face 2240 of the circuit board 2202 by coupling components 2222. The coupling components 2222 may take the form of any of the embodiments discussed above with reference to the coupling components 2216, and the IC package 2224 may take the form of any of the embodiments discussed above with reference to the IC package 2220.

[0123] The IC device assembly 2200 illustrated in FIG. 10 includes a package-on-package structure 2234 coupled to the second face 2242 of the circuit board 2202 by coupling components 2228. The package-on-package structure 2234 may include an IC package 2226 and an IC package 2232 coupled together by coupling components 2230 such that the IC package 2226 is disposed between the circuit board 2202 and the IC package 2232. The coupling components 2228 and 2230 may take the form of any of the embodiments of the coupling components 2216 discussed above, and the IC packages 2226 and 2232 may take the form of any of the embodiments of the IC package 2220 discussed above. The package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.

[0124] FIG. 11 is a block diagram of an example computing device 2300 that may include one or more components including one or more FE cells or memory cells which include such FE cells in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2300 may include a die (e.g., the die 2002 (FIG. 8B)) having one or more FE cells in accordance with any of the embodiments disclosed herein. Any one or more of the components of the computing device 2300 may include, or be included in, an IC device 2100 (FIG. 9). Any one or more of the components of the computing device 2300 may include, or be included in, an IC device assembly 2200 (FIG. 10).

[0125] A number of components are illustrated in FIG. 11 as included in the computing device 2300, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2300 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0126] Additionally, in various embodiments, the computing device 2300 may not include one or more of the components illustrated in FIG. 11, but the computing device 2300 may include interface circuitry for coupling to the one or more components. For example, the computing device 2300 may not include a display device 2306, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2306 may be coupled. In another set of examples, the computing device 2300 may not include an audio input device 2318 or an audio output device 2308, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2318 or audio output device 2308 may be coupled. [0127] The computing device 2300 may include a processing device 2302 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2300 may include a memory 2304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2304 may include memory that shares a die with the processing device 2302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0128] In some embodiments, the computing device 2300 may include a communication chip 2312 (e.g., one or more communication chips). For example, the communication chip 2312 may be configured for managing wireless communications for the transfer of data to and from the computing device 2300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0129] The communication chip 2312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2312 may operate in accordance with other wireless protocols in other embodiments. The computing device 2300 may include an antenna 2322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0130] In some embodiments, the communication chip 2312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2312 may include multiple communication chips. For instance, a first communication chip 2312 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2312 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2312 may be dedicated to wireless communications, and a second communication chip 2312 may be dedicated to wired communications.

[0131] The computing device 2300 may include battery/power circuitry 2314. The battery/power circuitry 2314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2300 to an energy source separate from the computing device 2300 (e.g., AC line power).

[0132] The computing device 2300 may include a display device 2306 (or corresponding interface circuitry, as discussed above). The display device 2306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0133] The computing device 2300 may include an audio output device 2308 (or corresponding interface circuitry, as discussed above). The audio output device 2308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0134] The computing device 2300 may include an audio input device 2318 (or corresponding interface circuitry, as discussed above). The audio input device 2318 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). [0135] The computing device 2300 may include a global positioning system (GPS) device 2316 (or corresponding interface circuitry, as discussed above). The GPS device 2316 may be in

communication with a satellite-based system and may receive a location of the computing device 2300, as known in the art.

[0136] The computing device 2300 may include an other output device 2310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0137] The computing device 2300 may include an other input device 2320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFI D) reader.

[0138] The computing device 2300 may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2300 may be any other electronic device that processes data.

[0139] The following paragraphs provide various examples of the embodiments disclosed herein.

[0140] Example 1 provides ferroelectric (FE) stack arrangement including a FE layer including one or more thin film FE materials and a templating layer provided above or/and below the eventual FE layer, where at least 80% of the templating layer is substantially monocrystalline. In other words, the material of the templating layer is a highly crystalline material which may include large grain polycrystalline grains/domains with long range order approaching single crystallinity, leading to at least 80% of the material being in its monocrystalline form. In some embodiments, 100% of the material of the templating layer may be in its monocrystalline form (i.e. the templating layer may be a single crystal material).

[0141] Example 2 provides the FE stack arrangement according to Example 1, where the templating layer is a crystalline oxide.

[0142] Example 3 provides the FE stack arrangement according to Example 2, where the crystalline oxide is a material including magnesium and oxygen (e.g. magnesium oxide (MgO)). [0143] Example 4 provides the FE stack arrangement according to Example 1, where the templating layer is a two-dimensional material.

[0144] Example 5 provides the FE stack arrangement according to Examples 1 or 4, where the templating layer is a transition metal dichalcogenide.

[0145] Example 6 provides the FE stack arrangement according to Example 5, where the transition metal dichalcogenide is one or more of molybdenum disulfide (M0S2), molybdenum diseienide (MoSe2), mlybdenum ditelluride (MoTe2), tungsten disulfide (WS2), tungsten diseienide (WSe2), tungsten(IV) teliuride (WTe2), hafnium disulfide (HfS2), hafnium diseienide (HfSe2), hafnium ditelluride (HfTe2), rhenium disulfide ( eS2), and rhenium diseienide ( eSe2).

[0146] Example 7 provides the FE stack arrangement according to any one of the preceding Examples, where the one or more thin film FE materials include one or more of a material including hafnium, zirconium, and oxygen (e.g. HZO), a material including hafnium, silicon, and oxygen (e.g. silicon-doped hafnium oxide), a material including hafnium, germanium, and oxygen (e.g.

germanium-doped hafnium oxide), a material including hafnium, aluminum, and oxygen (e.g.

aluminum-doped hafnium oxide), a material including hafnium, yttrium, and oxygen (e.g. yttrium- doped hafnium oxide), and a material including barium, titanium, and oxygen (e.g. BTO).

[0147] Example 8 provides the FE stack arrangement according to any one of the preceding Examples, where the FE layer has a thickness between 1 nanometers and 10 nanometers.

[0148] Example 9 provides the FE stack arrangement according to any one of the preceding Examples, where the templating layer has a thickness less than 100 nanometers.

[0149] Example 10 provides the FE stack arrangement according to any one of the preceding Examples, where the FE layer includes network stabilizing materials, the network stabilizing materials including one or more of magnesium (Mg), yttrium (Y), scandium (Sc), gadolinium (Gd), and silicon (Si).

[0150] Example 11 provides the FE stack arrangement according to Example 10, where the network stabilizing materials are arranged in one or more layers, each layer of the network stabilizing materials enclosed between two layers of the one or more thin film FE materials.

[0151] Example 12 provides a memory device that includes a memory cell having a ferroelectric (FE) cell including at least a first electrode and a FE stack arrangement adjacent to (e.g. in contact with) the first electrode. The FE stack arrangement includes a FE layer including one or more thin film FE materials, and a templating layer above or/and below the FE layer, where at least 80% of the templating layer is substantially monocrystalline. [0152] Example 13 provides the memory device according to Example 12, where the memory cell further includes an access transistor having at least one terminal electrically coupled to the first electrode.

[0153] Example 14 provides the memory device according to Examples 12 or 13, where the FE cell is a FE capacitor, the first electrode is a first capacitor electrode, the FE capacitor further includes a second capacitor electrode, and the FE stack arrangement is provided between the first capacitor electrode and the second capacitor electrode. Thus, the memory cell may be a 1T-1FE-C ("one access transistor and one ferroelectric capacitor") memory cell.

[0154] Example 15 provides the memory device according to Examples 12 or 13, where the FE cell is a FE transistor, the first electrode is a gate electrode of the FE transistor, and the FE stack arrangement is provided over a channel material of the FE transistor. Thus, the memory cell may be a 1T-1FE-T ("one access transistor and one ferroelectric transistor") memory cell.

[0155] Example 16 provides the memory device according to Example 15, where the channel material is shaped as a fin extending away from a substrate and the gate electrode wraps around the fin, or the channel material is shaped as a wire disposed over the substrate and the gate electrode wraps around the wire.

[0156] Example 17 provides the memory device according to any one of Examples 12-16, where the templating layer is a crystalline oxide.

[0157] Example 18 provides the memory device according to Example 17, where the crystalline oxide is a material including magnesium and oxygen.

[0158] Example 19 provides the memory device according to any one of Examples 12-16, where the templating layer is a two-dimensional material.

[0159] Example 20 provides the memory device according to any one of Examples 12-16, where the templating layer is a transition metal dichalcogenide.

[0160] Example 21 provides the memory device according to any one of Examples 12-20, where the

FE layer includes network stabilizing materials, the network stabilizing materials including one or more of magnesium (Mg), yttrium (Y), scandium (Sc), gadolinium (Gd), and silicon (Si).

[0161] Example 22 provides the memory device according to Example 21, where the network stabilizing materials are arranged in one or more layers, each layer of the network stabilizing materials enclosed between two layers of the one or more thin film FE materials.

[0162] Example 23 provides a method of manufacturing a memory device, the method including providing a ferroelectric (FE) stack arrangement and providing at least a first electrode or a channel material adjacent to the FE stack arrangement. The FE stack arrangement includes a FE layer including one or more thin film FE materials, and a templating layer above or/and below the FE layer, where at least 80% of the templating layer is substantially monocrystalline.

[0163] Example 24 provides the method according to Example 23, where the templating layer is provided over the first electrode or the channel material and the FE layer is provided over the templating layer.

[0164] Example 25 provides the method according to Example 23, where the FE layer is provided over the first electrode or the channel material and the templating layer is provided over the FE layer.

[0165] Example 26 provides the method according to Example 25, further including performing an anneal following provision of the FE stack arrangement, thus providing a high-temperature process that enables the templating layer to change the crystalline structure of the FE layer underneath.

[0166] Example 27 provides the method according to any one of Examples 23-26, where providing the FE layer includes depositing the FE layer performing atomic layer deposition (ALD) using one or more first precursors for forming the one or more thin film FE materials.

[0167] Example 28 provides the method according to Example 27, further using an oxidant while performing the ALD.

[0168] Example 29 provides the method according to Examples 27 or 28, where the one or more first precursors include hafnium-based precursors and zirconium-based precursors.

[0169] Example 30 provides the method according to any one of Examples 27-29, further including using one or more second precursors for including network stabilizing materials within the FE layer.

[0170] Example 31 provides the method according to Example 30, where the one or more second precursors include one or more of magnesium-based precursors, yttrium-based precursors, scandium-based precursors, gadolinium-based precursors, and silicon-based precursors.

[0171] Example 32 provides the method according to Examples 30 or 31, further including purging the one or more first precursors from a chamber in which the ALD is performed prior to providing the one or more second precursors, and/or purging the one or more second precursors from the chamber prior to providing the one or more first precursors.

[0172] Example 33 provides the method according to any one of Examples 30-32, further including performing an anneal at temperatures between about 550 and 1000 degrees Celsius after providing the FE layer arrangement. Such an anneal may be a rapid thermal anneal (e.g. 1-3 seconds), or a flash anneal (e.g. for the time period on the order of sub-milliseconds to a few milliseconds).

[0173] Example 34 provides the method according to any one of Examples 30-33, where the network stabilizing materials are arranged in one or more layers, each layer of the network stabilizing materials enclosed between two layers of the one or more thin film FE materials. [0174] Example 35 provides a computing device, including a substrate, and an integrated circuit (IC) die coupled to the substrate, where the IC die includes a memory device including a plurality of memory cells, and where each memory cell includes a first electrode and a ferroelectric (FE) stack adjacent to (i.e. in contact with) the first electrode. The FE stack includes a FE layer including one or more thin film FE materials, and a templating layer above or/and below the FE layer, where at least 80% of the templating layer is substantially monocrystalline.

[0175] Example 36 provides the computing device according to Example 35, where each memory cell further has an access transistor having at least one terminal electrically coupled to the first electrode.

[0176] Example 37 provides the computing device according to Examples 35 or 36, where the FE stack is the FE stack arrangement according to any one of Examples 2-9.

[0177] Example 38 provides the computing device according to any one of Examples 35-37, where the each memory cell is memory device according to any one of Examples 10-22.

[0178] Example 39 provides the computing device according to any one of Examples 35-38, where the computing device is a wearable or handheld computing device.

[0179] Example 40 provides the computing device according to any one of Examples 35-39, where the computing device further includes one or more communication chips and an antenna.

[0180] Example 41 provides a ferroelectric (FE) layer arrangement including a FE layer including one or more thin film FE materials, where the FE layer includes at least about 5% of network stabilizing materials, the network stabilizing materials including one or more of magnesium (Mg), yttrium (Y), scandium (Sc), gadolinium (Gd), and silicon (Si).

[0181] Example 42 provides the FE layer arrangement according to Example 41, where the network stabilizing materials are arranged in one or more layers within the FE layer, each layer of the network stabilizing materials enclosed between two layers of the one or more thin film FE materials.

[0182] Example 43 provides the FE layer arrangement according to Example 42, where each layer of the network stabilizing materials has a thickness less than about 1 nanometer.

[0183] Example 44 provides the FE layer arrangement according to any one of Examples 41-43, where the FE layer has a thickness between 1 nanometers and 10 nanometers.

[0184] Example 45 provides the FE layer arrangement according to any one of Examples 41-44, where the one or more thin film FE materials include one or more of a material including hafnium, zirconium, and oxygen (e.g. HZO), a material including hafnium, silicon, and oxygen (e.g. silicon- doped hafnium oxide), a material including hafnium, germanium, and oxygen (e.g. germanium- doped hafnium oxide), a material including hafnium, aluminum, and oxygen (e.g. aluminum-doped hafnium oxide), a material including hafnium, yttrium, and oxygen (e.g. yttrium-doped hafnium oxide), and a material including barium, titanium, and oxygen (e.g. BTO).

[0185] Example 46 provides the FE layer arrangement according to any one of Examples 41-45, further including a templating layer provided above or/and below the eventual FE layer, where at least 80% of the templating layer is substantially monocrystalline.

[0186] Example 47 provides the FE layer arrangement according to Example 46, where the templating layer is a crystalline oxide.

[0187] Example 48 provides the FE layer arrangement according to Example 46, where the templating layer is a two-dimensional material.

[0188] Example 49 provides the FE layer arrangement according to Example 46, where the templating layer is a transition metal dichalcogenide.

[0189] Example 50 provides a memory device including a memory cell that includes a ferroelectric (FE) cell including at least a first electrode, and a FE layer arrangement provided over or under the first electrode. The FE layer arrangement within the FE cell includes a FE layer including one or more thin film FE materials, where the FE layer includes at least about 5% of network stabilizing materials, the network stabilizing materials including one or more of magnesium (Mg), yttrium (Y), scandium (Sc), gadolinium (Gd), and silicon (Si).

[0190] Example 51 provides the memory device according to Example 50, where the memory cell further includes an access transistor having at least one terminal electrically coupled to the first electrode.

[0191] Example 52 provides the memory device according to Examples 50 or 51, where the FE cell is a FE capacitor, the first electrode is a first capacitor electrode, the FE capacitor further includes a second capacitor electrode, and the FE layer arrangement is provided between the first capacitor electrode and the second capacitor electrode. Thus, the memory cell may be a 1T-1FE-C memory cell.

[0192] Example 53 provides the memory device according to Examples 50 or 51, where the FE cell is a FE transistor, the first electrode is a gate electrode of the FE transistor, and the FE layer arrangement is provided over a channel material of the FE transistor. Thus, the memory cell may be a 1T-1FE-T memory cell.

[0193] Example 54 provides the memory device according to Example 53, where the channel material is shaped as a fin extending away from a substrate and the gate electrode wraps around the fin, or the channel material is shaped as a wire disposed over the substrate and the gate electrode wraps around the wire. [0194] Example 55 provides the memory device according to any one of Examples 50-54, where the network stabilizing materials are arranged in one or more layers, each layer of the network stabilizing materials enclosed between two layers of the one or more thin film FE materials.

[0195] Example 56 provides the memory device according to Example 55, where each layer of the network stabilizing materials has a thickness less than about 1 nanometer.

[0196] Example 57 provides the memory device according to any one of Examples 50-56, where the FE layer has a thickness between 1 nanometers and 10 nanometers.

[0197] Example 58 provides the memory device according to any one of Examples 50-57, where the one or more thin film FE materials include one or more of a material including hafnium, zirconium, and oxygen (e.g. HZO), a material including hafnium, silicon, and oxygen (e.g. silicon-doped hafnium oxide), a material including hafnium, germanium, and oxygen (e.g. germanium-doped hafnium oxide), a material including hafnium, aluminum, and oxygen (e.g. aluminum-doped hafnium oxide), a material including hafnium, yttrium, and oxygen (e.g. yttrium-doped hafnium oxide), and a material including barium, titanium, and oxygen (e.g. BTO).

[0198] Example 59 provides the memory device according to any one of Examples 50-58, further including a templating layer above or/and below the FE layer, where at least 80% of the templating layer is substantially monocrystalline.

[0199] Example 60 provides the memory device according to Example 59, where the templating layer is a crystalline oxide.

[0200] Example 61 provides the memory device according to Example 60, where the crystalline oxide is a material including magnesium and oxygen (e.g. magnesium oxide (MgO)).

[0201] Example 62 provides the memory device according to Example 59, where the templating layer is a two-dimensional material.

[0202] Example 63 provides the memory device according to Example 59, where the templating layer is a transition metal dichalcogenide.

[0203] Example 64 provides a method of manufacturing a memory device, the method including providing a ferroelectric (FE) layer arrangement including a FE layer including one or more thin film FE materials, where the FE layer includes at least 5% of network stabilizing materials, the network stabilizing materials including one or more of magnesium (Mg), yttrium (Y), scandium (Sc), gadolinium (Gd), and silicon (Si); and providing at least a first electrode or a channel material adjacent to the FE layer arrangement.

[0204] Example 65 provides the method according to Example 64, further including providing a templating layer above or/and below the FE layer, where at least 80% of the templating layer is substantially monocrystalline. [0205] Example 66 provides the method according to Example 65, where the templating layer is provided over the first electrode or the channel material and the FE layer is provided over the templating layer.

[0206] Example 67 provides the method according to Example 65, where the FE layer is provided over the first electrode or the channel material and the templating layer is provided over the FE layer.

[0207] Example 68 provides the method according to Example 67, further including performing an anneal following provision of the templating layer.

[0208] Example 69 provides the method according to any one of Examples 64-68, where providing the FE layer arrangement includes depositing the FE layer performing atomic layer deposition (ALD) using one or more first precursors for forming the one or more thin film FE materials and one or more second precursors for including the network stabilizing materials within the FE layer.

[0209] Example 70 provides the method according to Example 69, further using an oxidant while performing the ALD.

[0210] Example 71 provides the method according to Examples 69 or 70, where the one or more first precursors include hafnium-based precursors and zirconium-based precursors.

[0211] Example 72 provides the method according to any one of Examples 69-71, where the one or more second precursors include one or more of magnesium-based precursors, yttrium-based precursors, scandium-based precursors, gadolinium-based precursors, and silicon-based precursors.

[0212] Example 73 provides the method according to any one of Examples 69-72, further including purging the one or more first precursors from a chamber in which the ALD is performed prior to providing the one or more second precursors, and/or purging the one or more second precursors from the chamber prior to providing the one or more first precursors.

[0213] Example 74 provides the method according to any one of Examples 64-73, further including performing an anneal at temperatures between about 550 and 1000 degrees Celsius after providing the FE layer arrangement.

[0214] Example 75 provides a computing device, including a substrate, and an integrated circuit (IC) die coupled to the substrate, where the IC die includes a memory device including a plurality of memory cells, each memory cell having a first electrode and a ferroelectric (FE) layer arrangement provided over or under the first electrode, where the FE layer arrangement includes a FE layer including one or more thin film FE materials, and where the FE layer includes at least 5% of network stabilizing materials, the network stabilizing materials including one or more of magnesium (Mg), yttrium (Y), scandium (Sc), gadolinium (Gd), and silicon (Si). [0215] Example 76 provides the computing device according to Example 75, where each memory cell further has an access transistor having at least one terminal electrically coupled to the first electrode.

[0216] Example 77 provides the computing device according to Examples 75 or 76, where the FE layer arrangement is the FE layer arrangement according to any one of Examples 42-49.

[0217] Example 78 provides the computing device according to any one of Examples 75-77, where the each memory cell is memory device according to any one of Examples 50-63.

[0218] Example 79 provides the computing device according to any one of Examples 75-78, where the computing device is a wearable or handheld computing device.

[0219] Example 80 provides the computing device according to any one of Examples 75-79, where the computing device further includes one or more communication chips and an antenna.

[0220] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0221] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.