[0001] This relates to processing of integrated circuit (IC) devices having thin film resistors and capacitors both within the metal stack, and such ICs therefrom.

BACKGROUND

[0002] Some IC devices include thin film resistors (TFRs). Silicon chromium (SiCr) has been used for years for TFRs due to its high electrical resistance in thin film form, relatively low temperature coefficient of resistance (TCR), and the ability to carry relatively high current densities. The TFRs are formed in backend of the line (BEOL) processing within the metal stack (e.g., between Metal 1 (Ml) and M2, or between M2 and M3) over functional circuitry formed in front of the line (FEOL) processing the semiconductor surface layer below. Such IC devices may also include capacitors within the metal stack known as metal-insulator-metal (MIM) capacitors.

SUMMARY

[0003] Described aspects include a method of fabricating IC devices having thin film resistors and capacitors both within the metal stack. At least one dielectric layer is deposited on a semiconductor surface layer on a substrate having a plurality the IC die formed in the semiconductor surface layer, with each IC die including functional circuitry comprising a plurality of interconnected transistors. A metal layer is formed over the dielectric layer for a bottom plate for a MIM capacitor defined herein to have respective plates separated by a capacitor dielectric layer(s) each plate comprising at least one metal.

[0004] At least one capacitor dielectric layer is deposited on the metal layer. A TFR layer comprising at least one metal is deposited on the capacitor dielectric layer. A pattern is formed on the TFR layer. The TFR layer is etched using the pattern including defining a top plate comprising the TFR layer on the capacitor dielectric layer and to define a TFR layer portion lateral to the MIM capacitor to form a resistor comprising the TFR layer (referred to herein as a ‘TFR’). A pattern is formed on the capacitor dielectric layer, the capacitor dielectric layer is etched, and the metal layer is then etched to define the bottom plate to complete the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a flow chart that shows steps in an example method of fabricating ICs including at least one TFR and at least one MIM capacitor, where the same TFR layer is used at a single mask level to form the TFR and also to form a top plate for the MIM capacitor, according to an example aspect.

[0006] FIGS. 2A-2I are cross-sectional diagrams showing processing progression for an example method of forming an IC having at least one TFR and at least one MIM capacitor, where the same TFR layer is used as to form the TFR and for the top plate of the MIM capacitor, according to an example aspect.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0007] The drawings are not necessarily drawn to scale. In the drawings, like reference numerals designate similar or equivalent elements. In the drawings and this description, illustrated ordering of acts or events is not limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may be optional to implement a methodology in accordance with this description.

[0008] The terms "coupled to" or "couples with" (and the like) as used herein without further qualification describe either an indirect or direct electrical connection. Thus, if a first device "couples" to a second device, that connection can be through a direct electrical connection where only parasitics are in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal, but may adjust its current level, voltage level and/or power level.

[0009] FIG. 1 is a flow chart that shows steps in an example method 100 of fabricating ICs including at least TFR and at least one MIM capacitor, where the same TFR layer is used at a single mask level to form the TFR and also to form a top plate of the MIM capacitor, according to an example aspect. Step 101 comprises depositing at least one dielectric layer on a substrate (e.g., a wafer) including a semiconductor surface layer having a plurality of IC die formed therein with each IC die including functional circuitry comprising a plurality of interconnected transistors. The substrate can comprise a bulk substrate material such as silicon, or an epitaxial layer on a bulk substrate material (see substrate 208 with semiconductor surface layer 209, with functional circuitry 180 formed in the semiconductor surface layer 209 in FIGS. 2A-2I). Alternatively, the substrate can comprise silicon-germanium, other Group 4 material, or other semiconductor materials including III-V and II- VI compound semiconductor materials.

[0010] Functional circuitry as used herein realizes and carries out a desired functionality, such as that of a digital IC (e.g., digital signal processor) or analog IC (e.g., amplifier or power converter), and in one aspect a BiCMOS (MOS and Bipolar) IC. The capability of functional circuitry provided on a described IC may vary, for example ranging from a simple device to a complex device. The specific functionality contained within functional circuitry is not of importance to described ICs. The functional circuitry (see functional circuitry 180 in FIGS. 2A-2I described below) is generally formed in the substrate before forming the TFRs described below.

[0011] FIG. 2 A shows an in-process IC die after step 101 showing a dielectric layer 230 on a semiconductor surface layer 209 on a substrate 208 that has a plurality of IC die formed in the semiconductor surface layer 209 with the IC die including functional circuitry 180 comprising a plurality of interconnected transistors. The dielectric layer 230 electrically isolates FEOL components on the IC from its BEOL interconnections and components.

[0012] The dielectric layer 230 shown in FIGS. 2A-2I is a pre-metal dielectric (PMD) layer so that the bottom plate of the MIM capacitor is described in FIGS. 2A-2I as being metal 1 (Ml). However, the dielectric layer directly under the bottom plate of the MIM capacitor can also be an inter level dielectric (ILD) layer so that the bottom plate of the MIM capacitor can also be M2, M3, or up to the top M layer -1 M layer. The dielectric layer 230 can comprise a tetraethoxysilane (TEOS)-derived silicon oxide layer. A TEOS deposition for a non-plasma deposition process can comprise low pressure CVD (LPCVD) at a pressure of about 300 mTorr and at a temperature of about 700°C. However, other dielectric layers can also be used including deposited silicon oxides, such as comprising an organosilicate glass (OSG), a low-k dielectric (i.e., a smaller dielectric constant relative to silicon dioxide), a doped dielectric layer such as a fluorine-doped silica glass (FSG), or a SiN layer or its variants (e.g., SiON). The thickness range for the dielectric layer 230 is generally from 6,000A to 8,000A for a PMD layer and 1.0 to 1.4 pm for an ILD layer.

[0013] Step 102 comprises forming a metal layer 240 over the dielectric layer 230 that will include use as a bottom plate for a capacitor. FIG. 2B shows the in-process IC die after step 102 showing the metal layer 240 over the dielectric layer 230. The metal layer 240 can comprise AlCu, usually with 0.5 to 4 wt. % copper. Alternatively, the metal layer 240 can comprise only copper in which case a damascene process is generally performed (a damascene process is not shown in FIGS. 2A-2I).

[0014] Step 103 comprises depositing at least one capacitor dielectric layer 245 on the metal layer 240. FIG. 2C shows the in-process IC die after step 103 showing at least one capacitor dielectric layer 245 on the metal layer 240. The thickness of the capacitor dielectric layer(s) is generally 200A to 2,000A, and can be a single layer or comprise 2 or more layers. The dielectric stack can include at least one silicon nitride layer. In one embodiment the capacitor dielectric layer 245 comprises a silicon oxide-silicon nitride (SiN)-silicon oxide (ONO) stack, where the ONO stack can function as an anti -reflectance coating (ARC) for the below-described bottom metal plate photolithography and patterning.

[0015] Step 104 comprises depositing a TFR layer comprising at least one metal on the capacitor dielectric layer 245. The TFR layer deposition process can comprise a direct current (DC) or radio frequency (RF) sputtering process. FIG. 2D shows the in-process IC die after step 104 showing the TFR layer 260 on the capacitor dielectric layer 245. The TFR layer 260 can comprise SiCr or its alloys such as carbon containing including SiCCr, SiCOCr where C can be 1 atomic % to 50 atomic %, or NiCr or its alloys such as NiCrFe 61% Ni, 15% Cr, 24% Fe (all atomic %’s). The thickness of the TFR layer 260 is generally 10 nm to 100 nm, such as 25 nm to 35 nm thick, or about 30 nm thick in one specific aspect.

[0016] Step 105 comprises forming a first pattern on the TFR layer 260. FIG. 2E shows the in- process IC die after forming a pattern shown as a photoresist (PR) pattern 270 on the TFR layer 260. Step 106 comprises etching the TFR layer 260 using the PR pattern 270 to simultaneously define a top plate for the capacitors comprising the TFR layer shown as TFR portion 260a on the capacitor dielectric layer 245 and to define a patterned resistor comprising the TFR layer shown as TFR portion 260b positioned lateral to the capacitors. FIG. 2F shows the in-process IC die after etching the TFR layer 260. The etch gases used for plasma etching the TFR layer 260 generally include flowing 0 ₂ , Cl ₂ , and at least one carbon-halogen gas. For example, 0 ₂ Cl ₂ and CF ₄ with optional Ar may be used for etching SiCr. In addition other gasses may also be used for etching the TFR layer 260 such as CHF ₃ , OR CH ₂ F ₂ as a replacement for or in addition to CF ₄ , and/or N ₂ used as well.

[0017] Step 107 comprises forming a second pattern on the capacitor dielectric layer 245 and then etching the capacitor dielectric layer 245 and the metal layer 240 to define the bottom plate to complete the MIM capacitor. For this patterning the capacitor dielectric layer 245 can act as an anti-reflection coating (ARC), particularly when it includes silicon nitride or silicon oxynitride. The metal wiring needed for connections to the functional circuitry 180 is also generally defined as well in the step 107 etching of the metal layer 240.

[0018] FIG. 2G shows the in-process IC die after etching the capacitor dielectric layer 245 and the metal layer 240 thereunder to define the bottom plate to complete the MIM capacitor. The pattern used for step 107 provides a larger area for defining the capacitor dielectric layer 245 and the metal layer 240 for the MIM capacitor as compared to the area of the TFR portion 260a for the MIM capacitor (after step 106, TFR layer etching) to provide locations to place a via (shown as via lands 278 below) for contacting the bottom plate of the MIM capacitor comprising metal layer 240.

[0019] Optionally a hardmask/etch stop layer can be deposited on the TFR layer 260 before its patterning (before step 105). The hardmask/etch stop layer can comprise a LPCVD process at a pressure of about 300 mTorr and at a temperature of about 700°C for a TEOS-based deposition. The hardmask/etch stop layer thickness range can be 50A to l,500A. Such a hardmask/etch stop layer may not be needed if the TFR etching process includes essentially no over etch of the TFR layer 260. A top silicon oxide layer in an ONO stack for the capacitor dielectric layer 245 may work as an etch stop for the TFR layer 260.

[0020] FIG. 2H shows the in-process IC die after depositing an ILD layer shown as ILD layer 265 then planarizing the wafer surface, such as using chemical mechanical polishing (CMP). FIG. 21 shows the in-process IC die after etching vias in the ILD layer 265 and then filling the vias with an electrically conductive material (such as W) to form vias lands 278. Shown in FIG. 21 on the IC 295 are a MIM capacitor 280, a MIM capacitor 285, and TFR 290 comprising a TFR portion 260b, with a patterned metal layer 275 over the via lands 278. Although not shown, the MIM capacitors 280, 285 and the TFR 290 are connected to nodes within the functional circuitry 180. Because the TFR layer 260 and capacitor dielectric layer 245 are generally both thin, a single contact process can be used to contact both the bottom plate of the MIM capacitors 280, 285 and the TFR 290 comprising the TFR layer. This is because of a height difference for via etch in the capacitor region versus standard metal 1 circuitry is small. This may also eliminate the need to have a hardmask layer over the TFR layer. [0021] The wafer processing can then then be completed by conventional BEOL processing comprising forming one or more additional metal levels thereon including a top metal level. The top metal layer can comprise aluminum (or an aluminum alloy) or copper. Passivation overcoat (PO) then generally follows, followed by patterning the PO. The PO layer comprises at least one dielectric layer such as silicon oxide, silicon nitride, or SiON.

[0022] Advantages of described processing include:

1. Allows the contact to the MIM capacitor(s) and the resistor comprising the TFR layer to be provided in the same mask level.

2. Eliminates the cost of 1 mask and added cycle time by using the TFR layer as the top plate of the MIM capacitor.

3. Allows thinning of the TFR layer to provide a higher sheet resistance available to IC designers.

4. Allow thinning or the elimination of a via etch stop layer on top of the TFR layer.

5. Improves the process window for metal (capacitor bottom plate and interconnect) patterning.

6. Eliminates or significantly reduces unexpected parasitic capacitor as compared to a MIM capacitor having a TiN top plate caused by post-etch TiN notches.

7. Provides relaxation of keep out zone design rules and spacing rules between metal lines which will benefit IC designers because of a thinner top plate for the MIM capacitors as compared to MIM capacitors with a thicker top plate material such TiN, and etch selectivity for the top plate material such as when the TFR layer is a chromium alloy (e.g., SiCr) relaxing the spacing rules between metal lines.

EXAMPLES

[0023] For a current baseline BEOL process for forming a MIM capacitor with a TiN top plate, the top plate thickness was found to have an 85% variation across a wafer. For described processing forming the MIM capacitor’s top plate from the TFR layer, the top plate thickness had only a 12% variation across a wafer. TiN and TFR resistor segments with different width to length (W/L) combinations were tested and sheet resistances were extracted for each die location on the wafer. Sheet resistance variation was evaluated as 6-sigma of the sheet resistance divided by mean. The sheet resistance was directly translated to thickness variation. Cross sectional images of the capacitors were also collected to validate these measurements.

[0024] Described aspects can be used to form semiconductor die that may be integrated into a variety of assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

[0025] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.