Title:
THIN-FILM TRANSISTOR ARRAY, THIN-FILM TRANSISTOR ARRAY MULTIPLE-SURFACE MOUNTING SUBSTRATE, AND METHOD OF MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2019/203200
Kind Code:
A1
Abstract:
Provided are a thin-film transistor array with which it is possible to obtain a high level of freedom of wiring design and stable characteristics, a thin-film transistor array multiple-surface mounting substrate using the same, and a method of manufacturing the above at low cost. The thin-film transistor array includes at least: an insulating substrate; a pixel pattern region in which thin-film transistor elements including a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a semiconductor layer formed in a channel region between the source electrode and the drain electrode are arranged in a matrix; and a plurality of extraction electrodes electrically connected to the source electrode of a plurality of thin-film transistor elements arranged linearly in the pixel pattern region. The semiconductor layer is formed of a part of a plurality of stripe patterns obtained by forming a semiconductor material in a stripe shape parallel to a direction in which the linearly arranged plurality of thin-film transistor elements are arranged, wherein the stripe patterns and the extraction electrodes are formed in different layers.
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Inventors:
NISHIZAWA MAKOTO
Application Number:
PCT/JP2019/016206
Publication Date:
October 24, 2019
Filing Date:
April 15, 2019
Export Citation:
Assignee:
TOPPAN PRINTING CO LTD (JP)
International Classes:
H01L29/786; G09F9/00; G09F9/30; H01L21/336
Foreign References:
| JP2013211446A | 2013-10-10 | |||
| JP2016001687A | 2016-01-07 | |||
| JP2009076877A | 2009-04-09 | |||
| JP2015197633A | 2015-11-09 |
Attorney, Agent or Firm:
OGASAWARA PATENT OFFICE (JP)
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