BACKGROUND

Spin-transfer torque (STT) magnetic random-access memory (MRAM) is one of the leading candidates for emerging embedded memory in future system on a chip (SoC) technologies. STT-MRAM shows the promise of non-volatile data storage, high cycling endurance suitable for working memory, short write time, and high memory density. STT- MRAM uses STT magnetic tunnel junction (MTJ) devices to store the data. Such MTJs can be embedded in the lower interconnect layers to achieve high memory density and robust connectivity to selector transistors below. However, the material stack of STT MTJ technology has significant considerations for the thermal budget of a back end of line (BEOL) process. For example, the rapid increase of lower metal layer resistance has become one of the major scaling challenges for STT-MRAM, which uses the change of resistance value of the memory device to determine the logic state of the memory cell. Higher bitline and source line resistance adds parasitic resistance to the device resistance and reduces the margin to correctly sense the low and high states. Further, the processing temperature of lower metal layers has been increasing rapidly to support the smaller metal pitch in the newer process nodes. These higher processing temperatures have severely affected the functionality of MTJ technology, which only works in a particular thermal budget (such as under 400 °C). Accordingly, it is becoming increasingly challenging to integrate STT-MRAM in an advanced process node (such as 10 nanometer (nm), 7 nm, 5 nm, and beyond) due to the increasing processing temperature of the BEOL process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an example STT-MRAM, according to an embodiment of the present disclosure.

FIGs. 2A-2B are cross-sectional views of an example STT-MRAM memory cell, according to an embodiment of the present disclosure.

FIG. 3 is a cross-sectional view of an example STT MTJ, according to an embodiment of the present disclosure.

FIG. 4 illustrates an example method of fabricating an STT-MRAM memory cell, according to an embodiment of the present disclosure. FIG. 5 illustrates an example method of fabricating an STT-MRAM including memory cells at crossing regions of wordlines and bitlines, according to an embodiment of the present disclosure.

FIG. 6 illustrates an example computing system implemented with the integrated circuit structures or techniques disclosed herein, according to an embodiment of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

An embedded spin-transfer torque magnetic random-access memory (STT-MRAM) memory cell is provided. In an embodiment, the memory cell includes: a wordline to supply a gate signal; a selector thin-film transistor (TFT), a source line, a short metal stub, an STT magnetic tunnel junction (MTJ), and a bitline. The selector TFT includes an active layer and is configured to electrically connect a first region of the active layer to a second region of the active layer in response to the gate signal. The selector TFT is above the wordline. This source line is coupled to and above the first region of the active layer. The short metal stub is coupled to and above the second region of the active layer. The STT MTJ is coupled to and above the short metal stub and configured to store a memory state. The bitline is coupled to and above the MTJ to transfer the memory state in conjunction with the source line. In an embodiment, the memory cell further includes a capping layer coupled to and between the MTJ and the bitline. An embedded STT-MRAM is also provided. In an embodiment, the STT-MRAM includes wordlines extending in a first direction to supply a gate signal, source lines and bitlines extending in a second direction crossing the first direction to transfer memory states of the STT- MRAM, and memory cells at regions where the wordlines cross the source lines and the bitlines. In another embodiment, the STT-MRAM further includes a control circuit below the wordlines to drive the wordlines, the source lines, and the bitlines.

General Overview

An STT-MRAM memory cell includes a spin-transfer torque (STT) magnetic tunnel junction (MTJ) for storing a bit (logical 1 or 0) and a selector transistor. The MTJ fabrication technology has a relatively tight thermal budget (such as under 400 °C). This is being challenged by advanced process nodes, which continue to increase the fabrication temperatures to meet the smaller pitch requirements of the process nodes, especially in the lower levels of fabrication, such as the front end of line (FEOL, or device level) and lower metal layers of the back end of line (BEOL, or interconnect levels). These layers also suffer from increasing resistance in their signal lines due to factors such as smaller feature sizes, which further degrades STT-MRAM performance when the memory cells are fabricated in these layers (such as fabricating the selector transistors and source lines in the FEOL, or fabricating the bitlines in the lower interconnect layers).

Thus, and in accordance with an embodiment of the present disclosure, an MTJ with improved thermal budget window is provided to address the thermal budget challenges of MTJ technology. In further detail, in one or more embodiments of the present disclosure, an indium gallium zinc oxide (IGZO) based field-effect transistor (FET) is provided with performance suitable for logic and memory applications. Given the low process temperature requirement, an IGZO transistor can be embedded in the interconnect (such as the BEOL) of a modern CMOS process, such as in the higher metal interconnect layers (with lower processing temperature requirements and less resistance in the signals lines). This allows one or more embodiments of the present disclosure to embed entire STT-MRAM memory arrays, including the memory devices and selector transistors, all in the upper interconnect and without using logic (e.g., FEOL) transistors and the lower metal interconnect layers. According to one or more embodiments of the present disclosure, with both the selector transistor and the memory device embedded in the interconnect (e.g., BEOL), the MTJ devices can also be placed at a higher metal layer to alleviate thermal budget considerations. This further allows transistors and interconnect layers below the memory arrays to be used for peripheral (e.g., control) circuits to boost memory density.

In contrast to STT-MRAM approaches that use a logic (e.g., FEOL) transistor for the selector transistor, one or more embodiments of the present disclosure provide for IGZO thin- film transistor (TFT) based STT-MRAM, where the MTJ of the STT-MRAM can be moved to a higher metal layer to minimize exposure to high temperature process steps and alleviate the thermal budget considerations of STT MTJ technology. Widening the thermal budget of MTJ is one of the key scaling challenges for STT-MRAM. Further, according to one or more embodiments of the present disclosure, by embedding the entire memory array in the interconnect, the transistor area below the memory array is freed for the peripheral circuits, which can significantly reduce memory circuit area and cost. In addition, in one or more embodiments of the present disclosure, with the MTJs embedded in the higher metal layers, both the source lines and the bitlines of the STT-MRAM can use the upper metal layers with lower resistance. This reduces parasitic resistance of the memory array and improves both write and read margins.

In short, by using a TFT (such as an IGZO TFT) as the selector transistor of the STT- MRAM memory cell, one or more embodiments of the present disclosure allow the entire memory cell and array to be embedded in the upper metal layers of the interconnect (BEOL). This allows higher memory density and better performance and scalability, and enables relaxed thermal budget requirement for MTJ technology. Put another way, by embedding the STT- MRAM memory array completely in the upper BEOL interconnect using TFTs, one or more embodiments of the present disclosure provide a feasible path to integrate STT-MRAM in an advanced technology node where the MTJ thermal budget requirement continues to be a significant challenge. With the TFT-based STT-MRAM, the memory array can be integrated in the higher metal layers where the design rules are relaxed and have less process change from generation to generation. This enables an easier path to integrate STT-MRAM to different process nodes.

Architecture and Methodology

FIG. 1 is a cross-sectional (Y-Z) view of an example STT-MRAM 100, according to an embodiment of the present disclosure. FIG. 1 illustrates the Y and Z dimensions (width and height, respectively), the X dimension (length) extending into and out of the Y-Z plane. The STT-MRAM 100 includes an FEOL 110 that includes most of the various logic layers, circuits, and devices to drive and control the integrated circuit (e.g., chip) being fabricated with the STT- MRAM 100. As illustrated in FIG. 1, the STT-MRAM 100 also includes a BEOL 120 including, in this case, eight metal interconnect layers (namely, metal-1 layer 125, metal-2 layer 130, metal- 3 layer 135, metal-4 layer 140, metal-5 layer 145, metal-6 layer 150, metal-7 layer 165, and metal-8 layer 170, including via portion 155 and interconnect portion 160 of the metal-7 layer 165) to interconnect the various inputs and outputs of the FEOL 110. Generally speaking, and specifically illustrated for the metal-7 layer 165, each of the metal- 1 layer 125 through the metal-8 layer 170 includes a via portion and an interconnect portion located above the via portion, the interconnect portion for transferring signals along metal lines extending in the X or Y directions, the via portion for transferring signals through metal vias extending in the Z direction (such as to the next lower metal layer underneath). Accordingly, vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures of the next lower metal layer. Further, each of the metal- 1 layer 125 through the metal-8 layer 170 includes a pattern of conductive metal, such as copper (Cu) or aluminum (Al) formed in a dielectric medium or inter-layer dielectric (ILD), such as by photolithography.

In addition, the STT-MRAM 100 is further divided into a memory array 190 (e.g., an

STT-MRAM memory array) built in the metal-4 layer 140 through the metal-8 layer 170. The memory array 190 includes the selector TFTs (in the metal-5 layer 145) and MTJs (in the metal - 7 via portion 155). The memory array 190 further includes the wordlines (e.g., row selectors, in the metal-4 layer 140), the source lines and short metal stubs (in the metal-5 layer 145), the landing pads (in the metal-6 layer 150), and the bitlines (e.g., column selectors, in conjunction with the source lines, in the metal-7 interconnect portion 160) making up the MRAM memory cells. In addition, the memory array 190 is driven by a memory array peripheral circuit 180 built in the FEOL and metal-1 layer 125 through metal-3 layer 135 to control (e.g., access, store, refresh) the memory array 190.

The short metal stubs and landing pads are metal extensions coupling the selector TFTs to the MTJs, the short metal stubs representing the extensions through the metal-5 layer 145 and the landing pads representing the extensions through the metal-6 layer 150. In other embodiments, there may be more (e.g., three) or fewer (e.g., one) such extensions depending on factors such as the amount of BEOL customization to fabricate the STT-MRAM 100 and the number of metal interconnect layers separating the selector TFTs from the MTJs. For ease of description throughout, it is assumed that the MTJs are fabricated in the metal-7 layer 165, the selector TFTs are fabricated in the metal-5 layer 145, and there are two metal extensions coupling the selector TFTs to the MTJs, namely the short metal stubs (in the metal-5 layer 145) and the landing pads (in the metal-6 layer 150). However, other embodiments are not so limited, as will be apparent in light of the present disclosure.

Compared to other MRAM designs that locate such a memory control circuit in the same layers as the memory array but in a different macro (or X-Y) area of the integrated circuit than the memory array (such as at a periphery of the memory array), the STT-MRAM 100 locates the memory array peripheral circuit 180 below the memory array 190 (e.g., in the same X-Y area), This saves valuable X-Y area in the finished integrated circuit (e.g., chip). In further detail, the STT-MRAM 100 embeds the selector TFTs in the metal-5 layer 145 (such as the via portion of the metal-5 layer 145). For example, the metal-4 layer 140 can contain the wordlines extending in the X direction to select a row of memory cells (bits) while the metal-7 layer 165 (and more particularly, the metal- 7 interconnect portion 160) can contain the bitlines extending in the Y direction and the metal-5 layer 145 can contain the source lines to sense each of the memory cells (bits) in the selected row (and to write memory data to any of the memory cells in the selected row). The selector TFTs can be fabricated in the metal-5 layer 145, above the wordlines (that serve as or connect to the gate electrodes or contacts) and below the bitlines and source lines (that serve as or connect to the source and drain electrodes or contacts). For example, the selector TFT can have the transistor gate below the thin film layer (that can be formed at the bottom of the metal-5 layer 145, such as in the via portion) and source and drain contacts above the thin film layer.

The STT-MRAM 100 of FIG. 1 is a one-TFT and one-MTJ STT-MRAM memory cell design. In one or more embodiments of the present disclosure, the STT-MRAM 100 uses, for example, an IGZO TFT as the selector transistor of the memory cell. The bottom-gate TFT is embedded in the metal-5 layer 145 (such as in the via portion of the metal-5 layer 145) of the BEOL 120. In addition, the source line and short metal stub are also in the metal-5 layer 145 (such as in the interconnect portion of the metal-5 layer 145) above the IGZO thin film and define the source and drain terminals of the selector TFT. The space between the source line and the short metal stub defines the channel length of the selector TFT. Each memory cell has a dedicated landing pad (for the MTJ) in the metal-6 layer 150. The MTJ is embedded in the metal-7 via portion 155. By moving the MTJ to higher metal layers such as the metal-7 layer 165, the MTJ experiences fewer high-temperature processing steps as compared to placing the MTJ in the lower metal layers such as with other STT-MRAM designs. The lower thermal budget helps improve the MTJ device performance and provides a feasible path to integrate STT-MRAM in scaled technology nodes.

A capping layer is formed above the top electrode of the MTJ in the metal-7 via portion 155. The dimension of the capping layer is bigger than the MTJ and it is used to land the vias from the metal-7 interconnect portion 160. The larger capping layer prevents or helps prevent damage to the MTJ caused by the via etch, and prevents or helps prevent shorting of the MTJ top and bottom electrodes by wrap-around of the via through over-etch of the via. The capping layer may be formed from metal or other conductive material, such as tantalum nitride (TaN), titanium nitride (TiN), and tantalum (Ta), to name a few.

The metal-4 layer 140 is used for the wordlines of the STT-MRAM 100. It contacts (for example, directly contacts) the metal gate of the selector TFT (such as in the via portion of the metal-5 layer 145) and provides a low-resistance path for the wordline signal. The metal-3 layer 135 and below (including the logic transistor area) is used for the memory array peripheral circuit 180 of the STT-MRAM 100. This provides substantial improvement of memory macro density (e.g., X-Y area) as compared to other STT-MRAM macro designs where the peripheral circuit is placed outside of the memory array (in a separate X-Y portion of the integrated circuit), instead of directly below the memory array 190 as with the STT-MRAM 100. Having the memory array peripheral circuit 180 directly below the memory array 190 reduces the distance between the memory cells and the peripheral circuit, which reduces or minimizes the impact of interconnect resistance on memory speed. This is important for scaling STT-MRAM technology to smaller dimensions as increasing interconnect resistance has become a significant challenge.

In further detail, the metal gate of the selector TFT in each memory cell is connected to a continuous metal-4 line below, such as a copper (Cu)-based metal line, which provides much lower resistance compared to gate lines formed in the lower (e.g., FEOL) portions of the integrated circuit. The continuous metal-4 line is used as the wordline of the memory array, and is covered by diffusion barriers or diffusion barrier layers including dielectric layers, such as silicon nitride (e.g., Si ₃ N ₄ ), silicon carbide (e.g., SiC), or the like, with vias filled with metal diffusion barrier films like tantalum nitride (TaN), tantalum (Ta), titanium zirconium nitride (e.g., Ti^r N, such as X = 0.53), titanium nitride (e.g., TiN), titanium tungsten (TiW), or the like. A metal gate layer covers the diffusion barrier film-filled vias, which electrically connect the copper (Cu) wordline to the metal gates of the selector TFTs, the diffusion barrier film preventing or helping to prevent the diffusion or migration of copper (Cu) from the wordline to the rest of the selector TFTs. An active thin film layer (e.g., indium gallium zinc oxide, or IGZO) and then source and drain contacts above the thin film layer use the metal-5 layer 145. The space between the source and drain contacts determines the gate length of the selector transistor.

The integrated circuit can be fabricated with common steps for each of the metal interconnect layers, such as using copper for the metal-4 layer 140. In one embodiment, the STT-MRAM uses a custom metal-5 layer, such as a different metal (e.g., titanium nitride (TiN)), in place of copper. Varying the material or fabrication steps for the metal-5 layer 145 can improve the short metal stub and source line performance (e.g., lower resistance, better integration with the selector TFT).

A landing pad in the metal-6 layer 150 extends the short metal stub to make electrical contact with the MTJ, which is embedded in the metal-7 via portion 155 on top of (e.g., directly contacting) the landing pad. A capping layer (also formed in the metal-7 via portion 155) covers and protects the MTJ while a bitline is formed in the metal-7 interconnect portion 160 and connected to the capping layer through a via in the metal-7 via portion 155.

The wordlines in the STT-MRAM 100 have a different orientation than the bitlines and the source lines. For example, the wordlines can extend in the X direction while the source lines and bitlines extend in the Y direction. Both the bitlines and the source lines use higher metal layers (e.g., metal-7 layer 165 and metal-5 layer 145, respectively), which usually have much lower resistivity than the lower metal layers.

FIGs. 2A-2B are cross-sectional (X-Z and Y-Z, respectively) views of an example STT- MRAM memory cell 250, according to an embodiment of the present disclosure. FIG. 3 is a cross-sectional (X-Z) view of an example STT MTJ 270, according to an embodiment of the present disclosure.

The selector TFT 210 in the memory cell 250 is coupled to or controlled by wordline 220 (which serves as the gate), source line 230, and short metal stub 240. The source line 230 and short metal stub 240 serve as the source and drain contacts of the selector TFT 210. In the example embodiment of FIGs. 2A-2B, the wordline 220 is formed in the metal-4 layer 140 (such as with the same process used to fabricate the metal-4 layer 140 for the rest of the integrated circuit), the selector TFT 210 is formed in the metal-5 layer 145 (for instance, in the via portion of the metal-5 layer 145), and the short metal stub 240 and source line 230 are formed in the metal-5 layer 145 (for instance, in the interconnect portion of the metal-5 layer 145). The metal-5 layer 145 fabrication (specifically, the via portion fabrication) is augmented for the STT-MRAM memory array to fabricate the selector TFTs 210.

In the example embodiment of FIGs. 2A-2B, the bottom gate selector TFT 210 may include thin-film layers such as one or more gate electrode layers (e.g., diffusion barrier 212 and metal gate 214) on top of the wordline 220 and covered by a gate dielectric layer (such as gate dielectric 216), and then a semiconductor (active) layer such as active layer 218 in contact with the source line 230 and the short metal stub 240. The active layer 218 has source and drain regions under the short metal stub 240 and source line 230, with a semi conductive channel region in between (as controlled by a gate signal supplied by the wordline 220).

The diffusion barrier 212 can be a metal- or copper-diffusion barrier (e.g., a conductive material to reduce or prevent the diffusion of metal or copper from wordline 220 into the metal gate 214 while still maintaining an electrical connection between the wordline 220 and the metal gate 214) on the wordline 220 such as tantalum nitride (TaN), tantalum (Ta), titanium zirconium nitride (e.g., Ti Zr N, such as X = 0.53), titanium nitride (e.g., TiN), titanium tungsten (TiW), combination (such as a stack structure of TaN on Ta), or the like. For instance, the diffusion barrier 212 can include a single- or multi -layer structure including a compound of tantalum(Ta) and nitrogen(n), such as TaN or a layer of TaN on a layer of Ta. In some embodiments, a layer of etch resistant material (e.g., etch stop 211) such as silicon nitride (e.g., Si ₃ N ₄ ) or silicon carbide

(e.g., SiC) is formed over the wordline 220 with vias for a metal (or copper) diffusion barrier film 212 such as TaN or a TaN/Ta stack. The metal gate 214 can be a conductive material on the diffusion barrier 212, such as metal, conductive metal oxide or nitride, or the like. For example, in one embodiment, the metal gate 214 is titanium nitride (TiN). In another embodiment, the metal gate 214 is tungsten (W).

The gate dielectric 216 can be silicon dioxide (Si0 ₂ ), silicon nitride (e.g., Si ₃ N ₄ ), hafnium dioxide (Hf0 ₂ ) or other high-κ material, or a multi-layer stack including a first layer of Si0 ₂ and a second layer of a high-κ dielectric such as Hf0 ₂ on the Si0 ₂ . Any number of gate dielectrics can be used, as will be appreciated in light of the present disclosure. For example, in one embodiment, the gate dielectric 216 is a layer of Si0 ₂ . In another embodiment, the gate dielectric 216 is a stack (e.g., two or more layers) of Hf0 ₂ on Si0 ₂ .

The active layer 218 can be IGZO or the like in contact with the source line 230 (e.g., at a first region of the active layer 218, such as a drain region) and the short metal stub 240 (e.g., at a second region of the active layer 218, such as a source region, with a semi -conductive channel region between the first region and the second region). Such an active layer 218 channel may include only majority carriers in the thin film. Accordingly, the active layer 218 channel may require high bias (as supplied by the wordline 220, diffusion barrier film 212, and metal gate 214) to activate. In addition to IGZO, in some embodiments, the active layer is one of a variety of polycrystalline semiconductors, including, for example, zinc oxynitride (ZnON, such as a composite of zinc oxide (ZnO) and zinc nitride (Zn ₃ N ₂ ), or of ZnO, ZnO _x Z _y , and Zn ₃ N ₂ ), indium tin oxide (ITO), tin oxide (e.g., SnO), copper oxide (e.g., Cu ₂ 0), polycrystalline germanium (poly-Ge) silicon-germanium (e.g., SiGe, such as Sii- _x Ge _x ) structures (such as a stack of poly-Ge over SiGe), and the like.

The short metal stubs 240 of the selector TFTs 210 in the memory cells 250 are separated between cells 250. Each short metal stub 240 is connected to an MTJ 270 (e.g., an STT MTJ) above through the landing pad 260. For example, the landing pad 260 may be copper and fabricated in the metal-6 layer 150 while the MTJ 270 may be fabricated in the via portion 155 of the metal- 7 layer 165. For example, the metal-6 layer 150 may be fabricated in common across the whole integrated circuit, while the via portion 155 of the metal-7 layer is augmented for the STT-MRAM to fabricate the MTJs 270.

The MTJ 270 may be fabricated in a series of layers, such as thin-film layers including a conductive diffusion barrier film 271 (e.g., similar to the diffusion barrier 212 layer), a bottom electrode 272 on the conductive diffusion barrier film 271, a bottom magnet 274 (e.g., a fixed polarity or fixed-spin or fixed spin orientation magnet of ferromagnetic material, having a majority of electrons or other charge carriers of the same spin), a thin insulator 276 (e.g., a tunnel barrier, at most a few nanometers thick, to allow tunneling by electrons), a top magnet 278 (e.g., a varying polarity or free-spin or varying spin orientation magnet of ferromagnetic material), and a capping layer 280 (e.g., conductive metal). The bottom magnet 274 has electrons of one spin (fixed) while the top magnet 278 can switch between electrons having the same spin as the bottom magnet 274 and electrons having the opposite spin (e.g., through a dynamic write process, such as driving current upward through the MTJ 270 to convert the top magnet 278 to the opposite spin, and driving current downward through the MTJ 270 to convert the top magnet 278 to the same spin as the bottom magnet 274).

In one embodiment, the conductive diffusion barrier film 271 is tantalum nitride (TaN). In another embodiment, the conductive diffusion barrier film 271 is tantalum (Ta). In one embodiment, the bottom electrode 272 is ruthenium (Ru). In another embodiment, the bottom electrode 272 is tantalum (Ta). In another embodiment, the bottom electrode is titanium nitride (TiN). In some embodiments, the bottom magnet 274 is one or more layers of cobalt (Co), cobalt-platinum (Pt) alloys, ruthenium (Ru), cobalt-iron (CoFe) alloys, cobalt-iron-boron (CoFeB) alloys, and tungsten (W). In one or more embodiments, the thin insulator 276 is magnesium oxide (MgO). In some embodiments, the top magnet 278 is CoFeB alloys. In another embodiment, the top magnet 278 is tungsten. In another embodiment, the top magnet 278 is tantalum.

The capping layer 280 serves as both a top electrode on the MTJ 270 as well as a protective surface for receiving metal-7 via metal (e.g., during a remainder of the metal-7 via portion 155 fabrication). The capping layer 280 can be a thin layer of metal (e.g., TaN, TiN, Ta) having slightly larger X and Y dimensions than the MTJ 270 (to protect the MTJ 270 during via formation in the metal-7 layer to connect the MTJ 270 to a bitline).

Each bottom electrode 272 of an MTJ 270 connects to a corresponding landing pad 260 through a buffer layer or conductive diffusion barrier layer 271. The buffer layer may be fabricated in openings of the etch stop layer marking the bottom of the metal-7 layer 165 (that is also the bottom of the via portion 155 of the metal-7 layer 165) to connect the landing pad 260 (e.g., part of the metal-6 layer) to the bottom electrode 272 of the MTJ 270. The bottom electrodes 272 of the MTJs 270 are electrically insulated from each other while the capping layers 280 of the MTJs 270 of the same bitline 290 are electrically connected to each other, such as through vias (e.g., in the via portion 155 of the metal-7 layer 165) connecting the capping layers 280 to the bitline 290 (in the interconnect portion 160 of the metal-7 layer 165). The source line 230 of the selector TFT 210 is continuous (e.g., parallel to the corresponding bitline 290).

FIG. 4 illustrates an example method 400 of fabricating an STT-MRAM memory cell, according to an embodiment of the present disclosure. FIG. 5 illustrates an example method 500 of fabricating an STT-MRAM including memory cells at crossing regions of wordlines and bitlines, according to an embodiment of the present disclosure. These and other methods disclosed herein may be carried out using integrated circuit fabrication techniques such as photolithography as would be apparent in light of the present disclosure. The corresponding STT-MRAM memory cell and STT-MRAM including the memory cells may be part of other (logic) devices on the same substrate, such as application specific integrated circuits (ASICs), microprocessors, central processing units, processing cores, and the like. Unless otherwise described herein, verbs such as "coupled" or "couple" refer to an electrical coupling (such as capable of transmitting an electrical signal), either directly or indirectly (such as through one or more conductive layers in between).

Referring to FIGs. 4-5 (with specific example references to the structures of FIGs. 1-3) method 400 includes forming 410 logic devices (e.g., transistors, capacitors, resistors, and the like, such as FEOL 110) in a front end of line (FEOL) process on a substrate, and interconnecting 420 the logic devices in a back end of line (BEOL) process, such as BEOL 120. The BEOL process includes forming 430 a wordline (such as wordline 220) in a first metal layer (such as metal -4 layer 140) to supply a gate signal, and forming 440 a selector thin-film transistor (TFT, such as selector TFT 210) in a second metal layer (such as metal-5 layer 145) above the first metal layer using a thin film process. The selector TFT has an active layer (such as active layer 218) and is configured to electrically connect (such as through a channel region) a first region (such as a source or drain region coupled to source line 230) and a second region (such as a drain or source region coupled to short metal stub 240) of the active layer in response to the gate signal (such as the gate signal being delivered to metal gate 214). The BEOL process further includes forming 450 a source line (such as source line 230) in the second metal layer. The source line is coupled to and above the first region of the active layer. The BEOL process further includes forming 460 a short metal stub (such as short metal stub 240) in the second metal layer coupled to and above the second region of the active layer, and forming 470 an STT MTJ (such as MTJ 270) coupled to and above the storage node and configured to store the memory state. The BEOL process further includes forming 480 a bitline (such as bitline 290) coupled to and above the MTJ to transfer the memory state in conjunction with the source line (e.g., as current on a path between the bitline and the source line). Method 500 includes forming 510 logic devices in an FEOL process on a substrate, and interconnecting 520 the logic devices in a BEOL process. The BEOL process includes a first part (such as metal- 1 layer 125 through metal-3 layer 135) and a second part (such as metal-4 layer 140 through metal-8 layer 170) following the first part. The FEOL process and the first part of the BEOL process include forming 530 a control circuit (such as memory array peripheral circuit 180) to drive the wordlines (such as wordlines 220), the source lines (such as source lines 230), and the bitlines (such as bitlines 290). The second part of the BEOL process includes forming 540 the wordlines in a first metal layer (such as metal-4 layer 140) and extending in a first direction (such as the X direction) to supply a gate signal and, for each memory cell (such as memory cell 250), forming 550 a selector TFT (such as selector TFT 210) in a second metal layer (such as metal-5 layer 145) above the first metal layer using a thin film process. Each selector TFT has an active layer (such as active layer 218) and is configured to electrically connect a first region and a second region of the active layer in response to the gate signal being supplied by a corresponding one of the wordlines.

The second part of the BEOL process further includes forming 560 the source lines in the second metal layer and extending in a second direction (such as the Y direction) crossing the first direction. The first region of the active layer of the selector TFT of each memory cell is coupled to and below a corresponding one of the source lines. The second part of the BEOL process further includes, for each memory cell, forming 570 a short metal stub (such as short metal stub 240) in the second metal layer coupled to and above the second region of the active layer of the selector TFT, and forming 580 an STT MTJ (such as MTJ 270) coupled to and above the short metal stub and configured to store a corresponding one of the memory states. The second part of the BEOL process further includes forming 590 the bitlines (such as bitlines 290) extending in the second direction to transfer the memory states in conjunction with the source lines. The MTJ of each memory cell is coupled to and below a corresponding one of the bitlines.

While the above example methods appear as a series of operations or stages, it is to be understood that there is no required order to the operations or stages unless specifically indicated. For example, in one embodiment of the method 500, the forming 530 of the control circuit can take place as part of or concurrently with the forming 510 of the logic devices in the FEOL process and the first part of the interconnecting 520 of the logic devices in the BEOL process. Example System

FIG. 6 illustrates a computing system 1000 implemented with the integrated circuit structures or techniques disclosed herein, according to an embodiment of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 (including STT-MRAM) and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, to name a few examples.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM), resistive random-access memory (RRAM), and the like), a graphics processor, a digital signal processor, a crypto (or cryptographic) processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices (e.g., one or more STT-MRAM memory cells) formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, and the like., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE

802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-

DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices (e.g., one or more STT-MRAM memory cells) formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices (e.g., one or more STT-MRAM memory cells) formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi- standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices (e.g., one or more STT-MRAM memory cells) formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent. Example 1 is an embedded spin-transfer torque magnetic random-access memory (STT- MRAM) memory cell. The memory cell includes: a wordline to supply a gate signal; a selector thin-film transistor (TFT) above the wordline and including an active layer; a source line coupled to and above a first region of the active layer; a metal stub coupled to and above a second region of the active layer; an STT magnetic tunnel junction (MTJ) coupled to and above the metal stub and configured to store a memory state; and a bitline coupled to and above the MTJ.

Example 2 includes the subject matter of Example 1, where the active layer includes indium gallium zinc oxide (IGZO).

Example 3 includes the subject matter of any of Examples 1-2, where the selector TFT further includes a gate layer coupled to the wordline and below the active layer, and a gate dielectric layer between the gate layer and the active layer.

Example 4 includes the subject matter of Example 3, where the selector TFT further includes a first diffusion barrier layer coupled to and between the wordline and the gate layer.

Example 5 includes the subject matter of Example 4, where the first diffusion barrier layer includes tantalum (Ta) and nitrogen (N). For example, in one embodiment, the first diffusion barrier layer is tantalum nitride (TaN). In another embodiment, the first diffusion barrier layer is a stack of TaN on Ta.

Example 6 includes the subject matter of any of Examples 1-5, where the MTJ includes a bottom electrode coupled to the metal stub, a bottom magnet coupled to and above the bottom electrode and having a fixed spin orientation, a top magnet coupled to the bitline and having a varying spin orientation, and a thin insulator to act as a tunnel barrier between the bottom magnet and the top magnet.

Example 7 includes the subject matter of Example 6, where the MTJ further includes a second diffusion barrier layer coupled to and between the metal stub and the bottom electrode.

Example 8 includes the subject matter of Example 7, where the second diffusion barrier layer includes tantalum (Ta) and nitrogen (N). For example, in one embodiment, the second diffusion barrier layer is tantalum nitride (TaN). In another embodiment, the second diffusion barrier layer is a stack of TaN on Ta.

Example 9 includes the subject matter of any of Examples 1-8, further including a capping layer coupled to and between the MTJ and the bitline.

Example 10 includes the subject matter of any of Examples 1-9, further including a landing pad coupled to and between the metal stub and the MTJ.

Example 11 includes the subject matter of Example 10, where the source line and the metal stub are in a first metal layer, the landing pad is in a second metal layer above the first metal layer, the bitline is in an interconnect portion of a third metal layer above the second metal layer, and the MTJ is in a via portion of the third metal layer below the interconnect portion, the via portion coupling a metal structure of the interconnect portion to a metal structure of the second metal layer.

Example 12 includes the subject matter of any of Examples 1-10, where the wordline is in a first metal layer, the source line and the metal stub are in an interconnect portion of a second metal layer above the first metal layer, and the selector TFT is in a via portion of the second metal layer below the interconnect portion, the via portion coupling a metal structure of the interconnect portion to a metal structure of the first metal layer.

Example 13 includes the subject matter of any of Examples 1-9, where the source line and the metal stub are in a first metal layer, the bitline is in an interconnect portion of a second metal layer above the first metal layer, and the MTJ is in a via portion of the second metal layer below the interconnect portion, the via portion coupling a metal structure of the interconnect portion to a metal structure of the first metal layer.

Example 14 is an embedded spin-transfer torque magnetic random-access memory (STT- MRAM). The STT-MRAM includes: wordlines extending in a first direction to supply a gate signal; source lines and bitlines extending in a second direction crossing the first direction; and memory cells at regions where the wordlines cross the source lines and the bitlines. Each memory cell includes a selector thin-film transistor (TFT) above a corresponding one of the wordlines and having an active layer, a first region of the active layer being coupled to and below a corresponding one of the source lines, a metal stub coupled to and above a second region of the active layer, and an STT magnetic tunnel junction (MTJ) coupled to and above the metal stub and configured to store a memory state, the MTJ being coupled to and below a corresponding one of the bitlines.

Example 15 includes the subject matter of Example 14, further including a control circuit below the wordlines to drive the wordlines, the source lines, and the bitlines.

Example 16 includes the subject matter of any of Examples 14-15, where the active layer includes indium gallium zinc oxide (IGZO).

Example 17 includes the subject matter of Examples 14-16, where the selector TFT further has a gate layer coupled to the corresponding one of the wordlines and below the active layer, and a gate dielectric layer to insulate the gate layer from the active layer.

Example 18 includes the subject matter of Example 17, where the selector TFT further has a first diffusion barrier layer coupled to and between the corresponding one of the wordlines and the gate layer. For example, in one embodiment, the first diffusion barrier layer has high conductivity. In addition, in some embodiments, the wordline includes copper (Cu) and the first diffusion barrier layer is a copper-diffusion barrier layer. Example 19 includes the subject matter of Example 18, where the first diffusion barrier layer includes tantalum (Ta) and nitrogen (N).

Example 20 includes the subject matter of any of Examples 14-19, where the MTJ includes a bottom electrode coupled to the metal stub, a bottom magnet coupled to and above the bottom electrode and having a fixed spin orientation, a top magnet coupled to the corresponding one of the bitlines and having a varying spin orientation for storing the memory state, and a thin insulator to act as a tunnel barrier between the bottom magnet and the top magnet.

Example 21 includes the subject matter of Example 20, where the MTJ further includes a second diffusion barrier layer coupled to and between the metal stub and the bottom electrode.

Example 22 includes the subject matter of Example 21, where the second diffusion barrier layer includes tantalum (Ta) and nitrogen (N).

Example 23 includes the subject matter of any of Examples 14-22, each memory cell further including a capping layer coupled to and between the MTJ and the corresponding one of the bitlines.

Example 24 includes the subject matter of any of Examples 14-23, each memory cell further including a landing pad coupled to and between the metal stub and the MTJ.

Example 25 includes the subject matter of the source lines and the metal stub are in a first metal layer, the landing pad is in a second metal layer above the first metal layer, the bitlines are in an interconnect portion of a third metal layer above the second metal layer, and the MTJ is in a via portion of the third metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the second metal layer.

Example 26 includes the subject matter of any of Examples 14-24, where the wordlines are in a first metal layer, the source lines and the metal stub is in an interconnect portion of a second metal layer above the first metal layer, and the selector TFT is in a via portion of the second metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the first metal layer.

Example 27 includes the subject matter of any of Examples 14-23, where the source lines and the metal stub are in a first metal layer, the bitlines are in an interconnect portion of a second metal layer above the first metal layer, and the MTJ is in a via portion of the second metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the first metal layer.

Example 28 is a method of fabricating an embedded spin-transfer torque magnetic random- access memory (STT-MRAM) memory cell. The method includes: forming logic devices in a front end of line (FEOL) process on a substrate; and interconnecting the logic devices in a back end of line (BEOL) process. The BEOL process includes forming a wordline in a first metal layer to supply a gate signal, forming a selector thin-film transistor (TFT) in a second metal layer above the first metal layer using a thin film process, the selector TFT having an active layer and configured to electrically connect a first region of the active layer to a second region of the active layer in response to the gate signal, forming a source line in the second metal layer coupled to and above the first region of the active layer, forming a metal stub in the second metal layer coupled to and above the second region of the active layer, forming an STT magnetic tunnel junction (MTJ) coupled to and above the metal stub and configured to store a memory state, and forming a bitline coupled to and above the MTJ to transfer the memory state in conjunction with the source line.

Example 29 includes the subject matter of Example 28, where the forming of the selector TFT includes forming the active layer using indium gallium zinc oxide (IGZO).

Example 30 includes the subject matter of any of Examples 28-29, where the forming of the selector TFT includes forming a gate layer coupled to the wordline and below the active layer, and forming a gate dielectric layer to insulate the gate layer from the active layer.

Example 31 includes the subject matter of Example 30, where the forming of the selector TFT further includes forming a first diffusion barrier layer coupled to and between the wordline and the gate layer.

Example 32 includes the subject matter of Example 31, where the forming of the first diffusion barrier layer includes forming the first diffusion barrier layer using tantalum (Ta) and nitrogen (N).

Example 33 includes the subject matter of any of Examples 28-32, where the forming of the MTJ includes forming a bottom electrode coupled to the metal stub, forming a bottom magnet coupled to and above the bottom electrode and having a fixed spin orientation, forming a thin insulator on the bottom magnet, and forming a top magnet on the thin insulator, the top magnet being coupled to the bitline and having a varying spin orientation for storing the memory state, the thin insulator acting as a tunnel barrier between the bottom magnet and the top magnet.

Example 34 includes the subject matter of Example 33, where the forming of the MTJ further includes forming a second diffusion barrier layer coupled to and between the metal stub and the bottom electrode.

Example 35 includes the subject matter of Example 34, where the forming of the second diffusion barrier layer includes forming the second diffusion barrier layer using tantalum (Ta) and nitrogen (N).

Example 36 includes the subject matter of any of Examples 28-35, where the BEOL process further includes forming a capping layer coupled to and between the MTJ and the bitline. Example 37 includes the subject matter of any of Examples 28-36, where the BEOL process further includes forming a landing pad coupled to and between the metal stub and the MTJ.

Example 38 includes the subject matter of Example 37, where the forming of the landing pad includes forming the landing pad in a third metal layer above the second metal layer, the forming of the bitline includes forming the bitline in an interconnect portion of a fourth metal layer above the third metal layer, and the forming of the MTJ includes forming the MTJ in a via portion of the fourth metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the third metal layer.

Example 39 includes the subject matter of Examples 28-38, where the forming of the source line and the forming of the metal stub include forming the source line and the metal stub in an interconnect portion of the second metal layer, and the forming of the selector TFT includes forming the selector TFT in a via portion of the second metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the first metal layer.

Example 40 includes the subject matter of any of Examples 28-36, where the forming of the bitline includes forming the bitline in an interconnect portion of a third metal layer above the second metal layer, and the forming of the MTJ includes forming the MTJ in a via portion of the third metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the second metal layer.

Example 41 is a method of fabricating an embedded spin-transfer torque magnetic random- access memory (STT-MRAM) including memory cells for storing memory states at regions where wordlines cross source lines and bitlines. The method includes: forming logic devices in a front end of line (FEOL) process on a substrate; and interconnecting the logic devices in a back end of line (BEOL) process, the BEOL process including a first part and a second part following the first part. The FEOL process and the first part of the BEOL process include forming a control circuit to drive the wordlines, the source lines, and the bitlines. The second part of the BEOL process includes forming the wordlines in a first metal layer and extending in a first direction to supply a gate signal, for each memory cell, forming a selector thin-film transistor (TFT) in a second metal layer above the first metal layer using a thin film process, the selector TFT having an active layer and configured to electrically connect a first region of the active layer to a second region of the active layer in response to the gate signal being supplied by a corresponding one of the wordlines, forming the source lines in the second metal layer and extending in a second direction crossing the first direction, the first region of the active layer of the selector TFT of each memory cell being coupled to and below a corresponding one of the source lines, for each memory cell, forming a metal stub in the second metal layer coupled to and above the second region of the active layer of the selector TFT, for each memory cell, forming an STT magnetic tunnel junction (MTJ) coupled to and above the metal stub and configured to store a corresponding one of the memory states, and forming the bitlines extending in the second direction to transfer the memory states in conjunction with the source lines, the MTJ of each memory cell being coupled to and below a corresponding one of the bitlines.

Example 42 includes the subject matter of Example 41, where the forming of the selector TFT includes forming the active layer using indium gallium zinc oxide (IGZO).

Example 43 includes the subject matter of any of Examples 41-42, where the forming of the selector TFT includes forming a gate layer coupled to the corresponding one of the wordlines and below the active layer, and forming a gate dielectric layer to insulate the gate layer from the active layer.

Example 44 includes the subject matter of Example 43, where the forming of the selector TFT further includes forming a first diffusion barrier layer coupled to and between the corresponding one of the wordlines and the gate layer.

Example 45 includes the subject matter of Example 44, where the forming of the first diffusion barrier layer includes forming the first diffusion barrier layer using tantalum (Ta) and nitrogen (N).

Example 46 includes the subject matter of any of Examples 41-45, where the forming of the MTJ includes forming a bottom electrode coupled to the metal stub, forming a bottom magnet coupled to and above the bottom electrode and having a fixed spin orientation, forming a thin insulator on the bottom magnet, and forming a top magnet on the thin insulator, the top magnet being coupled to the corresponding one of the bitlines and having a varying spin orientation for storing the corresponding one of the memory states, the thin insulator acting as a tunnel barrier between the bottom magnet and the top magnet.

Example 47 includes the subject matter of Example 46, where the forming of the MTJ further includes forming a second diffusion barrier layer coupled to and between the metal stub and the bottom electrode.

Example 48 includes the subject matter of Example 47, where the forming of the second diffusion barrier layer includes forming the second diffusion barrier layer using tantalum (Ta) and nitrogen (N).

Example 49 includes the subject matter of any of Examples 41-48, where the second part of the BEOL process further includes, for each memory cell, forming a capping layer coupled to and between the MTJ and the corresponding one of the bitlines. Example 50 includes the subject matter of any of Examples 41-49, where the second part of the BEOL process further includes, for each memory cell, forming a landing pad coupled to and between the metal stub and the MTJ.

Example 51 includes the subject matter of Example 50, where the forming of the landing pad further includes forming the landing pad in a third metal layer above the second metal layer, the forming of the bitlines includes forming the bitlines in an interconnect portion of a fourth metal layer above the third metal layer, and the forming of the MTJ includes forming the MTJ in a via portion of the fourth metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the third metal layer.

Example 52 includes the subject matter of any of Examples 41-51, where the forming of the source lines and the forming of the metal stub include forming the source lines and the metal stub in an interconnect portion of the second metal layer, and the forming of the selector TFT includes forming the selector TFT in a via portion of the second metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the first metal layer.

Example 53 includes the subject matter of any of Examples 41-49, where the forming of the bitlines includes forming the bitlines in an interconnect portion of a third metal layer above the second metal layer, and the forming of the MTJ includes forming the MTJ in a via portion of the third metal layer below the interconnect portion, the via portion coupling one or more metal structures of the interconnect portion to one or more metal structures of the first metal layer.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.