Title:
THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2015/045213
Kind Code:
A1
Abstract:
A thin film transistor substrate (100) is provided with: a gate electrode (120), and a first electrode (121) of a capacitor (102), which are formed above a substrate (110) such that the gate electrode and the first electrode are disposed by being aligned with each other in the planar direction of the substrate (110); a gate insulating film (130) that is formed on the gate electrode (120); a semiconductor layer (140) that is formed on the gate insulating film (130); an insulating layer (150) that is formed on the semiconductor layer (140) and above the first electrode (121) such that a part of the semiconductor layer (140) is exposed; a source electrode (160s) and a drain electrode (160d), which are formed above the insulating layer (150) such that the source electrode and the drain electrode are connected to the semiconductor layer (140) at an exposed semiconductor layer (140) portion; and a second electrode (161) of the capacitor (102), said second electrode facing the first electrode (121), and being formed above the insulating layer (150). The film thickness of the insulating layer (150) above the gate electrode (120) is more than that of the insulating layer (150) above the first electrode (121).
Inventors:
KISHIDA YUJI
KAWASHIMA TAKAHIRO
NAKAZAKI YOSHIAKI
KAWASHIMA TAKAHIRO
NAKAZAKI YOSHIAKI
Application Number:
PCT/JP2014/002789
Publication Date:
April 02, 2015
Filing Date:
May 27, 2014
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
H01L21/336; G09F9/30; H01L29/786; H01L51/50; H05B33/02
Foreign References:
| JP2011049539A | 2011-03-10 | |||
| JP2013232548A | 2013-11-14 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
New house Extensive 守 (JP)
New house Extensive 守 (JP)
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