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Title:
THIN-FILM TRANSISTOR WITH SOURCE/DRAIN STRUCTURE TO REDUCE PARASITIC CAPACITANCE
Document Type and Number:
WIPO Patent Application WO/2019/135731
Kind Code:
A1
Abstract:
A thin-film transistor includes a gate electrode, a gate dielectric directly on the gate electrode, and a first semiconductor layer of a first material in contact with the gate dielectric. The first semiconductor layer has a body portion with a first body end, a second body end opposite the first body end, and a top surface spaced from the gate dielectric. A second semiconductor layer includes a first portion adjacent to and in direct contact with the first body end and a second portion adjacent to and in direct contact with the second body end. The first portion and the second portion are spaced apart by and directly connected to the body portion. The top surface of the first portion and of the second portion are spaced from the gate dielectric by an amount equal to or greater than for the top surface of the body portion.

Inventors:
MA, Sean T. (3306 SW Scholls Ferry Road, Portland, Oregon, 97221, US)
SHARMA, Abhishek A. (1091 NE Orenco Station Pkwy, E317Hillsboro, Oregon, 97124, US)
DEWEY, Gilbert (15530 NW Norwich St, Beaverton, Oregon, 97006, US)
LE, Van H. (5625 NW Peregrine Place, Portland, Oregon, 97229, US)
KAVALIEROS, Jack T. (3734 NW Bronson Crest Loop, Portland, Oregon, 97229, US)
Application Number:
US2018/012050
Publication Date:
July 11, 2019
Filing Date:
January 02, 2018
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
INTEL CORPORATION (2200 Mission College Boulevard, Santa Clara, California, 95054, US)
International Classes:
H01L29/786; H01L27/108
Foreign References:
US20150008428A12015-01-08
US20090325350A12009-12-31
US5414283A1995-05-09
US20060110869A12006-05-25
US20150311256A12015-10-29
Attorney, Agent or Firm:
KRUTSINGER, Ross K. (Finch & Maloney PLLC, Gateway One50 Commercial Street - Suite 30, Manchester New Hampshire, 03101, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. A thin-film transistor comprising:

a gate electrode;

a dielectric material directly on the gate electrode;

a first layer of a first semiconductor material on the dielectric material, the first layer including a source region, a drain region, and a body region between and physically connecting the source region and drain region, the body region having a top surface spaced from an underlying portion of the dielectric material by a vertical distance Dl;

a second layer of a second semiconductor material, the second layer including a first portion on the source region and a second portion on the drain region;

a first contact structure on the second layer over the source region, the first contact structure having a bottom surface spaced from an underlying portion of the dielectric material by a vertical distance D2, wherein D2 is equal to or greater than Dl; and

a second contact structure on the second layer over the drain region, the second contact structure having a bottom surface spaced from an underlying portion of the dielectric material by a vertical distance D3, wherein D3 is equal to or greater than Dl.

2. The thin-film transistor of claim 1, wherein the second semiconductor material is compositionally different from the first semiconductor material.

3. The thin-film transistor of claim 1, wherein the body region has a vertical thickness less than a vertical thickness of at least one of the source region or the drain region.

4. The thin-film transistor of any of claims 1-3, wherein the second layer over at least one of the source region or the drain region has a vertical thickness from 5 to 20 nm.

5. The thin-film transistor of claim 4, wherein a conduction band minimum of the second semiconductor material is from zero to 0.5 eV greater than a conduction band minimum of the first semiconductor material.

6. The thin-film transistor of claim 5, wherein the conduction band minimum of the second semiconductor material is from zero to 0.2 eV greater than the conduction band minimum of the first semiconductor material.

7. The thin-film transistor of any of claims 1-3, wherein the first semiconductor material comprises one or more of (i) indium, gallium, zinc, and oxygen, (ii) indium, zinc, and oxygen, (iii) indium, tin, and oxygen, (iv) amorphous silicon (a-Si), (v) zinc and oxygen, (vi) polysilicon, (vii) poly germanium, (viii) low-temperature polycrystalline silicon (LTPS), (ix) amorphous germanium (a-Ge), (x) indium and arsenic, (xi) copper and oxygen, and (xii) tin and oxygen.

8. The thin-film transistor of any of claims 1-3, wherein the second semiconductor material comprises (i) germanium, (ii) silicon, (iii) indium and arsenic, (iv) gallium and arsenic, (v) indium and antimony, or (vi) gallium and antimony.

9. The thin-film transistor of any of claims 1-3, wherein the body region has a vertical thickness from 4 nm to 20 nm as measured perpendicularly to the dielectric material.

10. The thin-film transistor of claim 9, wherein the body region has a vertical thickness from 4 nm to 10 nm

11. The thin-film transistor of any of claims 1 -3, wherein the dielectric material comprises a high- K dielectric.

12. The thin-film transistor of claim 11, wherein the dielectric material has a vertical thickness from 2 to 10 nm.

13. The thin-film transistor of any of claims 1-3, wherein the dielectric material comprises hafnium and oxygen.

14. The thin-film transistor of claim 13, wherein the dielectric material has a vertical thickness from 2 to 10 nm.

15. The thin-film transistor of any of claims 1-3, wherein a vertical thickness of the source region or the drain region is from 2 to 20 nm.

16. The thin-film transistor of any of claims 1-3 further comprising an insulating substrate, wherein the gate electrode is directly on the insulating substrate.

17. A memory array comprising:

a plurality of wordlines extending in a first direction;

a plurality of bitlines extending in a second direction crossing the first direction; and a plurality of memory cells at crossing regions of the wordlines and the bitlines, wherein one or more of the plurality of memory cells includes

a gate electrode,

a dielectric material directly on the gate electrode,

a first layer of a first semiconductor material on the dielectric material, the first layer including a source region, a drain region, and a body region positioned between and physically connecting the source region and drain region, a second layer of a second semiconductor material different from the first semiconductor material, the second layer including a first portion on the source region and a second portion on the drain region; and

a capacitor including a first terminal, a second terminal, and a dielectric medium electrically separating the first and second terminals, and one of the first and second terminals is electrically connected to the drain region;

wherein one of the plurality of wordlines is electrically connected to the gate electrode and one of the plurality of bitlines is electrically connected to the source region.

18. The memory cell of claim 17, wherein the second layer has a vertical thickness from 5 to 20 nm.

19. The memory cell of claim 17 or 18, wherein the body region has a vertical thickness from 4 to 20 nm.

20. The memory cell of claim 17 or 18, wherein the source region and the drain region have a vertical thickness from 2 to 20 nm.

21. A method of fabricating a thin-film transistor, the method comprising: forming a gate electrode;

forming a dielectric material on the gate electrode;

forming a first layer of a first semiconductor material, the first layer including a source region, a drain region, and a body region, at least the body region being on the dielectric material, and the body region physically connecting the source and drain regions;

forming an insulating layer on first layer;

defining openings in the insulating layer to expose the source region and the drain region; forming a second layer of semiconductor material in the openings and on the source region and the drain region, wherein a top surface of the second layer in the openings is coplanar with or vertically above a top surface of the body region; and

forming metal contact structures on the second layer in the openings.

22. The method of claim 21 further comprising:

removing the insulator material; and

removing a portion of the first layer between the source region and the drain region, thereby reducing a vertical thickness of the body region.

23. The method of claim 22, wherein removing the portion of the first layer comprises reducing a vertical thickness of the body region by at least 25% between the source region and the drain region.

24. The method of claim 22, wherein removing the portion of the first layer comprises reducing a vertical thickness of the body region by at least 50% between the source region and the drain region.

25. The method of any of claims 21-24:

wherein the first semiconductor material comprises one or more of (i) indium, gallium, zinc, and oxygen, (ii) indium, zinc, and oxygen, (iii) indium, tin, and oxygen, (iv) amorphous silicon (a-Si), (v) zinc and oxygen, (vi) polysilicon, (vii) poly germanium, (viii) low- temperature polycrystalline silicon (LTPS), (ix) amorphous germanium (a-Ge), (x) indium and arsenic, (xi) copper and oxygen, and (xii) tin and oxygen; and

wherein the second semiconductor material comprises (i) germanium, (ii) silicon, (iii) indium and arsenic, (iv) gallium and arsenic, (v) indium and antimony, or (vi) gallium and antimony.

Description:
THIN-FILM TRANSISTOR WITH SOURCE/DRAIN STRUCTURE TO REDUCE PARASITIC

CAPACITANCE

BACKGROUND

A thin-film transistor (TFT) is generally fabricated by depositing thin films of an active semiconductor layer as well as a dielectric layer and metallic contacts over a substrate. There are a number of non-trivial performance issues associated with TFTs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an example thin-film transistor (TFT) with openings defined in an insulating layer and positioned over source and drain regions of the active layer, in accordance with an embodiment of the present disclosure.

FIG. 2 is a cross-sectional view of an example TFT with a second semiconductor material on the source and drain regions of the active layer of semiconductor material, in accordance with an embodiment of the present disclosure.

FIG. 3 is a cross-sectional view of an example TFT with a second semiconductor material replacing the source and drain regions of the active layer of semiconductor material, in accordance with an embodiment of the present disclosure.

FIG. 4 is a cross-sectional view of an example TFT with a second semiconductor material on the source and drain regions of the active layer of semiconductor material and extending above the top surface of the channel region, in accordance with an embodiment of the present disclosure.

FIG. 5 is a cross-sectional view of an example TFT with a second semiconductor material on the source and drain regions of the active layer of semiconductor material and having a recessed channel region, in accordance with an embodiment of the present disclosure.

FIG. 6 is a cross-sectional view of an example TFT with a second semiconductor material replacing the source and drain regions of the semiconductor material of the active layer and having a recessed channel region, in accordance with an embodiment of the present disclosure.

FIG. 7 is a cross-sectional view of an example TFT with a second semiconductor material on the source and drain regions of the active layer of semiconductor material, where the second material extends above the top surface of the recessed channel region, in accordance with an embodiment of the present disclosure.

FIG. 8 is a cross-sectional view of an example embedded memory cell having a U-shaped capacitor and a TFT with a recessed channel region and a second semiconductor layer on the source and drain regions, in accordance with an embodiment of the present disclosure. FIG. 9 is a schematic view of an example TFT-based embedded memory configuration, in accordance with an embodiment of the present disclosure.

FIG. 10 is a flow chart illustrating an example method of fabricating a thin film transistor, in accordance with an embodiment of the present disclosure.

FIG. 11 illustrates an example computing system implemented with an integrated circuit including structures or techniques disclosed herein, in accordance with an embodiment of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real- world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

A thin-film transistor includes a gate electrode, a gate dielectric directly on the gate electrode, and a body of a first semiconductor material in contact with the gate dielectric. The body has a first body sidewall, a second body sidewall opposite the first body sidewall, and a top body surface between the first and second body sidewalls, the top body surface being spaced from an underlying portion of the gate dielectric by a vertical distance Dl . The thin-film transistor further includes a source region comprising a second semiconductor material different from the first semiconductor material, the source region having a source region sidewall adjacent to and in direct contact with the first body sidewall, and a top source region surface of the source region is vertically spaced from an underlying portion of the gate dielectric by a vertical distance D2, wherein D2 is greater than or equal to Dl . The thin-film transistor further includes a drain region comprising the second semiconductor material, the drain region having a drain region sidewall adjacent to and in direct contact with the second body sidewall, and a top drain region surface of the drain region is vertically spaced from an underlying portion of the gate dielectric by a vertical distance D3, wherein D3 is greater than or equal to Dl . Note that D2 and D3 may or may not be equal. The thin-film transistor further includes a first contact structure on the source region and comprising a first metal, and a second contact structure on the drain region and comprising a second metal.

General Overview

As previously explained, there are a number of non-trivial performance issues associated with TFTs. One such issue is with respect to parasitic capacitance. For instance, parasitic capacitance can result from the closely spaced metals of a back-gate electrode and the source/drain (S/D) contacts of a thin-film transistor. In such cases, noises in sense margins may occur, resulting in the lack of sensing clear on and off states. This problem is becoming particularly difficult as scaling continues to reduce the size of transistors. In addition, typical contact formation processes generally remove a portion of the underlying source and drain regions, thereby causing the metal contact to be even closer to the back-gate structure. This inadvertent thinning of the source/drain regions during contact formation is not well documented or otherwise depicted in the published literature. In any case, the increased proximity of the source/drain contact to the back-gate electrode effectively forms a parasitic capacitance that impairs TFT performance. For example, when TFTs are used as selectors (one per storage node) in an eDRAM array, a sense amplifier may fail to sense the correct value of a particular storage node (either logical“1” or“0”) by turning “on” the corresponding selector. Such failure is caused by the off-state parasitic capacitance from all of the remaining selectors that are in the off state on the same bitline. The problem is further exacerbated when the off state parasitic capacitance is elevated as the vertical thickness of the channel is reduced to attain other performance improvements, such as control over short-channel effects.

Therefore, various example embodiments in accordance with the present disclosure provide a thin-film transistor with reduced parasitic capacitance based on the distance between the back- gate electrode and the metal of the source/drain contacts. Properly maintaining or otherwise increasing the distance between the S/D contacts and the bottom gate electrode effectively reduces the parasitic capacitance in the TFT. This increase in distance can be achieved by, for example, adding a second semiconductor material on the source and drain regions to replace lost semiconductor material, which physically increases or otherwise maintains a suitable distance between the S/D contacts and bottom gate electrode. In some embodiments, the replacement source/drain materials may be coplanar with the channel region so as to maintain suitable distance), while in other embodiments the replacement source/drain regions are taller (vertically thicker) than the channel region so as to further provide an increase in physical distance between the S/D contacts and the bottom gate electrode. Numerous example embodiments will be appreciated in light of this disclosure. In addition to reducing the parasitic capacitance, TFTs in accordance with some embodiments may simultaneously realize improvements in the electrical performance of the device associated with a channel region having a reduced thickness. A reduced channel region thickness can improve electrostatics and short-channel control while also reducing or eliminating the need for targeting of contact etches, such as source and drain contact etches. In addition, recessing the channel region can be selectively performed after forming the source and drain contacts, which can allow for a self-aligned process. In some such embodiments, an active layer includes source and drain regions separated by a channel region, where the channel region has a vertical thickness that is less than the vertical thickness of the adjacent source and drain regions. For example, the channel region may be recessed to have a vertical thickness that is 50% or less compared to the vertical thickness of the source and drain regions. This reduced vertical thickness may be the case in some embodiments even when compared to the vertical thickness of the source and drain regions prior to adding a second semiconductor material on the source and drain regions. For example, in some embodiments, the vertical thickness of the channel region may be reduced by 50% or more compared to the as-formed vertical thickness. Reducing the vertical thickness of the channel region can provide for longer effective channel length as well as better threshold voltage roll-off and subthreshold swing (SS) roll-up.

Thin-film transistors having reduced parasitic capacitance and/or reduced channel thickness can have various uses, including memory applications. In some embodiments, for example, TFTs according to some embodiments of the present disclosure can be used in a memory array such as dynamic random-access memory (DRAM), embedded DRAM (eDRAM), static random-access memory (SRAM), cache or other logic integrated circuit devices. Numerous embodiments and applications will be apparent in light of this disclosure. In accordance with various embodiments of the present disclosure, a second semiconductor material for the source and drain (S/D) regions is formed/deposited/grown after opening vias for source and drain contacts. When vias are opened, some of the original source and drain region material is also inadvertently removed since the etch process is generally not sufficiently selective. In some example embodiments, the material in the source and drain regions may be intentionally and substantially removed or even completely removed as a result of the contact trench etch process. A second semiconductor material, or replacement material, can be added to the contact trenches and on the source and drain regions to replace the etched-away material of the active layer in the S/D regions. The second semiconductor material can have a thickness to elevate the top surface of the S/D regions above the top surface of the channel region. The added semiconductor material can be the same as the original material in some embodiments, but in other embodiments is compositionally different. By using the S/D contact vias to form the replacement S/D material, the process is self-aligned. In an example embodiment of the present disclosure, a thin-film transistor (TFT) includes a gate electrode formed on a substrate, a gate dielectric on the gate electrode, and an active layer of semiconductor material on the gate dielectric. The active layer includes a source region and a drain region that are spaced apart by and connected by a channel region. The channel region is above and in direct contact with the gate dielectric and physically connects the source and drain regions of the active layer. For instance, each of the source and drain regions can be adjacent to different portions of the channel region. For example, the source and drain regions are part of and connect to opposite ends or sides of the channel region. Replacement semiconductor material on the source and drain regions may extend at least to a top surface of the channel region, and in some embodiments, extends vertically above the top surface of the channel region. Metallic contact structures on the top surfaces of the replacement semiconductor material are therefore spaced from the metal back-gate electrode in part by the added thickness of the replacement material in the source and drain regions, thereby reducing the parasitic capacitance between these metals. While the present disclosure is primarily discussed for back-gate TFTs, the same principles can be applied to dual gate architecture and multilayer TFT devices, as will be appreciated in light of this disclosure.

In some embodiments, the channel region of the active layer material has a reduced thickness compared to the source and drain regions of active layer material. For example, the channel region is thinner than (e.g., has a smaller vertical thickness as measured from the gate dielectric) the source and drain regions that include both the original active layer material and replacement semiconductor material. In other embodiments, the channel region is thinner than the active layer material of the source and drain regions. In an embodiment, the TFT further includes source and drain contacts electrically connected to the source and drain regions, respectively.

In one or more embodiments, a memory cell includes a TFT with the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline. The memory cell further includes a capacitor including a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In some embodiments, a memory array includes a plurality of wordlines extending in a first direction, a plurality of bitlines extending in a second direction crossing the first direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In some embodiments, the memory array is an embedded memory, e.g., formed in the BEOL process above and electrically connected to frontend or front-end-of-line (FEOL) circuits including memory control circuits such as wordline drivers (electrically connected to the wordlines) and sense amplifiers (electrically connected to the bitlines). In this fashion, the BEOL circuits (memory array) can overlay the FEOL circuits (memory control) and save integrated circuit planar area. As such, embodiments of the present disclosure can be applied to smaller process technologies, such as 14 nanometer (nm), 10 nm, 7 nm, 5 nm, and beyond.

The term“compositionally different” as used herein with respect to semiconductor materials or features/lay ers/structures including semiconductor material means (at least) including different semiconductor materials or including the same semiconductor material but with a different elemental ratio.

As also used herein, the expression“X includes at least one of A or B” refers to an X that may include, for example, just A only, just B only, or both A and B. To this end, an X that includes at least one of A or B is not to be understood as an X that requires each of A and B, unless expressly so stated. For instance, the expression“X includes A and B” refers to an X that expressly includes both A and B. Moreover, this is true for any number of items greater than two, where“at least one of’ the items is included in X. For example, as used herein, the expression“X includes at least one of A, B, or C” refers to an X that may include just A only, just B only, just C only, only A and B (and not C), only A and C (and not B), only B and C (and not A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. To this end, an X that includes at least one of A, B, or C is not to be understood as an X that requires each of A, B, and C, unless expressly so stated. For instance, the expression“X includes A, B, and C” refers to an X that expressly includes each of A, B, and C. Likewise, the expression“X included in at least one of A or B” refers to an X that may be included, for example, in just A only, in just B only, or in both A and B. The above discussion with respect to“X includes at least one of A or B” equally applies here, as will be appreciated.

Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate, for example, a thin-film transistor including source and drain regions of equal or greater height than the channel region therebetween. In another example, such tools may also indicate replacement source and drain material that is distinct from, yet connected to the body or channel region, in accordance with various embodiments of the present disclosure. For example, TEM can be useful to show a cross section of the device structure. In a further example, scanning spreading resistance microscopy (SSRM) can be used to identify a boundary between the channel and source/drain regions based on conductivity of the material. In some embodiments, the techniques described herein may be detected based on the benefits derived from their use, which includes thin-film transistors with reduced parasitic capacitance.

Architecture and Methodology

FIGS. 1-7 illustrate cross-sectional (X-Z) views of example embodiments of a thin-film transistor (TFT) 100, according to various embodiments of the present disclosure. The TFT 100 includes a gate electrode 120 formed on an insulating substrate 110, a gate dielectric 130 on the gate electrode 120, and an active layer 140 on the gate dielectric layer 130. The active layer 140 includes a source region 142 and a drain region 144 spaced apart and connected to opposite portions of a channel region 146 positioned therebetween. The active layer 140 forms a transistor device with the gate electrode 120 and gate dielectric 130. In some embodiments, when a gate signal is supplied to the gate electrode 120, the active layer 140 becomes conductive, and current flows between the source and drain regions 142 and 144 via the channel region 146. In other embodiments, supplying a gate signal to the gate electrode 120 results in charge accumulating in the channel region 146, such as in memory structures.

Throughout this disclosure, TFTs are discussed with reference to a substrate being oriented in a horizontal plane, where the z-axis represents a vertical dimension (e.g., perpendicular to the substrate), while the x-axis and y-axis each represent horizontal dimensions (e.g., parallel to the wordline and bitline directions, respectively). Accordingly, terms referencing direction, such as upward, downward, vertical, horizontal, left, right, front, back, etc., are used for convenience to describe embodiments of TFTs having such an orientation. The present disclosure, however, is not limited by these directional references and it is contemplated that TFTs of the present disclosure may have any orientation.

Additionally, although layers and structures may be illustrated as having straight, orthogonal sidewalls, the actual geometry of the TFT 100 may include sloped sidewalls (e.g., 5° from vertical), residual material along edges of features, and other deviations from the geometries shown in the figures. For example, the source region 142 and drain region 144 may exhibit a concave profile due to etching to open the vias 182, where residual material of the active layer 140 is present along sidewalls or corners of the vias 182.

Referring to FIG. 1, a cross-sectional view shows an example structure of a partially completed TFT 100 during processing for source and drain contacts. Here, the gate electrode 120, gate dielectric 130, and active layer 140 have been formed. An isolation layer 180 is on the active layer 140 and the gate dielectric 130. Vias 182 defined in the isolation layer 180 are aligned with and extend to the source and drain regions 142, 144 of the active layer 140. In conventional processing, opening vias 182 as shown may be performed for depositing metal contacts on the source and drain regions 142, 144. When opening the vias 182 in the isolation layer 180, the etch process used to do so may etch into (or through) the material of the active layer 140 at the source and drain regions 142, 144. The result is that the active layer 140 in the source and drain regions 142, 144 has a reduced thickness compared to the channel region 146 at this stage of processing. In conventional processing, source and drain contacts 160, 164 would be deposited on the thinned active layer 140 at the source and drain regions 142, 144. The result, however, would be that the vertical spacing between the gate electrode 120 and the metal of the source and drain contacts 160, 164 (shown in FIGS. 2-5) is similarly reduced and the parasitic capacitance between these metal layers therefore increases. To reduce the parasitic capacitance associated with the source and drain contacts, a layer of semiconductor material can be formed on the source and drain regions 142, 144 to replace and even supplement the etched-away material of the active layer 140.

In example embodiments shown in FIGS. 2-5, the TFT 100 includes a replacement semiconductor layer 150 that replaces the etched-away material of the active layer 140 in the source region 142 and drain region 144. The replacement semiconductor layer 150 may be the same or different material compared to the active layer 140. In some embodiments, the replacement semiconductor layer 150 supplements the material in the source and drain regions 142, 144 to exceed the original thickness of the active layer 140. In some embodiments, the replacement semiconductor layer 150 is formed on the thinned material of the active layer 140 in the source and drain regions 142, 144. For example, the replacement semiconductor layer 150 includes a replacement source layer 152 and a replacement drain layer 154 on the active layer material of the source region 142 and drain region 144, respectively, where a portion of the active layer 140 remains in the source and drain regions 142, 144. In other embodiments, the active layer 140 may be etched through to the gate dielectric 130 or completely removed in the source and drain regions 142, 144. In such embodiments, the replacement source layer 152 and/or replacement drain layer 154 is formed directly on the gate dielectric 130 and any remaining portion of the active layer material in the source region 142 and drain region 144, respectively. After forming the replacement semiconductor layer 150 in the source and drain regions 142, 144, source and drain contacts 160, 162 can be formed on a top of the replacement source layer 152 and replacement drain layer 154, respectively. A passivation or dielectric layer 185 is formed on the structure and planarized to reveal the contacts in preparation for further processing. Each component layer of the TFT 100 will be discussed in more detail below.

Referring to FIG. 2, a cross-sectional view illustrates a TFT 100 with the replacement semiconductor layer 150 in accordance with an embodiment of the present disclosure. As illustrated, the source region 142 and drain region 144 of the active layer 140 have been recessed compared to the channel region 146 to result a reduced thickness of active layer 140 material in the S/D regions 142, 144. For example, the active layer 140 material in the source and drain regions 142, 144 may have a vertical thickness from 1 nm to 10 nm compared to a vertical thickness of 10 nm to 20 nm in the channel region 146. In another example, the active layer 140 material in the source and drain regions 142, 144 may have a vertical thickness from 10 to 20 nm compared to a vertical thickness of 20 to 40 nm in the channel region 146.

A replacement semiconductor layer 150 is directly on the active layer 140 of the recessed source and drain regions 142, 144, thereby defining a replacement source layer 152 and a replacement drain layer 154, in accordance with some embodiments. Source and drain contacts 160, 162 directly contact the replacement source layer 152 and replacement drain layer 154, respectively. In some embodiments, the vertical thickness of the replacement semiconductor layer 150 is selected so that the top surface of the source and drain regions 142, 144 is coplanar with or above the top surface l46a of the channel region 146, where the source and drain regions 142, 144 may include material of the replacement semiconductor layer 150 and the active layer 140. In other embodiments, the top surface of the source and drain regions 142, 144 may be below the top surface l46a of the channel region 146 at this stage of processing, such as when the channel region 146 will subsequently be thinned.

The top surface of the channel region 146 is spaced from the gate electrode 120 by a vertical distance Dl, the top surface of the source region 142 is spaced from the gate electrode 120 by a vertical distance D2, and the top surface of the drain region 144 is spaced from the gate electrode 120 by a vertical distance D3. In some embodiments, each of vertical distance D2 and vertical distance D3 is equal to or greater than vertical distance Dl . Vertical distance D2 and vertical distance D3 may or may not be equal.

In some embodiments, the replacement semiconductor layer 150 has a thickness of at least 5 nm, including 5-10 nm, 5-15 nm, 5-20 nm, 10-15 nm, and 15-20 nm 5-20 nm or 10-30 nm. The thickness may have a specific value in some embodiments, such as 5 nm, 10 nm, 15 nm, 20 nm, or greater. In some embodiments, the active layer 140 in the source and drain regions 142, 144 may have a thickness from 0-20 nm. Thus, in some embodiments, the source and drain regions 142, 144 may have a vertical thickness from 10-40 nm based on the combined thickness of the active layer 140 and replacement semiconductor layer 150. In any of these embodiments, the thickness of the replacement semiconductor layer 150 (or the combined thickness of the source and drain regions 142, 144) can be formed with a maximum value so as to not increase the contact resistance beyond a predefined value. For example, the replacement semiconductor material can have a thickness of not greater than 50 nm, including not greater than 30 nm, not greater than 20 nm, or not greater than 10 nm. Referring to FIG. 3, a cross-sectional view illustrates a TFT 100 with replacement semiconductor layer 150 in the source and drain regions 142, 144 and replacing the material of the active layer 140, in accordance with another embodiment of the present disclosure. In the embodiment of FIG. 3, material of the active layer 140 in the source region 142 and drain region 144 has been etched through completely to the gate dielectric 130 to completely remove the material of the active layer 140 in the source and drain regions 142, 144. In other embodiments, a residual layer (e.g., <5 nm thickness) of active layer 140 material may remain in the source and drain regions 142, 144. When the active layer material is completely removed in the source and drain regions 142, 144, replacement semiconductor layer 150 is deposited, grown, or formed on the gate dielectric 130 and in contact with ends or sides of the channel region 146. The resulting structure may exhibit semiconductor material in the source and drain regions 142, 144 that is different from the material in the channel region 146. In other embodiments, the replacement semiconductor layer 150 is the same material as the active layer 140, except perhaps for the presence and/or concentration of dopants.

In some instances, the top surfaces of the source region 142, channel region 146, and drain region 144 are coplanar, resulting in a semiconductor layer of substantially uniform thickness along the source region 142, channel region 146, and drain region 144. In other instances, the top surfaces of the source region 142, channel region 146, and drain region 144 are not coplanar, such as when the source and drain regions 142, 144 extend vertically above the channel region 146. As with the embodiments discussed above, the replacement semiconductor layer 150 can have a vertical thickness from to 5-20 nm or greater and/or have a thickness so that the top surface of the replacement semiconductor layer 150 is at least as high or higher than the top surface l46a of the channel region 146, in accordance with some embodiments.

Referring to FIG. 4, a cross-sectional view illustrates a TFT 100 with replacement semiconductor layer 150 in accordance with yet another embodiment of the present disclosure. In this embodiment, the replacement semiconductor layer 150 extends above the top surface l46a of the channel region 146 of active layer 140. The resulting structure may exhibit semiconductor material in the source and drain regions 142, 144 that is different from the material of the channel region 146, and where the top surfaces of the source and drain regions 142, 144 are not coplanar with (e.g., are higher than) the top surface l46a of the channel region 146. The source and drain regions 142, 144 may also exhibit a combination of semiconductor materials that includes active layer 140 material and a different replacement semiconductor layer 150. In other embodiments, the replacement semiconductor layer 150 is the same material as the active layer 140, except perhaps for the presence and/or concentration of dopants. Further, in some embodiments, the replacement semiconductor layer 150 at each of the source and drain regions 142, 144 may exhibit a wedge shape that increases in size as it extends in a vertical direction. Thickness values of the replacement semiconductor layer 150 discussed above may also apply to this embodiment. In one example, the replacement source layer 152 and replacement drain layer 154 each has a thickness of 5-20 nm and the active layer 140 has a thickness of 5-20 nm in the source and drain regions 142, 144. The combined thickness of the replacement semiconductor layer 150 and active layer 140 in the source and drain regions 142, 144 may be from 10 to 40 nm. In comparison, the channel region 146 may have a thickness that is generally less than the thickness of the source and drain regions, such as of 5-20 nm, in accordance with some embodiments.

Here, the top surface of the channel region 146 is spaced from the gate electrode 120 by a vertical distance Dl that is less than vertical distance D2 and vertical distance D3. As with embodiments discussed above, vertical distance D2 may or may not be equal to vertical distance D3.

In some instances, TFTs 100 may not have adequate electrostatic gate control due at least in part to the thickness of the channel region 146. Such devices can suffer from subthreshold swing (SS) degradation and high operating voltages. The use of thin channel region materials can undesirably increase parasitic capacitance and can make Damascene contact etch very challenging due to the aggressive etch chemistry involved. For example, if the active layer 140 is too thin, subsequent processing can blow through the active layer material. For example, chemical mechanical planarization (CMP) and other processing with little to no selectivity can inadvertently remove more channel material than desired, compromising the integrity of the TFTs.

Accordingly, reducing the thickness of the channel region 146 can reduce or eliminate some or all of the degrading thick-body effects in accordance with some embodiments. In one example, the channel region 146 can be recessed in a self-aligned process after forming the source and drain contacts 160, 162, where a portion of the exposed channel region 146 between the source and drain regions 142, 144 is removed using a suitable process.

Referring now to FIGS. 5-7, cross-sectional views illustrate additional embodiments of TFTs 100 in accordance with embodiments of the present disclosure. Here, the thickness of the channel region 146 has been reduced compared to the thickness of the active layer 140 as formed. Generally, the thickness of the channel region 146 is less than the channel regions 142, 144, which include replacement semiconductor layer 150. In some embodiments, the thickness of the active layer 140 in the channel region 146 is less than the thickness of the active layer 140 in the source and drain regions 142, 144. Similar to embodiments discussed above, the top surface of the channel region 146 is spaced from the gate electrode 120 by a vertical distance Dl that is equal to or less than vertical distance D2 for the top surface of the source region 142 and vertical distance D3 for the top surface of the drain region 144. As with embodiments discussed above, vertical distance D2 and vertical distance D3 may or may not be equal.

FIG. 5 illustrates one embodiment of TFT 100 where the source and drain regions 142, 144 include material of active layer 140 in addition to replacement source and drain layers 152, 154, respectively. Source and drain contacts 160, 162 are formed on top of the replacement source and drain layers 152, 154, respectively. In the embodiment of FIG. 5, replacement source and drain layers 152, 154 are added in an amount to replace the material of the active layer 140 that was removed during opening vias 182 for processing the source and drain contacts 160, 162. The result is that the replacement source and drain layers 152, 154 return the thickness of the source and drain regions 142, 144, respectively, to be about equal to the thickness of the active layer 140 as formed (e.g., 20-40 nm). In some embodiments, the resulting thickness of the source and drain regions 142, 144 may be somewhat greater or less than the original thickness of the active layer 140, but the thickness is generally commensurate with the layer thickness as deposited/formed. Here, the channel region 146 has been recessed to have a thickness that is reduced compared to the thickness of the source and drain regions (including replacement semiconductor layer 150) and compared to the recessed material of active layer 140 in the source and drain regions 142, 144. In one example, the channel region 146 has a thickness of 4-7 nm. In another example, the channel region has a thickness of 5-10 or 5-15 nm. The source and drain regions 142, 144 have a thickness of 10-20 nm, including about 5-10 nm of replacement semiconductor layer 150, for example.

FIG. 6 illustrates another embodiment of TFT 100 where the source and drain regions 142, 144 include material of replacement semiconductor layer 150. In some embodiments, source and drain regions 142, 144 include only the material of replacement semiconductor layer 150, such as when S/D contact processing removes all or substantially all (e.g., <1 nm remaining) of the active layer 140 material in the source and drain regions 142, 144. In other embodiments, the source and drain regions 142, 144 may include a residual amount of active layer 140 material, such as when active layer 140 is etched through to the gate dielectric 130 in some areas of the source and drain regions 142, 144 or when the active layer 140 in the source and drain regions 142, 144 has a thickness less than 2 nm, for example. As with the embodiment discussed above with reference to FIG. 5, source and drain contacts 160, 162 are formed on top of the replacement source and drain layers 152, 154, respectively.

In the embodiment of FIG. 6, replacement source and drain layers 152, 154 replace the material of the active layer 140 that was intentionally or inadvertently removed during processing for the source and drain contacts 160, 162, for example. The replacement source and drain layers 152, 154 may return the thickness of the source and drain regions 142, 144, respectively, to be about equal to the original thickness of the active layer 140 as formed (e.g., 20-40 nm). In some embodiments, the resulting thickness of the source and drain regions 142, 144 may be generally commensurate with the active layer 140 thickness as deposited/formed. In other embodiments, the resulting thickness of the source and drain regions 142, 144 can be significantly greater (e.g., 1 5x, 2. Ox, 3. Ox, etc.) than the thickness of the active layer 140 as deposited/formed. As with the embodiment of FIG. 5 discussed above, the channel region 146 in this embodiment has been recessed to have a thickness that is less than the thickness of the source and drain regions with replacement semiconductor layer 150. However, the remaining material of active layer 140 in the source and drain regions 142, 144, if any, may have a reduced thickness compared to the recessed channel region 146. In one example, the channel region 146 has a thickness of 4-7 nm and the source and drain regions 142, 144 have a thickness of 10-20 nm, where most or all of the material in the source and drain regions 142, 144 is replacement semiconductor layer 150.

FIG. 7 illustrates yet another embodiment of a TFT 100 where the source and drain regions 142, 144 include material of active layer 140 in addition to replacement source and drain layers 152, 154, respectively. As with the embodiments of FIGS. 5-6, source and drain contacts 160, 162 are formed on top of the replacement source and drain layers 152, 154, respectively. In the embodiment of FIG. 7, replacement source and drain layers 152, 154 are added in an amount to replace and exceed the amount of active layer 140 material that was removed. The resulting thickness of the source and drain regions 142, 144 is greater than (e.g., l .5x, 2. Ox, 3. Ox, etc.) and sometimes far exceeds the original thickness of the active layer 140 as deposited/formed. Stated another way, the resulting thickness of the source and drain regions 142, 144 is greater than (e.g., 2. Ox, 3. Ox, 4. Ox, 5. Ox, 6. Ox, etc.) and sometimes far exceeds the final thickness of the recessed channel region 146. In one example, the channel region 146 has a thickness of 4-7 nm while the source and drain regions 142, 144 have a thickness of about 10-30 nm, including about 10-20 nm of replacement semiconductor layer 150, for example.

As illustrated in FIG. 7, for example, the replacement source layer 152 and replacement drain layer 154 can have a tapered shape that increases in size as the layer extends upward. Such a shape provides a top surface with a greater area than the active layer 140 in the source or drain region 142, 144. This increased area enables metal contacts to be formed with reduced contact resistance. The tapered shape may result from forming the replacement semiconductor layer 150 in vias 182 having the form of a trench in the isolation layer 180, for example.

According to various embodiments, the thickness of the recessed channel region 146 can be a particular fraction of the thickness of the source and drain regions 142, 144 (including replacement semiconductor layer 150), such as three quarters or less than the thickness of the source and drain regions 142, 144, e.g., one half, one third, one quarter, one fifth, or one sixth. As illustrated, the channel region thickness is the vertical direction perpendicular to the substrate 110, such as a substrate of an integrated circuit incorporating the TFT 100. In some embodiments, the thickness of the recessed channel region 146 can be an absolute thickness, such as from 5 to 20 nm, from 7 to 15 nm, from 4-7 nm, or some particular thickness such as 5 nm or 10 nm. For example, a channel region 146 with a thickness of 40 nm as formed can be recessed to a thickness of 20 nm, 14 nm, 10 nm, or 5 nm in some embodiments. However, since performance can be improved for even small reductions in thickness of the channel region 146, the channel region 146 is thinned in some embodiments to 30 nm or about three fourths of the thickness of the active layer 140 as formed.

As shown in the embodiments of FIGS. 2-7, source and drain contacts 160, 162 are deposited on the top of the replacement source and drain layers 152, 154, respectively, in accordance with some embodiments. For example, the source and drain contacts 160, 162 are deposited on top of the replacement semiconductor layer 150 in vias 182 after partially filing the vias 182 with replacement semiconductor layer 150. When the same vias 182 are used for forming the replacement semiconductor layer 150 and for depositing the source and drain contacts 160, 162, the contacts are self-aligned with the replacement semiconductor layer 150 in the source and drain regions 142, 144.

The source and drain contacts 160, 162 can be formed, for example, by contact etching the material of the source and drain regions 142 and 144, respectively. In some embodiments, a contact metal is annealed, etched, or otherwise formed on or combined with the tops of the source and drain regions 142 and 144 to make contacts with the replacement semiconductor layer 150. For example, a silicide or other appropriate compound, depending on the contact metal, is formed as a contact on the replacement semiconductor layer 150. Example contact metals include titanium nitride (e.g., TiN, TiN x with 0.6 < x < 1.2), copper (Cu), tungsten (W), titanium oxynitride (e.g., TiO x N y with x > 0 and y > 0), titanium (Ti), tantalum (Ta), tantalum nitride (e.g., TaN), aluminum titanium nitride (e.g., AlTi x N y with 0 < x < 1 and y > 0), tantalum titanium nitride (e.g., TaTi x N y with x > 0 and y > 0), aluminum tantalum nitride (e.g., AlTa x N y with x > 0 and y > 0), tungsten nitride (e.g., W 2 N, WN, WN 2 ), indium arsenide (InAs), and indium oxide (e.g., Ih 2 0 3 , InO x with x > 0), to name a few. Source and drain electrodes can subsequently be formed on the source and drain contacts 160, 162. In some embodiments, the source and drain contacts 160, 162 may be metal, such as copper interconnect, formed by a damascene process using chemical mechanical planarization (CMP).

A passivation layer 185 is shown in the figures as being formed over the structure of the TFT and planarized to reveal the source and drain contacts 160, 162, The passivation layer 185 can be one or more of aluminum oxide, gallium oxide, silicon nitride, silicon dioxide, titanium dioxide, hafnium dioxide, silicon oxynitride, aluminum silicate, tantalum oxide, hafnium tantalum oxide, aluminum nitride, aluminum silicon nitride, sialon, zirconium dioxide, hafnium zirconium oxide, tantalum silicate, and hafnium silicate, to name a few examples.

In one example embodiment, the active layer 140 is formed with a thickness of 5-40 nm prior to opening vias 182 in the isolation layer 180. After opening vias 182, the thickness of the source and drain regions 142, 144 of the active layer 140 may be reduced to a value from 0 to 20 nm, for example. Material of the replacement semiconductor layer 150 is then added to source and drain regions 142, 144 so that the top surface of the replacement semiconductor layer 150 is even with or above the top surface l46a of the channel region 146. Replacement semiconductor layer 150 may be formed on the gate dielectric 130, on the active layer 140, or both. In some embodiments, the top surface of the replacement semiconductor layer 150 is 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, or more above the top surface l46a of the channel region 146. In some embodiments, the source region 142 and drain region 144 of the active layer 140 are doped, while the channel region 146 is left undoped or minimally doped (e.g., < 1E15 cm 3 ). The doping may be sufficient to make the active layer 140 material in the source and drain regions 142 and 144 conductive.

The active layer 140 of the TFT 100 can be a semiconductor material with a single-crystal, polycrystalline, or amorphous structure, in accordance with some embodiments. For example, in embodiments suited for eDRAM applications, the active layer 140 can be amorphous semiconductor material, such as hydrogenated amorphous silicon (a-Si:H), polysilicon, zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium-zinc oxide (IZO), indium-molybdenum oxide (IMO), and zinc-tin oxide (ZTO) to name a few examples. In other embodiments, the active layer 140 can be any one of a variety of polycrystalline semiconductors including, for example, zinc oxynitride (ZnON, such as a composite of zinc oxide (ZnO) and zinc nitride (Zn 3 N 2 ), or of ZnO, ZnO x N y , and Zn 3 N 2 ), indium tin oxide (ITO), tin oxide (e.g., SnO), copper oxide (e.g., Cu 2 0), polycrystalline germanium (poly-Ge) silicon-germanium (e.g., SiGe, such as Sii- x Ge x ) structures (such as a stack of poly-Ge over SiGe), and the like. In some embodiments, the active layer 140 is formed from a material of a first conductivity type, which may be an n-type or a p-type channel material. An n-type channel material may include one or more of indium tin oxide (ITO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), amorphous silicon, zinc oxide, amorphous germanium, polysilicon, poly germanium, and poly- III-V like indium arsenide (e.g., InAs). On the other hand, a p-type channel material may include one or more of amorphous silicon (a-Si), zinc oxide (e.g., ZnO), amorphous germanium (a-Ge), polysilicon (polycrystalline silicon or poly-Si), poly germanium (polycrystalline germanium or poly-Ge), poly- III-V like InAs, copper oxide (CuO), tin oxide (SnO), and any chalcogenide glass (including but not limited to germanium antimony tellurium (Ge x Sb y Te z )). In some embodiments, the active layer 140 can have a thickness in a range of about 5 nm to about 50 nm. In various embodiments, the material of the replacement semiconductor layer 150 may be the same or different material compared to the active layer 140. In some embodiments, the replacement semiconductor layer 150 comprises germanium, silicon, indium arsenide (InAs), gallium arsenide (GaAs), indium gallium arsenide (In x Gai -x As), indium phosphide (InP), indium antimonide (InSb), or gallium antimonide (GaSb), to name a few examples. In some embodiments, the replacement semiconductor layer 150 is doped. The doping may be sufficient to make replacement source and drain regions 152, 154 conductive. The material of the replacement semiconductor layer 150 is selected in some embodiments so that the conduction band minimum of the replacement semiconductor material is equal to or up to 0.5 eV greater than the conduction band minimum (CBM) of the active layer 140. In some embodiments, the CBM of the replacement semiconductor material is equal to or up to 0.2 eV greater than the CBM of the active layer material.

The gate dielectric 130 can be an insulating material or high-k dielectric, such as hafnium oxide (Hf0 2 ), alumina (AI2O3), tantalum oxide (Ta 2 0 5 ), titanium dioxide (Ti0 2 ), zirconium oxide (Zr0 2 ), lanthanum oxide (La 2 0 3 ), silicon dioxide (Si0 2 ), or silicon nitride (S13N4), to name a few examples. The gate dielectric 130 functions to electrically isolate the gate electrode 120 from the active layer 140. In some embodiments, the gate dielectric 130 has a thickness from 2 nm to 50 nm, including 2- 10 nm, 5-15 nm, 10-20 nm, 20-30 nm, 30-40 nm, and 40-50 nm. Other thicknesses are acceptable as deemed appropriate for a given application.

The gate electrode 120 can be a semiconductor, a metal, or other conducting material. For example, the gate electrode 120 can include thin-film layers such as one or more gate electrode layers (e.g., diffusion barrier and metal gate layers). The diffusion barrier can be a metal- or copper-diffusion barrier, such as a conductive material to reduce or prevent the diffusion of metal or copper from a wordline into the metal gate electrode 120 while still maintaining an electrical connection between the wordline and the metal gate electrode 120. For example, the diffusion barrier can be tantalum nitride (TaN), tantalum (Ta), titanium zirconium nitride (e.g., TίcZh-cN, such as X = 0.53), titanium nitride (e.g., TiN), titanium tungsten (TiW), combination (such as a stack structure of TaN on Ta), or the like.

In some embodiments, the diffusion barrier can include a single- or multi-layer structure that includes a compound of tantalum(Ta) and nitrogen(N), such as TaN or a layer of TaN on a layer of Ta. In some embodiments, a layer of etch-resistant material (e.g., an etch stop) such as silicon nitride (e.g., S13N4) or silicon carbide (e.g., SiC) is formed over the wordline with vias for a metal (or copper) diffusion barrier film such as TaN or a TaN/Ta stack. The gate electrode 120 can be a conductive material on the diffusion barrier, such as a metal, a conductive metal oxide or nitride, or the like. For example, in one embodiment, the gate electrode 120 is titanium nitride (TiN). In another embodiment, the gate electrode 120 is tungsten (W).

In some embodiments, the substrate 110 is an insulating material that is not active in device operation. For example, the substrate 110 is glass, a high-k dielectric, or other insulating material. In some embodiments, the substrate 110 includes a semiconducting base with a layer of insulating material on a top surface, such as an oxide or nitride layer formed on a silicon base. Such embodiments may be used when the TFT is formed on a substrate 110 that also includes other semiconductor devices, for example.

Referring now to FIG. 8, a cross-sectional (X-Z) view illustrates an example structure of an embedded memory cell 400 having a U-shaped capacitor 420 and a TFT 100 with replacement semiconductor layer 150 in the source and drain regions 142, 144, in accordance with an embodiment of the present disclosure. Replacement semiconductor layer 150 defines replacement source layer 152 on source region 142 and replacement drain layer 154 on drain region 144. Replacement semiconductor layer 150 raises the height of source contact 160 and drain contact 162 relative to the gate electrode 120, thereby reducing parasitic capacitance associated with the source and drain contacts 160, 162. The memory cell 400 may also exhibit improved electrostatic gate control and/or short-channel effects achieved by a channel region 146 of reduced thickness. The active layer 140 of FIG. 9 is illustrated as having an irregular top surface profile due to source and drain regions 142, 144 being recessed during metal contact processing, and due to recessing the channel region 146 of the active layer 140.

In the memory cell 400 of FIG. 8, a metal bitline 470 (e.g., metal interconnect material, such as copper, aluminum, or tungsten) is formed on the source contact 160. The bitline 470 is used, for example, to program or sense the capacitance of a capacitor 420 through the source region 142 of the TFT 100 in the on state. In addition, a storage node 480 (e.g., further metal interconnect material) is formed on the drain contact 162. The storage node 480 electrically connects the drain contact 162 to the capacitor 420 to write (e.g., program) or read (e.g., sense) the capacitance (e.g., logical 1 or 0) of the capacitor 420 (e.g., through the bitline 470 when the TFT 100 is in the on state). In some embodiments, the bitline 470 is used in combination with the storage node 480 to program or sense the state of a capacitor when the TFT 100 is used as part of a memory device (such as a DRAM cell). In some other embodiments, the TFT 100 acts as a switch, controlling an electrical current between the storage node 480 and bitline 470. In some embodiments, the roles of the source contact 160 and drain contact 162 are reversed, where the drain contact 162 is connected to the bitline 470 and the source contact 160 is connected to the storage node 480.

The capacitor 420 has a U-shaped structure, with first and second terminals 422 and 424, and a U-shaped dielectric 426. The U-shape can take advantage of the thicker metal interconnection layers to etch a relatively deep trench to boost capacitive surface area and capacitance without increasing planar area. The first and second terminals 422 and 424 can be metals or other conductive materials (e.g., metal, conductive metal nitride or carbide, or the like), while the dielectric 426 can be an insulator to electrically separate the first and second terminals 422 and 424, allowing a capacitance to be formed between the first and second terminals 422 and 424. In one embodiment, the first terminal 422 is tantalum (Ta), titanium nitride (TiN), titanium aluminum nitride (e.g., TiAlN, where the molar amount of titanium is at least that of aluminum), tantalum aluminum carbide (TaAlC), or tantalum nitride (TaN), to name a few examples. In one embodiment, the second terminal 424 is TiN or Si0 2 , for example. In some embodiments, the dielectric 426 is a high-k dielectric material such as zirconium dioxide (Zr0 2 ) or aluminum oxide (AbO,) to reduce tunneling.

The first terminal 422 is electrically connected to the drain contact 162 via the storage node 480. The second terminal 424 can be electrically connected, for example, to a common or programmable voltage (such as a ground voltage), or to a plate line (e.g., to all the memory cells 400 sharing the same wordline driving the gate 120) for supplying a common or programmable voltage. In some embodiments, the first terminals 422 of a plurality of such capacitors 420 (e.g., belonging to memory cells coupled to the same wordline) can be electrically insulated from each other while the second terminals 424 of the plurality of capacitors 420 are electrically connected to each other through a shared capacitor plate or plate line at the top of the capacitors 420. Separate arrays of capacitors 420 may have separate capacitor plates (e.g., one for each wordline). The capacitor plates may be coupled to a common voltage line to supply a common voltage to all the second terminals 424 through the capacitor plate. Unless otherwise described herein, verbs such as“coupled” or“couple” refer to an electrical coupling (such as capable of transmitting an electrical signal), either directly or indirectly, such as through one or more conductive layers.

The source contact of the TFT 100 is continuous and is used as the bitline 470 of the memory cell 400. By selecting the thickness of the replacement semiconductor layer 150, the heights of the source and drain contacts 160, 162 can be optimized to reduce bitline capacitance (e.g., between the source and drain contacts) for better sensing margins. The source contacts of the TFTs 100 also serve as the bitlines of an embedded memory array. The dimensions of the source contacts 160 (bitlines 470) can be customized for lower inter-metal capacitance (e.g., by using a separate fabrication stage to form the bitlines 470 versus the fabrication stage for this metal level in areas of the integrated circuit outside of the memory array). Each capacitor 420 connects to a drain contact 162 (e.g., via storage node 480) of the TFT 100.

Referring now to FIG. 9 a schematic view (X-Y) illustrates an example of a TFT-based embedded memory array configuration, according to an embodiment of the present disclosure. The array configuration includes a plurality of wordlines 490 extending in a first direction (e.g., an X-direction), a plurality of bitlines 470 extending in a second direction (e.g., a Y-direction) crossing the first direction, and a plurality of memory cells 400 at crossing regions of the wordlines 490 and the bitlines 470. Each memory cell 400 includes a TFT 100 and a capacitor 420 and is driven by a unique pair of wordline 490 and bitline 470. Each wordline 490 is selected by a corresponding wordline driver 495, while the corresponding bitlines 470 are used to sense the state of the capacitor 420 (e.g., logical 1 or 0) of each of the corresponding bits of the selected wordline 490. In some embodiments, a reference column of memory cells 400 provides a corresponding reference signal (e.g., halfway between a logic low value and a logic high value) over a reference bitline 470 concurrently with the sensing of the desired bit on the bitline 470. A sense amplifier 460 compares the two values to determine whether the desired bit is a logic high value (e.g., 1) or a logic low value (e.g., 0). The memory cells 400 are embedded in BEOL layers while the peripheral circuits responsible for memory operation, including the read sense amplifiers 460, bitline driver circuits 475, and wordline driver circuits 495, are placed below the memory array to reduce area of the embedded memory.

Fabrication

Referring now to FIG. 10, a flow chart illustrates processes in a method 200 of fabricating a thin-film transistor 100 (TFT) in accordance with some embodiments. In general, TFTs 100 according to the present disclosure can be fabricated using any suitable semiconductor fabrication techniques, including deposition, photolithography, wet or dry chemical etching processes, chemical mechanical polishing, deposition or epitaxial growth processes (e.g., CVD, PVD, ALD, VPE, MBE, LPE), melt regrowth, and/or any other suitable processing, as will be appreciated. The components of TFT 100 can be part of a backend process, such as the back end of line (BEOL) process of a semiconductor integrated circuit. As such, the components of TFT 100 can be fabricated as part of, or concurrently with, the metal interconnection layers of a semiconductor fabrication process. In another embodiment, the components of TFT 100 are fabricated on a substrate as part of a front end of line (FEOL) process. In example embodiments, fabrication of the components of TFT 100 can be part of the metal (interconnect) layer of a BEOL process.

Method 200 begins by forming 205 a gate electrode (or gate) on a substrate, such as on an interlayer dielectric (ILD), glass, or other non-conductive material. The gate electrode is conductive, and can represent one or more layers or features for supplying a gate signal to the TFT 100. For instance, the gate electrode can include a wordline to supply a gate signal from a wordline driver, along with diffusion barriers and a metal gate electrode for supplying the gate signal to the proximity of the channel region of the TFT. Method 200 continues with forming 210 a gate dielectric on the gate electrode, where the gate dielectric corresponds to the location of the active layer of semiconductor material of the TFT. The gate dielectric can be a high-k dielectric material such as hafnium dioxide (Hf0 2 ), silicon dioxide (Si0 2 ), silicon nitride (e.g., S13N4), or other high-k material, for example. In some embodiments, the gate dielectric is a multi-layer stack including, for example, a first layer of Si0 2 and a second layer of a high-k dielectric such as Hf0 2 on Si0 2 . Any number of gate dielectrics can be used, as will be appreciated in light of the present disclosure. In some embodiments, the gate dielectric has a thickness in a range from 2 nm to 10 nm, including 4-7 nm.

Method 200 continues with forming 215 an active layer of semiconductor material on the gate dielectric. In some embodiments, the active layer 140 has a thickness from 30 to 60 nm. In other embodiments, the thickness is from 20 nm to 80 nm. In some embodiments, the active layer material can be formed in a backend process, for example, from one or more of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and amorphous germanium (a-Ge). For example, the active layer 140 is electrically coupled to a bitline 470 via the source region and a storage node 480 via the drain region 144 of the active layer (shown in FIG. 8).

Method 200 continues with forming 220 an isolation layer on the active layer, followed by planarization with chemical mechanical polishing or other suitable process. The isolation layer can be silicon dioxide (Si0 2 ), silicon nitride (e.g., S13N4), or other insulating material. In some embodiments, the isolation layer has a thickness from 20 nm to 300 nm or greater.

Method 200 continues with forming 225 openings or vias in the isolation layer that extend to the source and drain regions. In some embodiments, the vias may be formed 225 by first masking off the surrounding areas and then using an anisotropic etch process to form the openings in the isolation layer that extend to the active layer. In some cases, forming 225 the vias may result in removal of part or all of the material of the active layer in the source and drain regions. In such a case, the gate dielectric may function as an etch stop. The depth of the vias is selected to accommodate a layer of replacement semiconductor material on the source and drain regions and source and drain contacts (e.g., metal) deposited on the replacement semiconductor material. Accordingly, the vias may have a depth from 20 nm - 300 nm as may be determined by the thickness of the isolation layer after planarization. Generally, as the depth of the vias increases, the vias will tend to have a more tapered shape that is smaller in size at the source or drain region and larger in size at the opening in the isolation layer.

Method 200 continues with forming 230 a replacement semiconductor layer on the source and drain regions of the active layer. As discussed above, acceptable examples of the replacement semiconductor material include germanium, silicon, indium arsenide (InAs), gallium arsenide (GaAs), indium antimonide (InSb), and gallium antimonide (GaSb). Chemical mechanical polishing may be used to planarize the structure and to remove the replacement semiconductor material from the top of the isolation layer, thereby leaving replacement semiconductor material on the source and drain regions. In some embodiments, the replacement semiconductor material completely fills the vias. In such cases, the replacement semiconductor material can be recessed into the vias as needed using a selective etch process, for example.

Method 200 continues with depositing 240 source and drain contacts on the replacement source and replacement drain layers, respectively. In some embodiments, a layer of metal is deposited directly onto the replacement semiconductor material in the vias, followed by planarization to remove excess metal from the top of the isolation layer. In one embodiment, the source and drain contacts 160, 162 may be metal, such as copper interconnect, formed by a damascene process using chemical mechanical planarization (CMP).

Optionally, method 200 continues with reducing the thickness of the active layer in the channel region. In one example, the isolation layer is removed 250 followed by an anisotropic etch or other suitable process to remove 260 a portion of the active layer between the source and drain regions. Such processing results in a semiconductor region (e.g., channel region 146) above and in direct contact with the gate dielectric, where the semiconductor region has a smaller vertical thickness than the source and drain regions. In some embodiments, the gate dielectric functions as an etch stop outside of the TFT and the source and drain contacts function as a mask to protect the material of the replacement source and drain layers. Accordingly, in some embodiments the channel region can then be etched in a self-aligned process when performed after processing the source and drain contacts. In other embodiments, an opening over the channel region can be defined in the isolation layer, followed by a suitable etch process to remove 260 a portion of the active layer material in the channel region.

Method 200 continues with completing 270 an integrated circuit implementing the TFT, such as formation of a memory cell with a TFT and processing to incorporate memory cells in a memory array.

Although method 200 is discussed above as an example series of operations or stages, it is to be understood that there is no required order to the operations or stages unless specifically indicated. For example, in various embodiments, method 200 is described as having a self-aligned process for forming the replacement source and drain layers 152, 154 and a self-aligned process for removing a portion of the channel region 146. Such self-aligned processing is not required even though such a process may facilitate fabrication. Method 200 has numerous variations as will be apparent. Example System

FIG. 11 illustrates a computing system 1000 implemented with the integrated circuit structures or techniques disclosed herein, according to an embodiment of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 (including embedded memory, such as an eDRAM incorporating recessed thin-channel TFTs as described herein) and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, to name a few examples.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM), resistive random-access memory (RRAM), and the like), a graphics processor, a digital signal processor, a crypto (or cryptographic) processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices (e.g., one or more memory cells, one or more memory cell arrays) formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, and the like that may communicate data through the use of modulated electromagnetic radiation through a non solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques, as variously described herein. The term“processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example l is a thin-film transistor comprising: a gate electrode; a dielectric material directly on the gate electrode; a body of a first semiconductor material on the dielectric material, the body having a first body sidewall, a second body sidewall opposite the first body sidewall, and a top body surface between the first and second body sidewalls, the top body surface being spaced from an underlying portion of the dielectric material by a vertical distance Dl; and a source region comprising a second semiconductor material different from the first semiconductor material, the source region having a source region sidewall adjacent to and in direct contact with the first body sidewall, and a top source region surface of the source region vertically spaced from an underlying portion of the dielectric material by a vertical distance D2, wherein D2 is greater than or equal to Dl; a drain region comprising the second semiconductor material, the drain region having a drain region sidewall adjacent to and in direct contact with the second body sidewall, and a top drain region surface of the drain region is vertically spaced from an underlying portion of the dielectric material by a vertical distance D3, wherein D3 is greater than or equal to Dl; a first contact structure on the source region and comprising a first metal; and a second contact structure on the drain region and comprising a second metal.

Example 2 includes the subject matter of Example 1, wherein the source region is directly on an underlying portion of the first semiconductor material that extends from the body in a first direction, and the drain region is directly on an underlying portion of the first semiconductor material that extends from the body in a second direction opposite the first direction.

Example 3 includes the subject matter of Examples 1 or 2, wherein at least one of the source region or the drain region is directly on the dielectric material.

Example 4 includes the subject matter of any of Examples 1-3, wherein a conduction band minimum of the second semiconductor material is from zero to 0.5 eV greater than a conduction band minimum of the first semiconductor material.

Example 5 includes the subject matter of any of Examples 1-3, wherein the conduction band minimum of the second semiconductor material is from zero to 0.2 eV greater than the conduction band minimum of the first semiconductor material.

Example 6 includes the subject matter of any of the Examples above, wherein the first semiconductor material comprises one or more of (i) indium, gallium, zinc, and oxygen, (ii) indium, zinc, and oxygen, (iii) indium, tin, and oxygen, (iv) amorphous silicon (a-Si), (v) zinc and oxygen, (vi) polysilicon, (vii) poly germanium, (viii) low-temperature polycrystalline silicon (LTPS), (ix) amorphous germanium (a-Ge), (x) indium and arsenic, (xi) copper and oxygen, and (xii) tin and oxygen.

Example 7 includes the subject matter of any of the Examples above, wherein the second semiconductor material comprises (i) germanium, (ii) silicon, (iii) indium and arsenic, (iv) gallium and arsenic, (v) indium and antimony, or (vi) gallium and antimony. Example 8 includes the subject matter of any of the foregoing Examples, wherein the first and second metal are the same.

Example 9 includes the subject matter of any of the Examples above, wherein distance D2 is substantially equal to distance D3, in that the difference between distance D2 and distance D3 is less than 1.0 nm.

Example 10 includes the subject matter of any of the Examples above, wherein the body has a vertical thickness from 4 nm to 20 nm as measured perpendicularly to the dielectric material.

Example 11 includes the subject matter of Example 10, wherein the body has a vertical thickness from 4 nm to 10 nm

Example 12 includes the subject matter of any of the Examples above, wherein the body has a vertical thickness no greater than half of that a vertical thickness of the source region or drain region.

Example 13 includes the subject matter of any of the Examples above, wherein the dielectric material comprises a high-k dielectric.

Example 14 includes the subject matter of Example 13, wherein the high-k dielectric comprises hafnium and oxygen.

Example 15 includes the subject matter of any of the Examples above, wherein the dielectric material has a vertical thickness from 2 to 10 nm.

Example 16 includes the subject matter of any of Examples 1 and 4-15, wherein the source region is directly on a first underlying portion of the first semiconductor material that extends from the body in a first direction, and the drain region is directly on a second underlying portion of the first semiconductor material that extends from the body in a second direction opposite the first direction, and a vertical thickness of at least one of the first or second underlying portions of the first semiconductor material is from 2 to 20 nm.

Example 17 includes the subject matter of Example 16, wherein the vertical thickness of at least one of the first or second underlying portions of the first semiconductor material is from 2 to 10 nm.

Example 18 includes the subject matter of any of Examples 1-17, wherein a vertical thickness of at least one of the source region or drain region is from 5 to 20 nm.

Example 19 is a thin-film transistor comprising: a gate electrode; a dielectric material directly on the gate electrode; a first layer of a first semiconductor material on the gate dielectric, the first layer including a source region, a drain region, and a body region between and physically connecting the source region and drain region, the body region having a top surface spaced from an underlying portion of the dielectric material by a vertical distance D 1 ; a second layer of a second semiconductor material, the second layer including a first portion on the source region and a second portion on the drain region; a first contact structure on the second layer over the source region, the first contact structure having a bottom surface spaced from an underlying portion of the dielectric material by a vertical distance D2, wherein D2 is equal to or greater than Dl ; and a second contact structure on the second layer over the drain region, the second contact structure having a bottom surface spaced from an underlying portion of the dielectric material by a vertical distance D3, wherein D3 is equal to or greater than Dl .

Example 20 includes the subject matter of Example 19, wherein the second semiconductor material is compositionally different from the first semiconductor material.

Example 21 includes the subject matter of Example 19 or 20, wherein the body region has a vertical thickness less than a vertical thickness of at least one of the source region or the drain region.

Example 22 includes the subject matter of Examples 19-21, wherein a vertical thickness of the source region or the drain region is from 2 to 20 nm.

Example 23 includes the subject matter of Examples 19-21, wherein the second layer over at least one of the source region or the drain region has a vertical thickness from 5 to 20 nm.

Example 24 includes the subject matter of any of Examples 19-23, wherein the body region has a vertical thickness no greater than half of (i) a combined vertical thickness of the second layer and the source region or (ii) a combined vertical thickness of the second layer and the drain region.

Example 25 includes the subject matter of any of Examples 19-24, wherein a conduction band minimum of the second semiconductor material is from zero to 0.5 eV greater than a conduction band minimum of the first semiconductor material.

Example 26 includes the subject matter of Example 25, wherein the conduction band minimum of the second semiconductor material is from zero to 0.2 eV greater than the conduction band minimum of the first semiconductor material.

Example 27 includes the subject matter of Examples 19-26, wherein the first semiconductor material comprises one or more of (i) indium, gallium, zinc, and oxygen, (ii) indium, zinc, and oxygen, (iii) indium, tin, and oxygen, (iv) amorphous silicon (a-Si), (v) zinc and oxygen, (vi) polysilicon, (vii) poly germanium, (viii) low-temperature polycrystalline silicon (LTPS), (ix) amorphous germanium (a-Ge), (x) indium and arsenic, (xi) copper and oxygen, and (xii) tin and oxygen.

Example 28 includes the subject matter of Examples 19-27, wherein the second semiconductor material comprises (i) germanium, (ii) silicon, (iii) indium and arsenic, (iv) gallium and arsenic, (v) indium and antimony, or (vi) gallium and antimony.

Example 29 includes the subject matter of any of Examples 19-28, wherein the first contact structure comprises a metal, and the second contact structure also comprises the metal. Example 30 includes the subject matter of any of Examples 19-29, wherein the body region has a vertical thickness from 4 nm to 20 nm as measured perpendicularly to the dielectric material.

Example 31 includes the subject matter of Example 30, wherein the body region has a vertical thickness from 4 nm to 10 nm

Example 32 includes the subject matter of any of Examples 19-31, wherein the dielectric material comprises hafnium and oxygen.

Example 33 includes the subject matter of any of Examples 19-31, wherein the dielectric material comprises a high-k dielectric.

Example 34 includes the subject matter of any of Examples 19-33, wherein the dielectric material has a vertical thickness from 2 to 10 nm.

Example 35 includes the subject matter of any of Examples 19-34 further comprising an insulating substrate, wherein the gate electrode is directly on the insulating substrate.

Example 36 is a memory cell comprising: a gate electrode; a dielectric material directly on the gate electrode; a first layer of a first semiconductor material on the dielectric material, the first layer including a source region, a drain region, and a body region positioned between and physically connecting the source region and drain region; a second layer of a second semiconductor material different from the first semiconductor material, the second semiconductor layer including a first portion on the source region and a second portion on the drain region; a wordline electrically connected to the gate electrode; and a capacitor including a first terminal, a second terminal, and a dielectric medium electrically separating the first and second terminals, the first terminal electrically connected to one of the source region or the drain region.

Example 37 includes the subject matter of Example 36, wherein the second layer has a vertical thickness from 5 to 20 nm.

Example 38 includes the subject matter of Example 36 or 37, wherein the semiconductor region has a vertical thickness from 4 to 20 nm.

Example 39 includes the subject matter of any of Examples 36-38, wherein the source region and the drain region have a vertical thickness from 2 to 20 nm.

Example 40 includes the subject matter of any of Examples 36-39, wherein the first semiconductor material comprises one or more of (i) indium, gallium, zinc, and oxygen, (ii) indium, zinc, and oxygen, (iii) indium, tin, and oxygen, (iv) amorphous silicon (a-Si), (v) zinc and oxygen, (vi) polysilicon, (vii) poly germanium, (viii) low-temperature polycrystalline silicon (LTPS), (ix) amorphous germanium (a-Ge), (x) indium and arsenic, (xi) copper and oxygen, and (xii) tin and oxygen. Example 41 includes the subject matter of any of Examples 36-40, wherein the second semiconductor material comprises (i) germanium, (ii) silicon, (iii) indium and arsenic, (iv) gallium and arsenic, (v) indium and antimony, or (vi) gallium and antimony.

Example 42 is a memory array comprising: a plurality of wordlines extending in a first direction;

a plurality of bitlines extending in a second direction crossing the first direction; and a plurality of memory cells at crossing regions of the wordlines and the bitlines, wherein one or more of the plurality of memory cells includes a gate electrode, a dielectric material directly on the gate electrode, a first layer of a first semiconductor material on the gate dielectric, the first layer including a source region, a drain region, and a body region positioned between and physically connecting the source region and drain region, a second layer of a second semiconductor material different from the first semiconductor material, the second layer including a first portion on the source region and a second portion on the drain region; and a capacitor including a first terminal, a second terminal, and a dielectric medium electrically separating the first and second terminals, and one of the first and second terminals is electrically connected to the drain region; wherein one of the plurality of wordlines is electrically connected to the gate electrode and one of the plurality of bitlines is electrically connected to the source region.

Example 43 includes the subject matter of Example 42, wherein the second layer has a vertical thickness from 5 to 20 nm.

Example 44 includes the subject matter of Example 42 or 43, wherein the semiconductor region has a vertical thickness from 4 to 20 nm.

Example 45 includes the subject matter of any of Examples 42-44, wherein the source region and the drain region have a vertical thickness from 2 to 20 nm.

Example 46 is a method of fabricating a thin-film transistor, the method comprising: forming a gate electrode; forming a dielectric material on the gate electrode; forming a first layer of a first semiconductor material, the first layer including a source region, a drain region, and a body region, at least the body region being on the gate dielectric, and the body region physically connecting the source and drain regions; forming an insulating layer on first layer; defining openings in the insulating layer to expose the source region and the drain region; forming a second layer of semiconductor material in the openings and on the source region and the drain region, wherein a top surface of the second layer in the openings is coplanar with or vertically above a top surface of the body region; and forming metal contact structures on the second layer in the openings.

Example 47 includes the subject matter of Example 46 and further comprises planarizing the insulating layer, thereby removing excess material of the second layer from a top surface of the insulator material. Example 48 includes the subject matter of Example 47 and further comprises removing the insulator material and removing a portion of the first layer between the source region and the drain region, thereby reducing a vertical thickness of the body region.

Example 49 includes the subject matter of Example 48, wherein removing the portion of the first layer results in the vertical thickness of the body region being from 4-10 nm.

Example 50 includes the subject matter of Example 48, wherein removing the portion of the first layer comprises reducing a vertical thickness of the body region by at least 25% between the source region and the drain region.

Example 51 includes the subject matter of Example 48, wherein removing the portion of the first layer comprises reducing a vertical thickness of the body region by at least 50% between the source region and the drain region.

Example 52 includes the subject matter of any of Examples 49-51, wherein removing the portion of the first layer comprises recessing an exposed portion of the first layer between the respective metal contact structures on the source region and the drain region.

Example 53 includes the subject matter of any of Examples 49-52, wherein the first semiconductor material comprises one or more of (i) indium, gallium, zinc, and oxygen, (ii) indium, zinc, and oxygen, (iii) indium, tin, and oxygen, (iv) amorphous silicon (a-Si), (v) zinc and oxygen, (vi) polysilicon, (vii) poly germanium, (viii) low-temperature polycrystalline silicon (LTPS), (ix) amorphous germanium (a-Ge), (x) indium and arsenic, (xi) copper and oxygen, and (xii) tin and oxygen.

Example 54 includes the subject matter of any of Examples 49-53, wherein the second semiconductor material comprises (i) germanium, (ii) silicon, (iii) indium and arsenic, (iv) gallium and arsenic, (v) indium and antimony, or (vi) gallium and antimony.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.