FACETING

TECHNICAL FIELD.

[1] This ^: disclosure relates generally to light field displays and cameras, and more particularly tp three- dimensional electronics distribution by geodesic faceting:.

BACKGROUND

[2] Electronic displays are utilized i.r¾. a variety of applications. For example, displays are used in smartpfcoftes, laptop computers, and digital cameras. Some devices, such as smartphones and digital cameras ^' , may include an image sensor in addition to an electronic display- While some cajneraa and electronic displays separately capture and reproduce light fields, light field displays and light field cameras are generally not integrated with one another.

SUMMARY OF PARTICULAR EMBODIMENTS

[3] In one embodiment, a flexible circuit board includes a plurality of facet locations that, each correspond to a particular one of a plurality of rigid sensor facets and a particular one of a plurality of rigid display facets. The flexible circuit board also includes a plurality of wire traces that serially connect the plurality of facet locations. The facet locations are arranged into & plurality of facet columns . When the flexible circuit board .is fiat, at least: some of the facet locations are separated from one or more adjacent facet locations fey a plurality of gaps. When the flexible circuit board is formed into a three-dimensional shape, the plurality of gaps are substantially eliminated, thereby permitting the plurality of rigid sensor facets to form a continuous sensing surface and the plurality of rigid display facets to form a continuous display surface.

[4] The present disclosure presents several technical advantages. Some embodiments provide a complete and accurate recreation pf a target light field while remaining lightweight, and comfortable to wear for a user. Some embodiments provide a thin electronic system which offers both opacity and controllable unidirectional emulated transparency, as well as digital display capabilities such as virtual reality (YE), augmented reality <AR) , and mixed reality (MR)... Some embodiments provide a direct sensox-to-display system that utilizes a direct association of input pixels to corollary output pixels to circumvent the need for image transformation. This reduces the complexity, cost, and power requirements for some systems. Some embodiments provide in.-dayer signal, processing configurations that provide for local, distributed processing of large quantities of data {e.g., 160k of image data or more) , thereby circumventing bottlenecks as well as performance, power, and transmission line issues associated with existing solutions. Some embodiments utilize microlens layers with arrays of plenopfcic ceils to accurately capture and display a volume of light, to a viewer. The plenopti-o ceils include opaque cell walls to eliminate optical crosstalk between cells, thereby improving the accuracy of ^" the replicated light field.

[6] Some embodiments provide three-dimensional electronics by geodesic faceting. In such embodiments, a flexible circuit board with an array of small, rigid surfaces (e.g., display and/or sensor facets} may toe formed into any 3D shape, which is especially useful to accommodate the narrow radii of curvature {e.g., 30-60 mm} necessary for head-mounted near-eye wrapped displays. Some embodiments provide distributed multi-screen arr¾ys for high density displays. In- such embodiments, an array of small, high-resolution micro displays (e.g., display facets) of custom sizes and shapes are formed and then assembled on a larger., flexible circuit bpard that may then be formed into a 3D shape (e.g., a semispherical surface) . Each micro display may act independently of any other display, thereby providing a large array of many high- resolution displays with unique content on each, such that the whole assembly together forms essentially a single extremely high-resolution display. Some embodiments provide a distributed multi-apert'ure camera array. Such embodiments provide an array of small image sensors (e.g., sensor facets) of custom sizes and shapes, all of which are assembled on a larger _/ flexible circuit board that is then formed to a 3D (e.g., semi-spherical) shape. Each discrete image sensor may act independently of any other image sensor in order to provide a large array of many apertures capturing unique content on each, such that the whole assembly essentially becomes a seamless, very high resolution, multi-node camera.

[6] Other technical advantages will be readily apparent to ©tte skilled in the art from FIGURES 1A through 42, their descriptions, and the claims-, Moreover, while specific advantages have been enumerated above, various embodiments may include all, some, or none of the enumerated advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[7 ] For a more complete under standi rig of the present disclosure and its advantages, reference is now made, to the following description, taken in conjunction with the accompanying drawings _/ in wnichi

[ 8 ] FIGURES 1A-1C illustrate a reference scene with various three-dijnensional - (3D) objects end various viewing positions , according to certain embodiments.;

[ 9] FIGURES 2A-2C illustrate viewing the 3D objects of FIGURES 1A-1C through a transparent panel, according to ce rt ain embodiroen t s ?

LlOjj FIGURES 3A- 3C illustrate, viewing the 3D objects of FIGURES iA-lC through a camera image panel, according to ce rtain embodiments ;

[ 113 FIGURES 4A-4C illustrate viewing the 3D objects of FIGURES 1A-1C through an emulated-transparency electronic panel, according to certain embodiments-.;

[ 12. FIGURES 5A-5C illustrate viewing the 3D objects of FIGURES 1A-1C through the camera image panel of FIGURES 3A-3C .from an alternate angle, according to certain embodiments;

[ 133 FIGURES 6A-6C illustrate viewing the 3D objects of FIGURES 1A-1C through the emulated^traxvsparency electronic panel of FIGURES 4.A- 4C from an alternate angle, according to certain embodiments ;

[ 143 FIGURE 7 illustrates a cut-away view of an emulated transparency assembly, according to certain embodiments;

[ 153 FIGURE S illustrates an exploded view of the emulated transparency assembly of FIGURE 7 , according to- ce r t.a in embodiment s ; [16] FIGURE 9 illustrates a method of manufacturing the emulated transparency assembly of FIGURE 7, according to certain embodiments/

[17] FIG-ORE 10 illustrates a direct sensor-to-display system that may be used by the -emulated transparency assembly of FIGURE ?, according to certain embodiments;

£183 FIGURE 11 illustrates a method of manufacturing the direct sensor-to-dispiay system of E'IGURE 10, according to certain embodiments ;

[19] FIGURES J2-13 illustrate various in-layer signal processing configurations that may be used foy the emulated transparency assembly of FIGURE 7, according to certain embodiments;

[20] FIGURE 14. illustrates a method of manufacturing the in-layer signal processing systems of FIGURES 12-13, according to certain embodiments;

[21] FIGURE 15 illustrates a plenoptic cell assembly that may be used by the emulated transparency assembly of FIGURE 7, according to certain embodiments;

[22] FIGURE 16 illustrates a cross septi&ft of a portion of the plenoptic cell assembly of FIGURE 15, according to certain .embodiments ;

[23] FIGURES 17A-17C illustrate cross sections of a portion of the plenoptic cell assembly of FIGURE 15 with various incoming fields of light, according to certain embodiments;

[24|: FIGURES X8A-18E illustrate a method of manufacturing the plenoptic ceil assembly of FIGURE 15, according to certain embodiments; [25] FIGURES Ϊ9&-Ί9Β illustrate another method of manufacturing the plenoptl-e cell assembly of FIGURE- IS, according to certain embodiments;

[26] FIG0RES 2-0-21 illustrate a pleaoptlc ceil assembly that may be manufactured by- the methods of FIGURES 18&-19B, according to certain embodiments;

[27 ] FIGURE 22 illustrates a flexible circuit board that may be used by the emulated transparency assembly of FIGURE 7, according to certain embodiments ;

12%] FIGURE 23 illustrates additional details of the flexible circuit board of FIGURE 22, according to certain embodiments;

[ 293 FIGURE 24 illustrates a data flow through the flexible circuit board of FIGURE 22, according to certain embodiments;

[30] FIGURE 2& illustrates a method of manufacturing an electronic assembly using the flexible circuit board of FIGURE 22, according to certain embodiments;

[31] FIGURE 26 illustrates a cut-away view of a curved multi-display array, according to certain embodiments;

[32] FIGURE 27 illustrates an exploded view of the curved multi-display array of FIGURE 26, according to. certain embodiments;

[33] FIGURES 28-29 illustrate logic facets and display facets of the curved multi-display array of FIGURE 26, according to certain embodiments;

[34] FIGURE 30 illustrates a back side of the flexible circuit board of FI-GEJPE 22, according to certain embodiments;

[35] FIGURE 31 illustrates a data flow through the flexible circuit board of FIGURE 30, according to certain eiribcdiineri t s ; [36] FIGURE 32 illustrates the flexible circuit board of FIGURE 30 that has been formed -into a serai spherical shape, according to certain eaibodixwents /

[37] FIGURE 33 illustrates a data flow through the flexible circuit board of FIGURE 32, according to certain embodiments i

[38] FIGURE 34 illustrates an array of logic facets that have been formed into a sendspherical shape, according to certain embodiments;

[39] FIGURE 35 illustrates communications between the logic facets of FIGURE 34, according to certain embodiments;

[40] FIGURE 36 illustrates a method of manufacturing the curved multi-display array of FIGURE 2% _f according to certain embodiments;

[41] FIGURE 37 illustrates a cut-away view of a curved multi-camera array, according to certain embodiments;

[42] FIGURES 38-39 illustrate exploded views of the curved multi-camera array of FIGURE 37, according to certain emhodiments t

[43] FIGURE 40 illustrates a back *ie¾? of the flexible circuit board of FIGURE 32, according to certain embodiments,'

[44] FIGURE 41 illustrates a data flow through the flexible circuit board of FIGURE 40, according to certain embodiments; and

[43] FIGURE 42 illustrates a method of manufacturing the curved multi-camera array of FIGURE 37, according to certain embodiments. DETAILED DESCRIPTION GF EX&MPLE EMBODIMENTS

[46] Electronic displays are utilized in a variety of appiicat ions . For example, displays are used in smartphones, laptop computers, and digital catmraa . Some devices, such as sinartphones and digital cameras, may include an image sensor in addition to an electronic display. Devices with displays and image sensors, however, axe generally .li.Ta.ited in their ability to accurately capture and display the full photonic environment .

[46] TO address problems and limitations associated with existing electronic displays, embodiments of the disclosure provide various electronic assemblies fo;r capturing and displaying light fields, FIGURES lA-3 are directed to display aseembXiee with electronically emulated transparency, FIGURES' 10-11 are directed to direct camera-to-display systems, FIGURES 12-14 are directed to in-layer signal processing, FIGURES 1:5-21 are directed to pienoptic cellular imaging systems, FIGUBK5 22-25 are directed to three- dimensional (3D) electronics distribution by geodesic faceting, FIGURES 26- _^ 36 are directed to distributed multiscreen arrays for high density displays, and FIGURES 37-42 are directed to distributed multi'-aperture camera arrays .

(480 To facilitate, a better understanding of the present disclosure, the following examples of certain embodiments are given. The following examples are not to be read to limit or define the scope of the disclosure. Embodiments of the present disclosure and its advantages are best understood, by referring to FIGURES 1&-42, where like numbers are used to indicate like and corresponding parts.

[49] FIGURES 1A-9 illustrate various aspects of an assembly with electronically emulated transparency, according to certain embodiments .· In general, the electronic assembly illustrated in detail in FIGURES 7-3 may be used in different applications to provide features such as virtual reality (VR) , augmented reality (APJ , and mixed reality -(MB) , For VR applications, a digital · display is required which can completely replace a view of the real world, similar to how a standard computer monitor blocks the view of the scene behind it. However, for AR applications, a digital display is required which pan overlay data on top of that view of the real world, such as a pilot's heads-up display in a modern cockpit. MR applications require a combination of both. Typical systems used to provide some or all of these features are not desirable for a number of reasons. For example, typical solutions do not provide an accurate or complete recreation of a target light field. Άβ another example, existing solutions are typically bulky and not comfortable for users .

[50] To address problems and limitations with existing electronic displays, embodiments of the disclosure provide a thin electronic: system which offers both opacity and controllable unidirectional emulated transparency, as well as digital display capabilities. From one side the surface appears opaque, but from the opposite side the surface can appear fully transparent, appear fxiily opaque, act as a digital display, or any combination of these. In some embodiments, simultaneous plenoptie sensing and display technologies are combined within a single layered structure to form what appears to be a unidirectional visually transparent surface, The system may include multiple layers of electronics and optics for the purpose of artificially recreating transparency that may foe augmented and/or digitally controlled- Individual image sensor pixels on one side may be arranged spatially to match the positions of display pixels on the opposite side of the assembly, ϊη aome. e^Qdii&ent*, all electronic driving circuitry as well as some display logic circuitry may foe sandwiched between the sensor layer and display layer, and each sensor pixel's output signal x¾ay be channeled through the circuitry to the corresponding display pixel on the opposite side. In some embodiments _/ this centrally-processed signal is aggregated with the incoming signal from the plenoptic itaaging sensor array on the opposite side, and is handled according to the following modea of operation. In VR mode, the external video feed overrides the camera data, completely replacing the user's view of the outride world with the incoming view from the video. In AR mode* the external video feed is overlaid on the camera data, resulting in a combined view of both the external world and the view from the video £e.g., the video data is simply added to the scene _? . In MR mode, the external video feed is mixed with the camera data, allowing virtual objects to appear to interact with actual objects in the real world, altering the virtual content to make it appear integrated with the actual environment through object occlusion, lighting, etc.

(Si] Some embodiments combine stacked transparent high dynamic range (HDR) sensor and display pixels into a single structure* with sensor pixels on one side of the asseiably and display pixels on the other, and with, pixel- for-pixel alignment between camera and display. Both the sensor and display pixel arrays may be focused by groups of micro lenses to capture and display four-dimensional light fields . This means that the complete view of the real world is captured on one side of the assembly and electronically reproduced on the other, allowing for partial or complete alteration of the incoming imags while maintaining intake clarity, luminance, and enough angular resolution for the display side to appear transparent, even when viewed at oblique angles.

[52] FIGURES 1ft-6C are provided to illustrate the differences between electronically emulated transparency provided by embodiments of the disclosure and typical camera images (such as through a camera viewfindex or using a smartphone to display its parrent camera image) .· FIGURES 1A-1C illustrate a reference scene with various 3D objects 110 {i.e., llOA-C) and a frontal viewing position, according to certain embodiments. FIGURE 1A is a top vie*? of an arrangement of 3D objects 11G and a frontal viewing direction of 30 objects 110. FIGURE IS is a perspective view of the same arrangement of 3D objects 13.0 and frontal viewing direction as FIGURE 1Λ. FIGURE 1C is the resulting front view Of 3D objects 110 from the position illustrated in FIGURES lA and IB, As can be seen, the view in FIGURE 1C of 3 ^' D objects 110 is a normal, expected view of 30 objects 110 {i.e., the view of 3D objects 110 is not altered at all because there is nothing between the viewer and 3D objects 110).

[53] FIGURES 2A-2C illustrate viewing the 3D objects 110 of FIGURES 1A-1C through a transparent panel 210:, according to cettain embodiments. Transparent panel 210 may be, for example, a piece of. transparent .glass. FIGURE 2A L» a top -view of a frontal viewing direction of 3D objects 110 through transparent: panel 210, and FIGURE 23 is a perspective view of the same arrangement of 3D objects 110 and frontal viewing direction as FIGURE 2A. FIGURE 2C is the resulting front view of 3D objects 1.10 through transparent panel 210 from the position illustrated in FIGURES 2A and 2B, As can foe seen, the view in FIGURE 20 of 3D objects 1.10 through transparent panel 210 is a normal, expected view of 3D objects 110 {i.e. _/ the view- of 3D objects 110 is not altered at all because the viewer is looking through a transparent panel 210} , In other words, the view of 30 objects 110 through transparent panel 210 in FIGURE 2C is the same as the view in FIGURE iC where no object is between the viewer and 3D objects 110 (i.e., ^perceived" transparency). Stated another way, the edges of the projected imagery on transparent panel 21-0 line up with the view of the actual 3D objects 110 behind transparent panel 210 to create a view-aligned image 2?OA of 3D object 110A, a view-aligned image 220b of 3.0 object 110», and a viewaligned image 220C of 3D object HOC.

[54] FIGURES 3A-3C illustrate viewing the 3D objects 110 of FIGURES 1A-1C through a camera image panel 310, according to certain embodiments . Camera image panel 310 may be, for example, a camera viewfinder or a display of a smartphone that is displaying its current camera image. In these images, camera image panel 310 is at an angle (e.g., 30 degrees) to the viewer to illustrate how s¾ch systems do not provide true emulated transparency. FIGURE 3ft is a top view of a frontal viewing direction of 3D objects 110 through camera image panel 310, and FIGURE 3B is a perspective view Of the same arrangement of 3D objects 110 and frontal viewing direction as FIGURE 3A. FIGURE 3β is the resulting front view of 3D objects 110 through camera image panel 310 from the position illustrated in FIGURES 3A and 3B, As can be seen, the view in FIGURE 3C o£ 3D objects 110 through camera image panel 310 is different from a view of 3D objects 110 through transparent panel 210. Here, camera image panel 310 redirects the lines of sight that are normal to camera image panel 310, thereby showing no perceived transparency {i.e., the image on camera image panel 310 is not aligned with the view but insbead depicts the image acquired by the redirected lines of sight) . Stated another way, the edges cf the projected imagery on camera image panel 310 do not line up with the view of the actual 3D objects IIQ behind camera image panel 310, This is illustrated by an unaligned image 320A of 3D object i ^' lGA and an unaligned image 3.2OB of 3D object HOB on camera linage panel 310 in FIGURE 3C.

[55] FIGURES 4A-4C illustrate viewing the 3D objects 110 cf FIGURES 1A-1C through an emulated-transparency electronic panel Alp _t according to asrtain embodiments·« in these images, emulated transparency panel 410 is at an angle (e.g., 30 degrees) to the viewer to illustrate how emulated transparency panel 410 provides true emulated transparency unlike camera image panels 310. FIGURE 4A is a top view of a frontal viewing direction of 3D objects 110 through emulated transparency panel 410, and FXGURS 4B is- a perspective view of the same arrangement of 30 objects 11.0 and frontal viewing direction as FIGURE 4A, FIGURE 4C is th¾ resulting front view of 3D objects 110 through emulated transparency panel 410 from the position illustrated in -FIGURES 4A and 4&. As can be seen, the view in FIGURE 4C of 3D objects 110 through emulated transparency panel 410 is different from a view of 3D objects 11G through camera image panel 310 but is similar to a view of 3D objects 110 through transparent, panel 210. Here, emulated transparency panel 410 does not redirect the lines of ^" sight from the viewer through emulated transparency panel. 410, but allows them to remain virtually unchanged and thereby providing emulated transparency (i.e., the image on emulated transparency panel. 410 is aligned with the view as in transparent panel 210) . hike transparent panel 210„ the edges of the projected imagery on emulated transparency panel 410 lines up with the view of the actual 3D objects US behind emulated transparency panel 410 to create view-aligned image 22OA of 31) object 11QA, view-aligned image 22ΩΒ of 3D object HOB, and view-aligned image 220C of 3D object HOC.

[56] FIGURES 5A-5C illustrate viewing the 3D objects 110 of FIGURES 1A-1C through the camera image panel 310 of FIGURES 3A-3C, but from an alternate angle. In these images, camera image panel 31.0 is at a different 30 degree angle to the viewer to further illustrate how* such systems do not provide true emulated transparency.. Like in FIGURES 3A-3C, the edges of the projected imagery on camera image panel 310 do not line up with the view of the actual 3D objects 110 behind camera image panel 310- This is illustrated by an unaligned image 320C of 3D object 110C and an unaligned image 320S of 3D object HOB on camera image panel 310 in FIGURE SC.

[57] FIGURES 6A-6C illustrate viewing the 3D objects 110 of FIGURES lA-IC through the eraulated-transparency electronic panel 410 of FIGURES 4A-4C, but. from an alternate angle. Like in FIGURES 4A-4C, the edges of the -projected imagery on emulated transparency panel 410 in FIGURE fiQ line up with the view of the actual 30 objects 110 behind emulated transparency panel 410 to create view-aligned image 22OB of 3D object 110B and view-aligned linage 220C of 3D object HOC.

[58] As illustrated above in FIGURES 4A-4C ^" and 6A-6C, emulated transparency panel 410 provides view-aligned images 220 of 3D objects 110 behind emulated transparency panel 410» thereby providing eleotronically-eniulated transparency. FIGURES 7-8 illustrate an example embodiment of emulated transparency panel 410 ^: . FIGURE 7 illustrates a cut-away view of an emulated transparency assembly 710 which may be emulated transparency panel 41.0, and FtGjLJRE S illustrates an exploded view of the: emulated transparency asserribly 710 of FIGURE 7, according to certain embodiments .

[59] In some embodiments, emulated transparency assembly 710 includes two microiens arrays 72X? (i.e., a sensor side microiens array 720A and a display side microiens array 720B)\, an image sensor layer 730 _r a circuit board 740, and an electronic display layer 760. In general, incoming light field 701 enters sensor side microiens array 720A where it is detected fey image sensor layer 730. Electronically-replicated outgoing light field 702 is then generated by electronic display layer 760 and projected through display side microiens array 7203. As explained in more detail below, the unique arrangement and features of emulated transparency assembly 710 permits it to provide electronica11y-«mulated transparency via electronically-replicated outgoing light field 702, as well as other features described below. While, a specific shape of emulated transparency assembly 710 is illustrated in FIGURES 7-8, emulated transparency assembly 710 may have any appropriate shape including any polygonal or non-polygonal shape, and both fiat and non-flat configurations-

[60] Microiens arrays 720 (i.e., sensor side microiens array 72OA and display side microiens array 7.2OB) are generally layers of microlenses . In some embodiments, each microiens of microiens arrays 720 is a plerioptic cell 1510 as described in more detail below in reference to FIGURE 15. In general, each microiens of sensor, side microiens array 72PA is configured to capture a portion of incoming light field 701 and direct it to pixels within image sensor layer 730. Similarly, each microiens of display side jfticrolens array 72 ps is configured to emit a portion of al¾ctronically*-repiieated outgoing light field 702 that is generated by pixels of electronic display layer 760. In some embodiments, each microlens of sensor side microlens array 72OA and display side mioroiens array 7283 is in a 3D shape with a coll3-mating lens on one end of the 3D shape. The 3D shape may be, for example, a triangular polyhedron, a rectangular cuooid, a pentagonal polyhedron, a hexagonal polyhedron, a heptagonal polyhedron, or aft octagonal polyhedron. In some embodiments _/ each microlens pf sensor side microlens array 72OA and display side microlens array 720B includes opaque wails such as ceil wails 1514 (discussed belov? in reference to FIGURE 1.5) that areconfigured to prevent light from bleeding into adjacent microlensss _* In some e»toodii»en.te> each microlens of sensor side micro-lens array 720A and display side microlens array 720B additionally or alternatively includes s light incidence angle rejection coating such as filter layer 1$Αύ described below to prevent light from bleeding into adjacent iriicrolenses.

[61] In some embodiments, the microienses of sensor side microlens array 72OA are oriented towards a first direction, and the microlersses of display side microlens array 720B are oriented towards a second direction that is 180 degrees from the first direction. In other words, some embodiments of emulated transparency assembly 710 include a sensor side microlens array 720A that is oriented exactly opposite from display side microlens array 720B. In other embodiments, any other orientation of sensor side microlens array 720 A and display side microlens array 72C3 is possible.

[62] In -general, image sensor layer 730 includes a plurality of sensor pixels that are configured to detect. incoming light field 701 after it passes through sensor side microlens array 72OA. In some embodiments, image sensor layer 73& includes, an array of sensor units 735 {e.g., sensor units 735A-C as illustrated in FIGURE 8) . Each sensor unit 735 may be a defined portion of linage sensor layer 730 (e.g., a specific area such as a portion of a rectangular grid) or a specific number or pattern of sensor pixels- within image sensor layer 730. In svtm embodiments, each sensor unit 735 corresponds to a specific ^" logic wnit 755 of logic unit layer 750 as described below. In some embodiments, image sensor layer 73Q is coupled to or otherwise immediately adjacent to sensor side microl-ene array 720ft. In some exnbodiiiients, image sensor layer 730 is between sensor side xciicr0lens array 720ft and circuit board 740. In other embodiments, image sensor layer 730 is between sensor side roicrolens array 72ΌΑ and logic unit layer 750. In some embodiments, other appropriate layers may be included in emulated transparency assembly 710 on either side of image sensor layer 730. Furthermore, while a specific number and pattern of sensor units 735 are illustrated, any appropriate number (including only one) and pattern of sensor units 735 may be used.

[63] Circuit board 740 is any appropriate rigid or flexible circuit board. In general, circuit board 740 includes various pads and traces that provide electrical connections between various layers of emulated transparency assembly 710. As one example, in embodtxeents that include circuit board 740, circuit board 740 may be located between image sensor layer 730 and logic unit layer 750 as illustrated in FIGURES 7-8 in order to provide electrical connections between image sensor layer 730 and logic unit layer 756. in otner embodiments, circuit board 740 may be located between logic unit layer 750· and electronic? display layer 760 in order to provide electrical connections- between l0gic unit layer 750 and electronic display layer 760. In sprue embodiments, circuit board 740 includes an array of unit attachment locations 745 le..g, _r unit attachment locations 745-ft-C as illustrated in FIGURE 8} . Each unit attachment location 745 may toe a defined portion of circuit board 740 (e.g., a specific area such as a portion of a rectangular grid) and may include a plurality of pads (e.g., ball grid array (BGA) pad) and/or vias _r In some embodiments, each unit attachment location 745 corresponds to a specific sensor unit 735 of image sensor layer 730 and a specific display unit 765 of electronic display layer 760 ie.g. , unit attachment location 74 _: 5A corresponds to Sensor unit 735A and display unit 765Λ) and is configured to -permit electrical communication between the corresponding: specific sensor unit 735 and the specific display unit 765.

[643 Logic unit layer 750 provides optional/additional logic and/gr processing for emulated transparency assembly 710. in general, logic unit layer 750 emulates transparency by directing signals from the plurality of sensor pixels of image sensor layer 730 to the plurality of display pixels of electronic display layer 760, thereby emitting electronically- replicated outgoing light field 702 from display side microlens array 7208 at angles that correspond to angles pf the incoming light field 701 detected through sensor side microlens array 7^0». By emitting electronically-replicated outgoing light field 702 from display side microlens array 7203 at angles that correspond to angles of the incoming light field 701 detected through senepr side microlens array 72QA, an image is displayed, that matches what would be seen if emulated transparency assembly 710 ¾as not present (i.e., emulated transparency) . In. some embodiments, logic unit layer 750 includes an array of logic units 755 (e.g. _/ logic units 755A-C as illustrated in FIGURE 8) . Each logic units 755 may be a defined portion of logic unit layer 750 {e.g., a specific area such as a portion of a rectangular grid) . In some embodiments _/ each logic unit 755 is a separate physical, rigid, unit that is later joined to or coupled to other logic units 755 in order to form logic unit layer 750. in some embodiments _/ each logic unit 755 corresponds to a specific sensor unit 735 of image sensor layer 730 and a specific display unit 765 of electronic display layer 760 Je.g.y logic unit 755A corresponds to (and: is electrically coupled to) sensor unit 735i¾ and display unit 765A) . In some embodiments, logic unit layer 750 is located between circuit board 740 and electronic display layer 760. In other embodiments, logic; unit layer 750 is between image sensor layer 730 and circuit board 740. In some embodiments, other appropriate layers may be included in emulated transparency assembly 710 on either side of logic unit layer 750. .Furthermore, while a specific number and pattern o;f logic units 755 is illustrated, any appropriate number (including none or only one) and pattern of logic units 755 may be used,

[65] In general, electronic display layer 760 includes a plurality of display pixels that are configured to generate and project electronically-replicated outgoing light field 702 through display side 5n.icrol.en3 array 7.20JB « In some embodiments, electronic display layer 760 includes an array of display units 765 (e.g., display units 7S5A-C as illustrated in FIGURE H) . Each display unit 76$ may be a defined portion of electronic display layer 760 (e.g., a specific area such as a portion of a rectangular grid} or a specific number or pattern of display pixels witftise electronic display layer 76©. in &em embodiments, each display unit 765 corresponds to a specific- logic unit 755 of logic unit layer 750. In some erobcdiroents, electronic display layer 760 is coupled to or otherwise iroroediafce ^' ly adjacent to display side microlens: array 720S. In isone embodiments, electronic display layer 760 is between display side microleas array 7.2OB and circuit board 740. In other exobodiraents, electronic display layer 760 is between display side microlens array 7203 and logic unit layer 750. In some embodiment*, other appropriate layers may be included in emulated transparency assembly 710 on either side of electronic display layer 760- Furthermore, while a specific number and pattern of display units 765 > <are illustrated, any appropriate number (including only one; and pattern of display units 765 may be used,

t66] In some embodiments, the sensor pixels of image sensor layer 730 may be sensor pixels 1800 as described in FIGURES 18-20 and their associated descriptions in U.S< Patent Application Mo. 15/724,027 entitled "Stacked Transparent Pixel Structures for Image Sensors," which is incorporated herein by reference in its entirety. In some embodiments, the display pixels of electronic display layer 760 are display pixels 100 as described in FIGURES 1-4 and their associated descriptions in U.S. Patent Application ;So. 15/724,004 entitled ^Stacked Transparent Pixel Structares for Electronic Displays," which is incorporated herein by reference in its entirety.

[67] While FIGURES 7-S depict emulated transparency assembly 710 as having arrays of sensors, displays, and electronics, other embodiments aiay have single-unit setups;. Furthermore, while the illustrated embodiments of emulated transparency assembly 710 depict, unidirectional emulated transparency (i.e. allowing the capture of incoming light field 701 from a single direction and displaying a corresponding electronicallyreplicated outgoing light field 702 in the opposite direction), other embodiments may include arrangements and combinations o£ emulated transparency assembly 710 that permit bidirectional transparency.

[68] FIGURE 9 illustrates a method 900 of manufacturing the emulated transparency assembly 710 of FIGURE 7, according to certain embodiments. Method 900 may begin in step 910 sphere a plurality of unit attachment locations are formed on a circuit board. In some embodiments, the circuit board is circuit board 740 and the unit attachment locations are unit attachment locations 145. In some embodiments, each unit attachment location corresponds to one of a plurality of display units such as display units 765 arid one of a plurality of sensor units such as sensor units 735.

[69] &t step $20, a plurality of sensor units are coupled to a first side of the circuit board- In some embodiments, the sensor units are sensor units 735. In some embodiments, each sensor unit is coupled in step 920 to a respective one of the unit attachment locations of step 910. In some embodiments, the sensor units are first formed into an image sensor layer such as image sensor layer 730, and the image sensor layer is coupled to the first side of the circuit board in this step.

[70] At step 930, a plurality of display units are coupled to a second side of the circuit board that is opposite the first side. In some embodiments, the display units are display units 765. In some embodiments^ each display unit is coupled to a respective one of the unit attachment locations. In some embodiments, the display units are first formed into a display layer such as electronic display layer 760, and the display layer is coupled to the second side of the circuit board in this step.

[71] At step 940, a fixst plurality of micrpienses are coupled to the plurality of seasor units of strep 920. In some embodiments, the microlenses are plenoptic cells 1510. In some embodiments, the microlenses are first formed into an miczoiens array layer such as sensor side microlens array 720ft, and the microlens array layer is coupled to the sensor units.

[72] At step $50, a second plurality of microienses are coupled to the plurality of display wits of step 930, In some: embodiments, the mierolenses are plsnoptic ceils 1510, In some embodiments:, the mierolenses are first formed into an microlens array layer such as display side microlens array 720B, and the microlens array layer is coupled to the display units. After step 950, method 900 may end.

[73] In some embodiments; method 900 may additionally include coupling a plurality of logic units between the circuit board of step 910 and the plurality of display units of step 930. In some embodiments, the logic units are logic units 755. In some embodiments , the plurality of logic units are coupled between the circuit board and the plurality of sensor units of step 920.

:[74] Particular embodiments may repeat one or .more steps of method. 900., where appropriate. Although this disclosure describes and illustrates particular steps of method 900 as occurring in a particular order, this disclosure contemplates any suitable steps of method 900 occurring in any suitable order {e.g., any temporal order). Moreover, although this disclosure describes and illustrates an example emulated transparency assembly manufacturing method including the particular steps of method MO, this disclosure contemplates any suitable emulated transparency assembly manufacturing method including any suitable steps, which may include all> some, or none of the steps of seethed 900, where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of method ¾>0G, this disclosure contemplates any suitable combination of any suitable components, devices, or systems carrying out any suitable steps of method 300,

[75] FIGURE 10 illustrates a direct sensor-to-display system 1000 that may be implemented by the emulated transparency assembly of FIGURE 7, according to certain embodiments. In general, FIGURE; 10 illustrates how embodiments of emulated transparency assembly 710 utilize a direct association of input pixels to corollary output pixels. In some embodiments, this is accomplished by using a layered approach such that the. image sensor layer ?3D arsd electronic display layer 760 are in close proximity to one another, mounted on opposite sides of a shared substrate (e.g., circuit board 7401 as illustrated in FIGURES 7-8. Signals from image sensor layer 730 may be propagated directly to electronic display layer 760 through circuit board 740 (and logic unit layer 75Q in. some embodiments) . Logic unit layer 750 provides simple processing with optional input for any necessary control or augmentation . Typical electronic sensor/display pairs Je.g. , a digital camera) do not express a one-to-one relationship in that £he display is not coupled directly with the input sensor and thus requires some degree of image transformation. Certain embodiments of the disclosure, however, implement a one-to-one mapping between input and output pixels (i.e., the sensor pixel and display pixel layouts are identical) , thereby circumventing the need fpr any image tranaformation..- This reduces the complexity and power requirements of emulated transparency assembly HO.

[76] As illustrated in FIGURE 10, each sensor unit 735 is directly coupled to a corresponding display unit 7£5 _¾ For example, sensor unit 735A may be directly coupled to display unit 765A, sensor unit 735B may be directly coupled to display unit 765B, .and so on. In some emtoodiments, the signaling between sensor units 735 and display units 765 may be any appropriate differential signaling such as low-voltage differential signaling (LVDS) . More specifically, each sensor unit 735 may output first signals in a specific format {e.g., LVDS} that corresponds to incoming light field 701. In some embodiments, the first signals are sent via a corresponding logic unit 755, which in turn sends second signals to display unit 765 in the same format as the first .signals (e.g., LVDS) . In other embodiments, the first signals are sent, directly to display units 765 from sensor units 735 te.g., sensor units 735 and display ux.its 765 are coupled directly to opposite sides of circuit board 740), Display unit 765 receives the second signals from the logic unit 755 {or the first signals directly from the sensor unit 735 via .circuit board 740) and uses them to generate outgoing light field 702.

[77] Bfscause no conversion is needed in the signaling between sensor units 735 and display units 7£5, emulated transparency assembly 710 may provide many benefits from typical display/sensor combinations. First, no signal processors are needed to convert the signals from sensor units 735 to (display units 765. For example-, no off-board signal processors are needed to perform .image transformation between sensor units 735 and display units 765. This reduces the space, complexity, weight, and cost requirements for emulated transparency asseif-biy 710, Second, emulated transparency assembly 710 may provide greater resolutions than would typically be possible for display/sensor combinations. -By directly coupling sensor units 735 with, display units 765 and not requiring any processing or transformation of data between the units, the resolution of sensor units 735 and display units 765 may be far greater than would typically be -possible _* Furthermore, emulated transparency assembly 71.0 my provide heterogeneous resolutions across sensor units 735 and display units 765 at any particular time. That is, a particular senspr unit 735 and corresponding display unit 76:5 may have a particular resolution that is different from other sensor units 735 and display units 765 at a particular time, and the resolutions of each sensor unit 735 and display unit 765 may be changed at any time.

[78] In some embodiments, each particular sensor pixel of a sensor unit 735 is mapped to a single display pixel of a corresponding display unit 765, and the display pixel displays light corresponding to light captured by its mapped sensor pixel. This is illustrated best in FIGURES 17A.-17B. As one example, each center sensing pixel 1725 of a particular plenoptic ceil 1510 of sensor side micro-lens array 720A ie-g., the bottom plenoptic cell 1510 of sensor side microlens array

[79] in FIGP.RS 17A.) is mapped to a center display pixel 1735 of a corresponding plenoptic cell 1510 of display side inicrolena array 72GB {e.g., the bottom plenoptic cell 1510 of display side itdcrolens array 720B- in FIGURE 17A) . As another example, each top sensing pixel 1725 of a particular plenoptic cell 1510 of sensor aide mierolens array 720& (e.g., the top plenoptic ceil 1510 of sensor .side mierolens array 72OA. in FIGURE 17B) i& mapped to a bottoifi display pixel 1715 of a cox-responding plenoptic cell 15X0 of display side mierolens: array 720B (e.g., the top plenoptic cell 15IQ of display side mierolens array 720B in FIJSUBB 17B) <

[79] In some embodiments, sensor units 735 are coupled directly to circuit board 740 while display units 765 are coupled to logic units 755 (which are in turn coupled to circuit board 740} as illustrated in FIGURE 8. In other embodiments, display units 765 are coupled directly to circuit board 740 while sensor units 735 are coupled to logic units 755 (which are in turn coupled to circuit board 740) - In other embodiments, both sensor units 735 and display units 765 are coupled directly to circuit board 740 |i.e _* , without any intervening; logic units 755) . In such embodiments, sensor Units? 735 and display units 765 are coupled to opposite sides of circuit board 740 at unit attachment locations 745 (e.g,, sensor unit 7 ^' 25A and display unit: 765¾ are coupled to opposite sides of circuit board 740 at unit attachment location 745A) ,

[80] FIGURE II illustrates a method HOG of manufacturing the direct sensor-to-display system 1000 of jflSURE .10, according to certain embodiments . Method 1100 may begin at step 1110 where a plurality of unit attachment locations are formed on a circuit board. In some embodiments, the circuit board is circuit board 740 and the unit attachment locations are unit attachment locations 74.5. In some embodiments, each unit attachment location corresponds to one of a plurality of display units and one of a plurality of sensor units. The display units may be display units 765 and the sensor units may toe sensor unite 735. In some embodiments, each particular unit attachment location includes BGA pads that are configured to couple to one of the plurality of sensor units and/or one of the plurality of logic units. In some embodiments,- each particular unit attachment location includes a plurality of interconnection pads configured to electrically couple the particular unit attachment location to one or more adjacent unit attachment locations. In seme embodiments, the unit attachment locations are arranged into a plurality of columns and plurality of rpwg as illustrated in FIGURE 8.

iBl] At step 112.0, a plurality of sensor units are coupled to a first side of the circuit board. In some embodiments, each sensor unit is coupled to a respective one of the unit attachment locations of step 113.0. At step 11:30, & plurality of display units are coupled to a sesond side of the circuit board that is opposite to the first side.. In some embodiments, each display unit is coupled to a respective one of the unit attachment locations of step 1110 such that each particular one of the plurality of sensor pixel units is mapped to a corresponding one of the plurality of display pixel units. By mapping each particular sensor pixel unit to one of the display pixel units, the display pixels of each particular one of the plurality of display pixel units are configured to display light corresponding to light captured toy sensor pixels of its mapped sensor pixel unit . After step 1130, method lie0 may end.

[82] Particular embodiments may repeat one or more steps of method 1100, where appropriate. Although this disclosure describes and illustrates particular steps of method 1100 as occurring in a particular order, this disclosure contemplates any suitable steps of method 1100 occurring in any suitable order (e.g., any temporal order). Moreover, although this disclosure describes and illustrates an example direct sensox-to-display system manufacturing method: including the particular steps of method IIGO, this disclosure contemplates any suitable direct sensor-to-display system manufacturing method including any suitable steps, which may include ail, some, or none of the steps of jrtethdd iXQ$ _: , : where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of laethe-d 1100, this disclosure contemplates any suitable combination of any suitable components, devices, or systems carrying out any suitable steps of method HOC

[83] FI-GGTU5S 12-13 illustrate various in-layer signal pi:ocessing configurations that may be used by emulated transparency assembly 710 of FIGURE 7, according to certain embodiments. In general, the configurations of FIGURES 12-13 utilize a layer of ^" digital logic (e.g., logic unit layer 7.50) that is sandwiched between the camera and display (i.e., between image sensor layer 12® and electronic display layer 7€0) v These configurations allow for local, distributed processing of large quantities of data (e.g., 160k of image data or more), thereby circumventing bottlenecks as well as performance., power, and transmission line issues associated with typical configurations. Human visual acuity represents a tremendous amount of data which must be processed in realtime, typical imaging systems propagate a single data stream to/from a high-powered processor {e.g., a CPU or GPU), which may or may not serialize the data for manipulation. The bandwidth required for this approach at human -20/20 visual acuity far exceeds that of any known transmission protocols. Typical systems also use a master centroller which is responsible for either processing all incoming/outgoing data or managing distribution to smaller processing nodes. Regardless, all data must be transported off-system/off-chip, manipulated., and then returned to the display device (s)· . However, this typical approach is unable to handle the enormous amount of data required by human visual acuity. Erofcodiwenti* of the disclosure, however, harness the faceted nature of a sensor/display combination as described herein to decentralize <a.nd localise signal processing. This enables previously unachievable real-time digital image processing.

[84] As illustrated in FIGURES 12-13, certain embodiments of emulated transparency assembly 710 include logic unit layer 750 that contains the necessary logic to manipulate input signals from image sensor layer 730 and provide output signals to electronic display layer 760. In some embodiments, logic unit layer 750 is located between image sensor layer 730 and circuit board 740 as illustrated in FIGURE 12, In other embodiments, logic unit layer 750 is located between circuit board 740 and electronic display layer 760 as illustrated in FIGHKS 13, In general, logic unit layer 7S0 is a specialxaed image processing layer that is capable of mixing an input signal directly from image sensor layer 730 and performing one or more mathematical operations {e.g., matrix transforms} on the input signal before outputfcing a resulting signal directly to electronic display layer 760, Since each logic unit 755 of logic unit layer 750 is responsible only for it's associated facet (i.e., sensor unit 735 or display unit 765), the data of the particular logic unit 755 can be manipulated with no appreciable impact to the system-level I/O. This effectively circumvents the need to parallelize any incomixig sensor data for centralized processing. The distributed approach enables emulated transparency assembly ?10 to provide multiple features such as magnification/zoom {each facet, applies a scaling transform to its input) _/ vision correction {each facet applies a simulated optical transformation, compensating for common, vision issues such as near-sightedness, far-sightedness, astigmatism, etc.), color blindness correction {each facet applies a color transformation compensating for common color blindness issues) > polarization .each facet applies a transformation simulating wave polarization allowing for glare reduction), and dynamic range reduction (each facet applies a transformation that darkens high-intensity regions (e.g. Sun) and lightens low-intensity regions {e.g. shadows}). Furthermore, since any data transformations remain localized to logic unit layer 750 of each facet, there may be no need for long transmission lines. This circumvents issues of crosstalk, signal integrity, etc. Additionally, since the disclosed embodiments do not require optical transparency {but instead harness emulated transparency), there is no functional impact to placing an opaque processing layer between the sensor and display facets ,

[85] In some embodiments, logic unit layer 75.0 contains discrete logic units (erg-, transistors) that are formed directly on circuit board ?4Q, For example, standard photo lithography techniques may be used to form logic unit layer 750 directly on circuit board 740. In other einbodiinerits, each logic unit 755 is a separate integrated circuit (IC) that is coupled to either a sensor facet or a display facet, or directly to circuit board 740. As used herein, *»facet" refers to a discrete unit that is separately manufactured and then coupled to circuit board 740. For example, a "display facet" may refer to a unit that includes a combination of. an el«dbrpnic display layer 760 and a display aide microlens array 12OBj and a "Ssensor facet"' may refer to a unit that— includes a combination of an image senior layer 730 and a sensor side microlens array 720&. In some embodiments, a display facet may include a single display unit 765, or it may include multiple display units 765. Similarly, a sensor facet aay include a single sensor unit 735 _r or it may include multiple sensor units 735- In sortie embodiments, a logic unit 755 may be included in either a sensor facet or a display facet. In embodiments where a logic unit 755 is a separate IC that is coupled directly to either a display ox sensor facet (as opposed to being formed directly on circuit board 740} , any appropriate technique such as 3D IC design with through- silicon viae may be used to couple the IC of logic unit 755 to a wafer of the facet.

[86] in some embodiments, logic unit layer 750 is an application^specific integrated circuit (ASIC) or an arithmetic logic unit (ALC?) , but not a general purpose processor. This allows logic unit layer 750 to toe power efficient. .Furthermore, this allows logic unit layer 750 to operate without cooling, further reducing epst and power requirements of emulated transparency assembly 710.

[87] In some embodiments, logic units 755 are configured to communicate using the same protocol as sensor emits 735 and display units 755, For example, in embodiments where logic units 755 are discrete lCs, the ICs may be configured to communicate in a same protocol as the sensor and display facets (e.g., LVOS or Inter-Integrated Circuit (I»C) } - This eliminates the problem of having fee translate between the sensor and display facet, thereby reducing power and cost.

[80] In some eiBbodiments, logic unit layer. 750 performs pne or more operations on signals received from iifcage sensor layer 730 before transmitting output signals to electronic display layer 760. For example, logic unit layer 750 may transform received signals from image sensor layer 730 to include augmented information for display on electronic display layer 760. This may be used, for example, to provide &R to a viewer. In some eiitbo&iments, logic unit layer 750 may completely replace received signals from image sensor layer 730 with alternate information for display on electronic display layer 760, This may he used, for example, to provide VR to a viewer.

[89] FIGURE 14 illustrates a method 1400 of manufacturing the in-layer signal processing systems of FIG0RE5 12-13, according to certain embodiments. Method 1300 jnay begin in step 1410 where a plurality of sensor units are coupled to a first side of a circuit board. In sosfe embodiments, the sensor units are sensor units 735·, and the circuit board is circuit board 740. In some embodiments, each sensor unit is coupled to one of a plurality of unit attachment locations such as unit attachment locations 74S. Each sensor unit includes a plurality of sensor pixels «

[90] At step 1420, a plurality of display tinits are formed. In some embodiments, the display units are a combination Of display units 765 and logic units 755. Each display unit may be formed by combining an electronic display and a logic unit into a single ^' .3-0 integrated circuit using through-silicon vias. Each display unit includes a plurality pf display pixels. [91] At step 1430, the plurality of display units of step 1420 are co¾pl ^Q & to ^a second side of the circuit board that is opposite the first side- In some embodirsents, each logic unit is coupled to a respective one of the unit, attachment locations. After step 1430, method 1400 may end,

[92] Particular embodiments may repeat one or more steps of method 1400, where appropriate. Although this disclosure describes and illustrates particular steps of method 1400 as occurring in a particular order, this disclosure contemplates any suitable steps of niebhod 1400 occurring in any suitable order (e.g., any temporal order). Moreover, although this disclosure describes and illustrates an example in-layer signal processing system manufacturing method .including the particular steps of method 1400, this disclosure contemplates any suitable in-layer signal processing system manufacturing method including any suitable steps, which may include all, some, or none of the steps of method I400 _r where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying cut particular steps of method 1400, this disclosure contemplates any suitable combination of any suitable components, devices, or systems carrying out any suitable steps pf method 1400.

[93] FIGURES 15-17C illustrate various views pf an array 1500 of pienpptic ceils 1510 that may be used within microiens arrays 720A-E of emulated transparency assembly 710. FIGURE 15 illustrates a pienoptie ceil assembly 1500, FIGURE 16 illustrates a cross section of a portion of the pienoptic cell assembly 1500 of FIGURE 15, and FIGURES 17A-17C illustrate cross sections of a portion of the pienoptic cell assembly 1500 or FIGURE 15 with various incoming and outgoing fields of. light..

[94] Standard electronic displays typically include planar arrangements of pixels which form a two-dimensional rasterised image, conveying inherently two-dimensional data. One limitation is that the planar image cannot be rotated in order to perceive a different perspective within the scene being conveyed. In order to clearly view this image, regardless of What is portrayed within the image itself, either a viewer's eyes or the lens ©f a camera must focus on the screen _* By contrast, a yaluare of light entering the eyes from the real world allows the eyes to naturally focus on any point within that volume of light. This pienoptic "field" of light contains rays of light from the scene as they naturally enter the eye, as opposed to a virtual image focused by an external lens at a single focal plane. While existing light field displays may be able to replicate this phenomenon, they present substantial tradeoffs between spatial and angular resolutions, resulting in the perceived volume of light looking fuz.zy or scant in detail ,.

[95] To overcome problems and limitation with existing light field displays, embodiments of the disclosure provide a coupled light field capture and display system that is capable of recording and then electronically recreating the incoming pienoptic volume of light. Both the capture and the display process are accomplished by an arrangement of pienoptic ceils 1510 responsible for recording or displaying smaller views of a larger compound image. Each pienoptic ceil 151(5 of the sensor is itself comprised of a dense cluster of image sensor pixels, and each pienoptic cell of the display is itself, comprised of a dense cluster of display pixels. In both cases, light rays entering the sensor cells or exiting the display pells are focused by one or more transparent lenslets 1512 to produce a precisely tuned distribution of near-collimaied rays. This essentially records an incoming light field and reproduces it on the opposite side of the assembly. More specifically, for the sensor, the volume of light entering the lens (or series of lenses) of this cell is focused onto the image pixels such that each pixel gathers light from only one direction, as 4eterminer by its position within the cell and the profile of the lens- This allows rasterized encoding of the various angular rays within the light field, with the number of pixels in the cell determining the angular resolution recorded. For the display, the light emitted from the pixels is focused toy an identical lens (or series of lenses) to create a volume o£ light that matches what was recorded by the sensor, plus any electronic augmentation or alterations (e.g., from logic unit layer ?50 described above?. The cone of emitted light from this cell contains a subset pf rays at enough interval angles to enable the formation of a light field for the viewer, where each output ray direction is determined by the position of its originating pixel within the cell and the profile of the lens,

[96] Pienoptic cells 1510 may be utilised by both sensor side microlens array 720A and display 3ide microlens- array 72QB. For example, multiple plenoptic cells 151OR may be included in sensor side microlens array 72QA> and each piehpptic cell 1510A may be coupled to or otherwise adjacent to an image sensor 1520. Image sensor 1520 may foe a portion of linage sensor layer 730 and may include a sensor pixel array 1525 that includes sensing pixels 1725. Similarly, multiple plenoptic cells 151QB may be included in display aide microlens array 720B, and each plenoptic ceil 1510E may be coupled to ox otherwise adjacent to a display 1530. Display 1530 may be a portion of electronic display layer ?S0 and may include .a display pixel array 1625 that includes display pixels 1735·. Sensing pixels 1725 may be sensor pixels 1300 as described in FIGURES 18-20 and fcfceir associated descriptions in U.S. Patent Application No- 15/724,027 entitled ^,x 3tacJced Transparent Pixel Structures for Image Sensors," which is incorporated herein by reference in its entirety. Display pixels 1735 may be display pixels 100 as described in FIGURES 1-4 and their associated descriptions in U.S. Patent Application No. 15/724,004 entitled "Stacked Transparent Pixel Structures for Electronic Displays," which is incorporated herein by reference in its entirety.

[97] In some embodiments, plenoptic cell 151G includes a transparent lenslet 1512 and cell wails 1514. Specifically, plenoptic cell 1510A includes transparent lenslet 1512A and cell walls 1S14A, and plenoptic cell 1510B includes transparent lenslet 1512B and cell walls 1514S. In some embodiments, transparent lenslet 1512 contains a 3D shape with a cellimating lens on one end of the 3D shape _* For example, as illustrated in FIGURE 15, transparent lenslet 1512 may be a rectangular cuboid with a collimating lens cm one end of the rectangular cuboid. In other embodiments, the 3D shape of transparent lenslet 1512 tnay be a triangular polyhedron, a pentagonal polyhedron, a hexagonal polyhedron, a heptagonai polyhedron, an octagonal polyhedron, a cylinder, or any other appropriate shape. Each plenoptic cell 1610A includes an input field of view (FOV) 1610 (e.g., 30 degrees), and each plenoptic cell 1510B includes an output FOV 1620 (e.g., 30 degrees) . In some embodiments, Input FOV 1610 matches output FOV 1520 for corresponding plenoptic ceils 1510.

![98j Transparent lenslet 1512: may foe formed from any appropriate transparent optical material. For example, transparent lensiet 1512 may fee formed from a polymer, silica glass, or sapphire. In some embodiments, transparent lenslet 1512 may be formed from a polymer such as polycarbonate or acrylic. In some embodiments, transparent lenslets 1512 may be replaced with waveguides and/or photonic crystals in order to capture and/ox produce a light field.

[99] In general, cell walls 1514 are barriers to prevent optical crosstalk between adjacent plenoptic ceils 1510, Ceil walls 1514 may be formed from any appropriate material that is opaque to visible light when hardened. In some embodiments, cell walls 1514 are formed from a polymer. Preventing optical cross talk vising cell wails 1514 is described in more detail below in reference to FIGURES 17?. and 17C,

[.100] In some embodiments, image sensor 1520 includes ox is coupled to backplane circuitry 163OA, and display 1530 includes or is coupled to backplane circuitry 1S30B. In general, backplane circuitry 163GA-8 provides electrical connections to permit image data to flow from image sensor 1520 to display 1530. In some embodiments, backplane circuitry 1630A and backplane circuitry 1630B are the opposite sides of a single backplane. In some embodiments, backplane circuitry 1630A and backplane circuitry 1630B are circuit board 740.

[101] In some embodiments, a filter layer 1640 may be included on one ox both ends of transparent lenslet 1512 in order to restrict the entry or exit of light to a specific incidence angle. For -example, a first filter layer 164OA may be included on the convex end of transparent lenslet 15.12, and/or a second filter layer 1S4QS may be included on the opposite end of transparent lenslet 1512. Similar to cell walls 1514, such a coating or film may also limit ireage bleed between adjacent transparent lenslets 1512 to an acceptable amount. Filter layer 1640 may be used in addition to ox in place of cell walls 1514.

[102] FIGURES 17A-17C each illustrate a cross-sectional view of seven adjacent plenoptic ceils 1510 for a sensor side microlens array 730A and a corresponding display side microlens array 720B. ?heae figures show how incoming light fields 701 are captured by image sensors 1520 and electronically replicated on display 1530 to emit a virtually identical field Of light. in FISORS 17ft, an incoming light field 1710 irpm objects directly in front of the sensor plenoptic delis 1510 are focused by the transparent lenslets 1512 of the sensor plenoptic cells 1510 onto center sensing pixels 1725. Corresponding light is then transmitted by corresponding: center display pixels 1735 of corresponding display plenoptic cells 1510. The transmitted light is £o£u*ed and emitted as emitted light field 1711 by the transparent lenslets- 1$12 of display plenoptic ceils 1510. Emitted light field 1711 precisely matches the zero degree source light field ii.e., incoming light field 1710). In addition, emitted light rays striking cell walls 1514 at location 1740 that would otherwise penetrate adjacent display plenoptic cells 1510 are blocked by the opaque cell walls 1514, thereby preventing optical cross-talk-

[103] In FIGPRB 178, an incoming light field 1720 from objects fourteen degrees off the a*is of sensor plenoptic ceils 1510 are focused fey the transparent lenslets 1512 of the sensor plenoptic cells 1510 onto top sensing pixels 1725. Corresponding light is then transmitted by corresponding opposite (i.e., bottom) display pixels 1735 of corresponding display plenoptic cells 1510. The. transmitted light is focused and emitted as emitted light field 1721 by the transparent lenslets 1512 of display plenoptic cells 1510, Emitted light field 1721 precisely matches the 14 degree source light field {i.e., incoming light field 17205.

[104] In FIGURE 170, an incoming light field 1730 from objects 25 degrees off the axis of sensor plenoptic ceils 1510 are focused by the transparent lenslets 1512 of the sensor plenopLic ceils 1510 entirely onto cell walls 1514. Because incoming light field 1730 is focused entirely onto cell walls 1514 of sensor plenoptic cells 1510 instead of sensing pixels 1725, no corresponding light is transmitted by corresponding display plenoptic cells 1510. In addition, incoming light rays striking ceil walls 1514 at location Ϊ750 that would otherwise penetrate adjacent sensor plenoptic cells 1510 are blocked by the opaque cell walls 1514, thereby preventing optical cross-ta1Jc.

[105] FIGURES 1SA-19B illustrate a method of maraafaeturing the plenoptic cell assembly of FIGURE 15, according to certain embodiments. In FIGURE ISA, a microlens array (MIA} sheet 1910 is formed or obtained. MLA sheet 1310 includes .a plurality of lenslets as illustrated. In FIGURE 13B, a plurality of grooves 18-20 are cut around each of the plurality of lenslets of MIA shesc 1810 to a predetermined depth. Irs some embodiments, grooves 1820 may be cut using multiple passes to achieve the desired depth. In some embodiments _/ grooves 182:0 may foe cut using laser ablation, etching, lithographic processes, or any other appropriate method. After grooves 1820 are cut to the desired depth, they are filled with a material configured to prevent light from bleeding through grooves 1820, In some embodiments, the Kiaterial is any light, absorbing (e.g., carbon nanotuhes) or opaque material (e.g., a ηση-reflectivs opaque material or a tinted polymer) when hardened. The resulting plenoptic cell assembly after grooves 1820 are filled and allowed to harden is illustrated in FIGURES 20-21,

[106] FXGORES 19A-19B illustrate another method of manufacturing the plenoptic cell assembly of FIGURE 15, according to certain embodiments. In FIGURE 1.3¾, a pre-foxioed lattice 1830 having voids 1840 is obtained or formed. Lattice 1830 is made of any suitable material as described above fox cell wails 1514. Lattice .1830 may be formed from any suitable method including, but not limited to, additive manufacturing and ablation of cell matter.

[107] In FIGURE 19B, voids 3.840 are filled with an optical polymer 1350. -Optical polymer 1850 may be any suitable material as described above for transparent lenslet 1512, After voids Ϊ840 are filled with optical polymer 1850, the final lens profile is created using molding or ablation, ftn example of the resulting plenoptic cell assembly after the lenses are formed is illustrated in FIGURES 20-21.

[108] FIGURE 22-23 illustrates a flexible circuit board 2210 that may be used as circuit board 740 by the emulated transparency assembly 710 of FIGURE 7, according to certain embodiments. Generally, wrapping electronics around a 30 shape such as spherical or semispherical surface is a non- trivial task. Though various examples of flexible and even stretchable circuitry are currently available, there are several hurdles to overcome when positioning such electronics on a small radius ¾e.g, _/ 30 - 60 ram) spherical ox. semispherical surface. For example, bending of flexible electronics substrates in one direction does not inherently indicate adaptability to compound curvature, as the torsional forces required for such curvature can be damaging to the thin films involved. As another example, questions remain about the degree of stretcbability and lifetime of s-tretenable electronics currently available,

[109] To address the problems and limitations of current solutions, embodiments of the disclosure present a 3D {e.g., spherical or semispherioai} electronics manufacturing method using a geodesic faceted approach consisting of an array of small, rigid surfaces built on a single flexible circuit. In some embodiments, the flexible circuit is cut to a specific net shape and then wrapped to a 3D shape (e.g., a spherical, pr seafcisphe-rica1 shape) and locked into place to prevent wear and tear -from repeated flexing. The method is especially useful to accommodate the narrow radii of curvature (s.g,, 3.Q-& ^Q ram) necessary for head-mounted near-eye wrapped displays . In same embodiments, the assembly includes a single, foundational flexible printed circuitry layer, with rigid sensor and display -arrays layered on opposite sides of the flexible circuit. The entire assembly including sensor and display layers may be manufactured by standard planar semiconductor processes (e.g., spin coatings, photolithography, etc.). The rigid electronics layers may be etched to form individual sensor and display units {i.e., "facets") and then connected to the flexible circuitry by connection pads and adhered through patterned conductive and non-conductive adhesives. This permits the flexible circuitry to fold slightly at the. edges: between the rigid facets. In some embodiments, foilowing planar manufacturing, the fully cured and functional electronic stack is formed to the desired final 3D shape using one side of a final rigid polymer casing as a mold. In this way, the arrays of rigid electronics facets are not deformed but simply fall Into place in their mold, with the flexible circuitry bending at defined creases/gaps to match the faceted interior of the casing. The assembly may be finally capped and sealed using an opposite matching side of the rigid: casing.

[lip] Embodiments of the disclosure are not limited to only spherical or semispherical shapes, although such shapes are certainly contemplated. The disclosed erabp&iraenfcs- may be formed into any compound curvature or any other revolved shape. Furthermore, the disclosed embodiments may be formed into any non-uniform curvature, as well as non-curved (i.e., flat) surfaces _*

[111] FIGURE 22 illustrates flexible circuit board 2210 in two different states: a flat flexible circuit board 22¾0A and a 3D-shaped flexible circuit board 221OB. Flexible circuit board 2210 includes facet locations 2220, which in general are locations in which facets (e.g., sensor facets 3735, display facets 2£65, or logic facets 2655 discussed below) :may be installed on flexible circuit board 2210. In some embodiments, flexible circuit board 2210 includes gaps 2215. As illustrated in the bottom portion of FIGURE 22, when flexible circuit board 223.0 is fiat, at least some of facet location 2220 are separated from one or more adjacent facet locations 2220 by one or more gaps 2215. As illustrated in the top portion of FISUBE 22, when flexible circuit board 2210 is formed into a 3D shape, gaps 2215 may be substantially eliminated, thereby forming a continuous surface across at least some of the. facets that are coupled at facet locations 2220 (e.g., a continuous sensing surface serosa multiple sensor facets 3735 or a continuous display surface across multiple display facets 2€65) .

[112] In general, facet locations 222 ⁽ 3 may have any shape. In some embodiments, facet locations 2220 are in the shape of a polygon (e.g., a triangle, square-, rectangle, pentagon, ^' hexagon, heptagon, or octagon) . In some embodiments, facet .locations- 2220 are all identical. In other embodiments, however, fapet locations 2220 all share the same polygon shape -;e,g., all are hexagoaal) , but have different dimensions. In some embodiments, facet locations 2220 have heterogeneous shapes (e.g. _/ some are rectangular and some are hexagonal) . Any appropriate shape of facet locations 2220 my be used,

[113] In some embodiments, facet locations 2220 are arranged in columns 2201, In some embodiments, facet locations 2220 are additionally Or alternatively arranged in rows 2202. While a specific pattern of facet locations 22.20 is illustrated, any appropriate pattern of facet locations 2220 .eiay be used.

( 1X41 FIGURE 23 illustrates additional details of flexible circuit board 2210, according to certain embodiments. In some embodiments, each facet location 2220 includes pads and/ox: vias for coupling sensor or display facets to flexible circuit board 2210. As an example, some embodiments of flexible circuit board 2210 include BGA pads 2240 at each facet location 2220. Any appropriate pattern and number of pads/vias may be included at each facet location 2220.

[115] In general, each particular facet location 2220 is configured to transmit signals between a particular censor facet coupled to the particular facet location and a particular display facet coupled to an opposite side of the particular facet location _* For example, a particular facet location 2220 may have a sensor facet 3735 coupled to one side, and a display facet 2685 coupled to its opposite side. The particular facet location 2220 provides the necessary electrical connections to permit signals from the sensor facet 3735 to travel directly to the display facet 2665 _/ thereby enabling the display facet 2665 to display light that corresponds to light captured by the sensor facet 3735.

[116] In some embodiments, wire traces 2230 are included on flexible circuit board 2210 to electrically connect facet locations 2220. Tor example, wire traces 2230 may connect to interconnection psds 2250 of each facet location 2220 in order to electrically connect adjacent facet locations 2220. In some embodiments, facet locations 2220 are serially connected via wire traces 2230. E'er example, FIGURE 24 illustrates a serial data flow through flexible circuit board 2210, according to certain embodiments. In this example, each facet location 2220 is assigned a unique identifier (e.g., ?2," and so on), and data flows serially through facet locations 2220 via wire traces 2230 as illustrated. In this manner, each facet location 2220 may be addressed by a single processor or logic unit using its unique identifier. Any appropriate addressing scheme and data flow pattern may be used. [117] FIGURE 2.5 illustrates a method 2500 of manufactoring an electronic assembly using flexible circuit beard 2210 of F1GUF.S 22, according to certain embodiments. At step 2510, a plurality of facet locations are formed on a flexible circuit board. In some embodiments; the facet locations are facet locations 2220, and the flexible circuit board is flexible circuit board 2210. Each facet location corresponds to one of a plurality of sensor facets and one of a plurality of display facets. The sensor facets may be sensor facets 3735, and the display facets may be display facets .26|65. In some embodiments, the plurality of facet locations are arranged into a plurality of facet columns such as columns 2201. In some embodiments, the plurality of facet locations are additionally or alternatively arranged into a plurality of facet: rows such as rows 2202.

[118] &t step 2520, the flexible circuit board of step 2510 is cut or otherwise shaped into a pattern that permits the flexible circuit board to be later formed into a 30 shape such as a spherical or semispherical shape. When the flexible circuit board is fiat, at least some of the facet locations are separated from one or more adjacent- facet locations by a plurality of gaps such as gaps 2215. ¾fhe.n the flexible circuit board is formed into the 3D shape, the plurality of gaps are substantially eliminated.

[119] At step 2530, the electronic assembly is assembled by coupling a first plurality of rigid facets to a first side of the flexible circuit board _* The first plurality of rigid facets may be sensor facets 3735 or display facets 2665. Each rigid facet is coupled to a respective one of the facet locations. In some embodiments, the first plurality of rigid facets are coupled to connection pads en the first, side of the flexible circuit board using, patterned conductive and non- conductive adhesives.

[120] In some embodiments, the first plurality of. rigid facets of step 2530 are rigid sensor facets such as sensor facet-- 3735, atad method 2500 further includes coupling a plurality of rigid display facets sach as display facet 3665 to a second side of the flexible circuit board that is opposite the first side. In this case, each particular facet location is configured to transmit signals between a particular rigid sensor facet electrically coupled to the particular facet location and a particular rigid display facet electrically coupled to the same particular facet location. This permits light to be displayed from the particular rigid display facet that corresponds to light captured by the corresponding rigid sensor facet.

[121] At step 2540, the assembled electronic assembly is formed into the desired 3D shape. In some embodiments, this step involves placing the flexible circuit board with its coupled rigid facets into one side of a rigid casing that is in the desired shape. This allows the rigid facets to fall into defined spaces in the casing and the flexible circuit board to bend at defined creases/gaps between the rigid facets. After placing the flexible circuit board with its coupled rigid facets into one side of the rigid casing, an opposite matching side of the rigid casing may be attached to the first side, thereby sealing the assembly into the desired shape .

[122] Particular embodiments may repeat one or more steps of method 2500, where appropriate. Although this disclosure describee and illustrates particular steps of method 2500 as occurring in a particular order, this disclosure contemplates any suitable steps of method 2500 occurring in. any suitable order {e.g., any temporal order) . Moreover, although this disclosure describes and illustrates an example method of manufacturing an electronic assembly using flexible circuit board* this disclosure contemplates any suitable method of manufacturing an electronic assembly using flexible circuit board, which may include all, some, or none of the steps of method 2500, where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of method 2500, this disclosure contemplates any suitable combination of any suitable components, devices, or systems carrying out any suitable steps of method 2500.

[123] FIGURES 26-36 illustrate distributed multi-screen arrays for high density displays, according to certain embodiments. In general, to provide a near-eye display capable of emulating the entire visual field of a single human eye, a high dynamic range image display with a resolution orders of magnitude greater than current common display screens is required. Such displays should be able to provide a light field display with enough angular and spatial resolution to accomodate 20/20 human visual acuity. This is an enormous amount of information, equating to a total horizontal pi*el count of 1O0K to 20OK. These displays should also wrap around the entire field pf vision of one human eye <approximately 160° horizontally anq 130° vertically} . For rendering binocular vision, a pair of such displays spanning the entirety of a curved surface around each eye would be necessary. Typical displays available today, however, are unable to meet these requirements. [124] To address these and other limitations of current displays?, embodiments of the disclosure provide :an array of small, high-resolution micro displays !¾,g./ display facets 2665} of custom sizes and shapes, ail of which are formed ahd then assembled on a larger, flexible circuit board 2210 that may be formed into a 3D shape {e.g., a semispherical surface) , The micro displays may be mounted to the interior side ©f semispherical circuitry, where another layer containing an array of TFT logic units (e.g., logic units 755) may be included to handle all the power and signal «\anag«xaej&t .. Typically, one logic unit 755 may be included for each micro display. Bach micro display operates as a discreet unit, displaying data from the logic unit behind it, Any additional information (e.g., such as external video for AR, VR, or ½R applications} may be passed to the entire array via a central control processor. In some embodiments, the external data signal progresses serially from one micro display to the next as a packed multiplex stream, while the TFT logic unit for each display determines the source and section of the signal to read. This allows each unit to act independently of any other display, providing a large array of many high-resolution displays with unique content, on each, such that the whole assembly together forms essentially a single extremely high- resolution display .

[125] To fulfill the requirements of resolution, color clarity, and luminance output, each micro display may hays a unique, high performance pixel architecture. For example, each laicro display screen may include arrays of display pixels 100 as described in FIGURES 1-4 and their associated descriptions in U.S. Patent Application No, 15/724,004 entitled "Stacked Transparent Pixel Structures for Electronic Displays," which is incorporated herein by reference in its entirety. The micro- display screens way be assembled on the same substrate using any appropriate method. Such simultaneous manufacturing using standard semiconductor layering and photolithographic processes virtually eliminates the · overhead and - costs associated with production and packaging of many individual screens, greatly improving affordaMlity .

[126] FIGURE 26 illustrates a cut-away view of a curved multl-display array 2600, according to certain embodiments. FIGUBS 26 is essentially the back side of flexible circuit board 221GB of FIGURE 22 with the addition of logic facets 2655 and display facets 2665 coupled to flexible circuit board 221QB at facet locations 2220, In general, each logic facet 2655 is an individual logic unit 755 from logic unit layer 75.8, Similarly, each display facet 2665 is an individual display unit 765 from display layer 760 coupled with a portion of microlens array 720.

[127] In some embodiments, each individual logic facet 2655 is coupled to flexible circuit board 2210, and each individual display facet 2665 is then coupled to one of the logic facets 2655. In other embodiments, each logic facet 2655 is first coupled one of the display facets 2665, and the combined facet is then coupled to flexible circuit board 2210. In such embodiments, the combined logic facet 2655 and display facet 2665 may be referred to as a display facet 2665 for simplicity. As used herein _r "display facet" may refer to both embodiments {i.e., an individual display facet 2665 or a combination of a display facet 2665 with a logic facet 2655) .

[128] In general, each display facet 2665 can be individually addressed <e.g., by a central control processor not pictured), and a collection of display facets 2665 may represent a dynamic, heterogeneous collection, forming a singular collective . In other words , laulti-display array 2600 provides a tiled electronic display system showing imagery through individual display facets 2665 that together form a complete whole . Bach individual display facet 2665 is capable of providing multiple different display resolutions and can be customized on the fly to run a different resolution, color range, frame rate, etc. For example, one display facet 2665 may have a 512x512 display resolution while an adjacent display facet 2665 (of equal size) has a 128x128 display resolution, wherein the former represents a higher concentration of imagery data. In this example, these two displays are heterogeneous, but are individually controllable and work in unison to form a singular display image _¾

[129 ] The overall collection of display facets 2665 can follow any curved or flat surface structure . For example, display facets 2665 may be farmed into a hemispherical surface, a cylindrical surface, an oblong spherical surface, or any other shaped surface .

[130] Logic facets 2655 and display facet 2665 may be in any appropriate shape. In some embodiments, the shapes of logic facets 2655 and display facets 2665 match each other and the shape of facet locations 2220 _r In some eiabodimexits, logic facets 2653 and display facets 2665 are in the shape of a polygon such as a triangle, a quadrilateral, a pentagon, a hexagon, a heptagon, or an octagon. In some embodiments, some or all of logic facets 2655 and display facets Z665 have non- polygorial shapes . For example, display facets 26-65 on the edges of flexible circuit board 2210 may not foe polygonal as they may have curved cutoffs so as to enhance the aesthetic of the overall assembly. [131] In addition to having a Selectable/controllable display resolution _/ each display facet 2665 may in scree embodiments also have a selectable color range froj&i a plurality of color ranges and/or a selectable frame rate from a plurality of frame rates. In such eiKbodirnents , the display facets 2665 of a particular flexible circuit board 2210 are configurable to provide heterogeneous frame rates and heterogeneous color range. For example, one display facet 2665 may have a particular color range while another display facet 2665 has a different color range. Similarly, one display facet 2605 may have a particxiiar frame rate while another display facet 2665 has a different frame: rate.

[132] FIGURE 27 illustrates an exploded view of the curved multi-display array 2600 of FIGURE 26, and FIGURES 28- 2:9 illustrate additional details of logic facet 2655 and display facet 2665, according to certain embodiments . As illustrated in these figures, each logic facet 2655 may include interconnections pads 2850 that may be electrically coupled to interconnection pads 225-0 of adjacent logic facets 2655.. This may enable display facets 2665 to be serially coupled via wire traces 2230. In addition, each logic facet 2655 may include pads 2.840 in a pattern that matches pads 2940 on the back side of display facet 2665. This permits logic facet 2655 and display facet 2665 to be coupled together using any appropriate technique in the art. In seme embodiments, pads 2840 and pads 2940 are BGA pads or any other appropriate 3urface-mounting pads .

{1333 FIGURES 30 and 32 illustrate a back side of flexible circuit board 2210 of FIGURE 22, and sh&vf similar details as described in reference to FIGURE 23. FIGURES 31 and 33 illustrate a serial data flow through flexible Circuit board 2210, and show similar details as described in reference to FIGURE 24. FIGURE 34 illustrates an array of logic facets 2655 that have beer. £oxmed ^' into a semispherical shape, according to certain embodiments. In this figure, flexible circuit- fcoaxd 2210 and. display facet 2665 have been removed for clarity. FIGURE 35 illustrate* consnunications between the logic facets 20:55 of. FIGURE 34, according to certain embodiments. As illustrated in this figure, each logic facet 2655 may communicate with, adjacent logic facets 265S using interconnections pads 2850. In addition, each logic facet 2655 may have a unique identification as illustrated in FIGURE 35. This permits each logic facet 2$55 to fee. uniquely addressed by, for example, a central processing unit.

[134] _, FIGURE 36 illustrates a method 3600 of manufacturing the curved multi-display array of FIGURE 26, according to certain embodiments. Method 3600 may begin in step 3610 where a plurality of facet locations are £o£Med on a circuit board. In scioe embodiments, the facet locations are facet locations 2220 and the circuit, board is flexible circuit board 2210. In some .embodiments, each facet location corresponds to one of a plurality of display facets such as display facets 2665.

[135] At step 3620, the flexible circuit board is cut or otherwise formed into a pattern that permits the flexible circuit board to be later formed into a 3Ώ shape. When the flexible circuit board is fiat, at least some of the facet locations are separated from one or more adjacent facet locations by a plurality of gaps such as gaps 2215. When the flexible circuit beard is formed into the 3D shape, the plurality pf gaps are substantially eliminated. ;[l36 ^' j At step 3630, a plurality of logic facets are coupled to a first side of the flexible circuit board. Each logic facet is compiled to a respective one of the facet locations of step 3610. At step 3640, a plurality of display facets are coupled to a respective one of the plurality of logic facets of step 3S3Q. In alternate embodiments, the display facets may be mounted to the logic facets of step 3630 at the wafer level prior to coupling: the logic facets to the first side of the flexible circuit bpard. At step 3650, the assembled electronic display assembly is formed into the 3D .shape _r In some embodiments, this step may be similar to step 2540 of method 2500 described above. After step 3650, _: metnod 3600 may end,

[137] particular embodiments may repeat erne or more steps of method 3600, where appropriate. Although this disclosure describes and illustrates particular steps of method 3600 as occurring in a particular order, this disclosure contemplates any suitable steps of method 3600 occurring in any suitable order {e.g., any temporal order} . Moreover, although this disclosure describes and illustrates an example method of manufacturing a curved multi-display array, this disclosure contemplates any suitable method of manufacturing a curved a&ulti-display array, which may include, ail, some, or none of the steps of method 3600, where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying oat particular steps of method 3600, this disclosure contemplates any suitable combination of any suitable cozoponents, devices, or systems carrying out any suitable steps of method 3600. [138] FIGURES 37-42 illustrate a distributed multi- aperture camera array 3700, according to certain embodiments. In general, to capture the fall light field of the entire visual field of a single human eye, a large, high dynamic range image sensor with a resolution much higher than ^: currently available is needed- Such an image sensor would enable a light field camera with enough angular and spatial resolution to accomodate 20/20 human visual acuity. This is an enormous amount of information/ equating to a total horizontal pixel count of iOOK to 2C0K. This multi-aperture image sensor must also wrap around the entire field of vision of one human eye (approximately 160 ^* horizontally and 130° vertically) , For imaging binocular vision, a pair of such cameras spanning the entirety of a curved surface around each eye are necessary. Typical image sensor assemblies available today are unable to meet these requirements.

[139] To overcome these and other limitations of typical linage sensors, embodiments of. the disclosure provide an array of small image sensors of custom sizes and shapes, all of which are assembled on a larger, flexible circuit board 2210 that is formed to a 3D (e.g., semi-spherical) shape. The image sensors (e.g., sensor facets 3735) are mounted to the exterior side of flexible circuit, board 2210, where another layer containing an array of TFT logic units (e.g., logic units 755} may foe provided to handle all the power and signal management - one logic unit for each display. Bach image sensor operates as a discrete unit passing readout data to the logic unit behind it (in embodiments that include logic units), where it. is handled and routed accordingly (e,g., to a corresponding display facet 2665 in some embodiments) . This allows each sensor facet 3735 to act independently of any other sensor facet 3735, providing a large array of many apertures capturing unique content on each, such that the Whole assembly essentially becomes a seamless, very high, resolution, multi-node camera. It should foe noted that while iiaage sensors may pass data to their paired- logic units in some embodiments, the functionality of the image sensors themselves do not necessarily require logic unit coupling.

[140] To fulfill the requirements of resolution, color clarity, and luminance output, each micro sensor may have a unique, high performance pixel architecture . For example, each micro sensor may include arrays of sensor pixels 1300 as described in FIGORES 18-20 and their associated descriptions in UVS. Patent Application No, 15/754,027 entitled "stacked. Transparent Pixel Structures for Image sensors," which is incorporated herein by reference in its entirety. The micro sensor may be assembled on the ^* game substrate using any appropriate method. Such simultaneous manufacturing using standard semiconductor layering and photolithographic processes virtually eliminates the overhead and costs associated with production and packaging of many individual screens, greatly improving affordafeiiity,

[141] £nobher characteristic of certain embodiments of distributed multi-aperture camera array 370G is built-in depth perception based on parallax between different plenoptic cells. Imagery produced by cells on opposite sides or a giver- sensor may be used to calculate the offset of image detail, where offset distance directly correlates with proximity of the detail to the sensor surface. This scene information may be used by a central processor when overlaying any augmented video signal _/ resulting in AP./biR content placed in front of the viewer at the appropriate depth. The information can also be used for a variety of artificial focus blurring and depth- sensing tasks, including, simulated depth of field, spatial edge detection, and other visual affects.

[142] FIGURE 37 illustrates a cut-away view of distributed rouiti-aperture -camera array ^{· ·} 3700> -.according to certain enbodimente . FIGURE 37 is essentially the flexible circuit board 22108 of. FI@JJ.RE 22 with the addition of sensor facet 3735 coupled to flexible circuit board 2210B at facet locations 2220. In some embodiments, each sensor facet 3735 is an individual sensor unit 735 frpra image sensor layer 730.

[143] In some embodiments, eacn individual sensor facet 3735 is coupled to flexible circuit board 2210, In other embodiments, each individual sensor facet 3735 is coupled to one of the logic facets 2655 that has been coupled to flexible circuit board 2210. In other enibodiii-ents, each logic facet 2655 is first coupled one of the sensor facets 3735, arid the combined facet is then coupled to flexible circuit board 2210. In such embodiments. _/ the combined logic facet 2655 and sensor facet 3735 may be referred to as a sensor facet 373:5 for simplicity. &e used herein, '"sensor facet" may refer to both embodiments (i.e., an individual sensor facet -37.35 or a combination of a sensor facet 3735 with a logic facet 2655} .

[144] In general, each sensor facet 3735 can be individually addressed (e.g., by a central control processor not pictured), and a collection of sensor facets 3735 ssay represent a dynamic, heterogeneous collection forming a singular collective. In other words, distributed multi- aperture camera array 3700 provides a tiled electronic sensor system providing imagery captured through individual sensor facets 373.5 that together form a complete whole. Each individual sensor facets? 3735 is capable of ^" capturing images at: multiple different resolutions and can foe customized on the fly to capture a different resolution, color range, frame rate, etc. For example, one sensor facet 3735 may have a 312x512 capture resolution while an adjacent sensor facet 3735 (of equal size) has"a 128x128 'capture resolution, wherein the former represents a higher concentration of imagery data, in this example, these two sensors are heterogeneous, but are individually controllable and work in unison to capture a singular light field.

[145] The overall collection of sensor facets 3735 can follow any curved or flat surface structure. s'cr example, sensor facets 3735 may he formed into a semispherical surface, a cylindrical surface, an oblpng spherical surface, or any other shaped surface .

[146] Sensor facets 3735 may be in any appropriate shape. In some embodiments, the shapes of sensor facets 3735 match the shapes of display facets 266S and the sha:pe of facet locations 2220. In some embodiments, sensor facets 3735 are in the shape of a polygon such as a triangle, a quadrilateral, a pentagon, a hexagon., a heptagon, pr an octagon. In some embodiments, some or «11 of sensor facets 3735 have non- polygonal shapes. For example, sensor facets 3735 on the edges of flexible circuit board 2310 may not be polygonal as they may have curved cutoffs so as to enhance the aesthetic of the overall assembly.

[147] In addition to having a selectafoIe/contxollabl¾ resolution, each sensor facets 3735 may in some embodiments also have a selectable color range from a plurality of color ranges and/or a selectable frame rate from a plurality of frame rates. In such embodiments, the sensor facets 3735 of a particular flexible circuit board 2210 are configurable to provide heterogeneous- .frame rates and heterogeneous c&l&v range. For example, one sensor facet 3735 may have a particular cplpr range while another sensor facet 3735 has a different color range. Similarly, one sensor facet 3735 may have a particular frame rate while another sensor facet 3735 has a different frame rate.

[148] FIGURES 38-39 illustrate exploded views of ^" the distributed multi-aperture camera array 3700 of FIGURE 37, according to certain embodiments. As illustrated in these figures, each sensor facet 3735 may include pads 3940 in a pattern that matches pads 2240 on flexible circuit board 2210 or pads 2940 on logic facet 2655. This permits sensor facet 3735 to be coupled to logic facet 2655 or flexible circuit board 2210 using any appropriate technique in the art. In some embod±n»nts _/ pads 3940 are BGh pads or any other appropriate surface-mounting pads. FIG0RBS 4Ρ-4Ό illustrate similar views of flexible circuit board 2210 as shown in FIGURES 23-24, except that flexible circuit board 2210 has been formed into a 3D shape.

[149] FIGURE 42 illustrates a method 4200 of inanufaoluring distributed multi-aperture camera array 3700, according to certain embodiments. Method 4200 may begin in step 4210 where a plurality of facet locations are formed prt a circuit board s In some eabodljaeats, the facet locations are facet locations 2220 and the circuit board is flexible circuit board 2210. In some embodiments, each facet location corresponds to one of a plurality of sensor facets such as sensor facets 3735.

[150] At step 4229, the flexible circuit board is cut or otherwise formed into s pattern that permits the flexible circuit board to be later formed into & 3D shape. When the flexible circuit board is flat, at least some of the facet locations are separated from one or more adjacent facet ^" locations toy a plurality of gaps such as gaps 2215- When the flexible circuit board is formed into the 3D shape, the plurality of gaps are- .substantially eliminated.

[151] Afc step 4230, a plurality of sensor facets are coupled to a first side of the flexible circuit board. Bach sensor facet is coupled to a respective one of the facet locations of step 4210. At step 4240, the assembled electronic camera assembly is formed into the 3D shape.* In some, embodiments, this step may be similar to step 2540 of method 2500 described above. After step 4240, method 4200 may end .

[152] Particular embodiments may repeat one or more steps of method 420G, where appropriate. Although this disclosure describes and illustrates particular straps of method 4200 as occurring in a particular order, this disclosure contemplates any suitable steps of method 4200 occurring in any suitable order (e.g., any temporal order) - Moreover, although this disclosure describes and illustrates an example method of manufacturing, a distributed multi- apsrtuxe camera array, this disclosure contemplates any suitable method of manufacturing a distributed multi-aperture camera array, which may include all, some, or none of the steps of method 4200, where appropriate. Furthermore, although this disclosure describes and illustrates particular components, devices, or systems carrying out particular steps of method 4200, this disclosure contemplates any suitable combination of any suitable components, devices, or systems carrying: out any suitable steps of method 4200. [153] Herein, *or" is inclusive and not exclusive, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, ^V, A or B" means "ft, B, or both," unless expressly indicated otherwise or indicated otherwise hy context. Moreover; "and'' is tooth joint and several, unless expressly indicated otherwise or indicated otherwise fey context. Therefore _f herein, "*A and B" means *A and B, jointly or severally, " unless expressly indicated otherwise or indicated otherwise by context.

[154] The scope of this disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example -embodiments described or illustrated herein that a person having ordinary skill in the art would comprehend. The scope of this disclosure is not limited to the example embodiments described or illustrated herein. Moreover, although thi3 disclosure describes and illustrates respective embodiments herein as including particular components, elements, functions, operations, or steps, any of these embodiments may include any combination or permutation of any of the components, elements, functions, operations, ox steps described or illustrated anywhere herein that a person having ordinary skill in the art would comprehend. Furthermore, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled tp, operable to, or operative to perform a particular function encompasses that apparatus, system, component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that, apparatus* system, or component is so adapted, arranged, capable , configured, enabled, operable, or operative. [155] Although this disclosure describes and illustrates respective embodiments herein as including particular components, elements, functions, operations, or steps, any of these embodiments may include any cortsbination or permutation of- any of ^' the component8, elements;, "functions, operations, or steps described or illustrated anywhere herein that a person having ordinary skill in the art would comprehend.

[1561] Furthermore, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system; or . component Is so adapted, arranged, capably, configured, enabled, operable, or operative,