CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to US provisional application 61/265,297 for "Selective p-n junction fabrication technique for high-aspect-ratio semiconductor microstructures" filed on November 30, 2009, US provisional application 61/265,306 for "Light- trapping Si wire-array structure for solar cells and photodetectors" filed on November 30, 2009, and US provisional application 61/313,654 for "Processing Steps for the Fabrication of a Microwire Array Solar Cell" filed on March 12, 2010, all three of which are herein incorporated by reference in their entirety. The present application is also related to US Patent Application

S/N for "Semiconductor Wire Array Structures, and Solar Cells and

Photodetectors Based on such Structures" filed on even date herewith, Attorney Docket Number P708-US, also incorporated herein by reference in its entirety.

FIELD

[0002] The present disclosure relates to patterning methods for three-dimensional structures, such as semiconductor microstructures. Examples of these microstructures are semiconductor wire arrays, such as silicon (Si) wire arrays.

STATEMENT OF GOVERNMENT GRANT

[0003] The present application was supported in part by the Department of Energy under grant DE-SC0001293 and grant DE-FG02-07ER46405. The US government may have certain rights in the invention.

BACKGROUND

[0004] Solar cells based on arrays of Si micro- or nanowires have been proposed as a potentially low-cost alternative to conventional wafer-based Si solar cells. See reference [1], incorporated herein by reference in its entirety. [0005] A large-area, solid-state, Si wire-array solar cell requires the formation of a radial or axial p-n junction within each wire. However, the formation or deposition of a monolithic p-n junction across the wire array (as suggested, for example, in reference [2], incorporated herein by reference in its entirety) is prone to shunting, as it provides no electrical isolation between adjacent wires and damaged areas of the array or substrate. Furthermore, a radial junction that extends to the bottom of each wire would greatly complicate the formation of backside electrical contacts to a polymer-embedded, peeled-off wire array. This is because a non-selective contact to the bottom of each wire would contact both the n- and p-type regions, effectively shunting the junction.

SUMMARY

[0006] According to a first aspect of the disclosure, a method for selectively patterning a three- dimensional structure comprising a plurality of spaced elements is provided, comprising: embedding a portion of the three-dimensional structure with a material filling a space within the elements, the material defining an embedded portion of the three-dimensional structure and an unembedded portion of the three-dimensional structure, thus defining, for each element, an embedded portion of the element and an unembedded portion of the element; and patterning the unembedded portions of the elements, thus selectively patterning the three-dimensional structure.

[0007] According to a second aspect of the disclosure, a method for forming radial and axial junctions in a silicon microscale or nanoscale wire array is provided, comprising: providing a silicon wire array; doping the silicon wire array with a first type of dopant; covering the silicon wire array with oxide to form an oxide covered silicon wire array; applying a polymer to the oxide covered silicon wire array; forming on each wire a first region where the wire is covered with the oxide and the polymer, and a second region where the wire and oxide are exposed; removing the exposed oxide from the second region without removing the polymer protected oxide from the first region; removing the polymer; and doping the second regions of the silicon wire array with a second type of dopant different from the first type of dopant, forming radial junctions between the first type of dopant in the second region and the second type of dopant in the second region of the wires.

[0008] According to a third aspect of the disclosure, a silicon microscale or nanoscale wire solar cell is provided, comprising: a plurality of aligned microscale or nanoscale wires embedded into polymer; a plurality of light scattering particles embedded into the polymer between the wires; a first contact; and a second contact, the second contact acting as a back reflector.

[0009] Further embodiments of the disclosure are provided in the specification, drawings and claims of the present application.

[0010] Appendix 1, Appendix 2, and Appendix 3 are filed together with the present application and form integral part of the specification of the present application.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]

FIGURE 1 shows a schematic partial cross sectional view of photolithographically patterned catalyst particles prior to growth.

FIGURE 2 shows a schematic partial cross sectional view of a microscale or nanoscale wire array following VLS (vapor-liquid-solid) growth, catalyst removal, and thermal-oxide diffusion- barrier formation.

FIGURE 3 shows a schematic partial cross sectional view of wire array after formation of a PDMS (polydimethylsiloxane) mask layer and selective removal of a thermal oxide diffusion barrier. FIGURE 4 shows a schematic partial cross sectional view of wire array following selective p-n junction diffusion. The height of the diffusion-barrier determines the extent of axial (masked) vs. radial (unmasked) junction formation. Independent p-n junctions within each wire of the array are formed.

FIGURES 5A and 5B show perspective and cross sectional views of a single-wire solar cell device.

FIGURE 6 shows a perspective view of a solar cell device according to a further embodiment of the present disclosure.

FIGURES 7A-7E show patterning steps according to an embodiment of the disclosure.

FIGURE 8 shows a scanning electron microscope (SEM) image of a plurality of coated Si wires with an exposed Si top portion.

DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure are directed to a three-dimensional (3-D) non- photolithographic patterning method that utilizes a polymeric infill (e.g. PDMS infill) of a 3-D microstructure (e.g. semiconductor wire arrays) in conjunction with etching and/or deposition steps to pattern the 3-D microstructure.

[0013] By way of example, this method can be used to form radial p-n junctions in Si micro- wires for photovoltaic applications as shown in FIGURES 1-4.

[0014] FIGURES 1-2 show wire growth by a photolithographically patterned VLS technique, as described in reference [3], incorporated herein by reference in its entirety. [0015] A wire array is initially defined. FIGURE 1 shows photolithographically patterned catalyst particles prior to growth. A photolithographically patterned hole array (110) covered by buffer oxide (120) contains a plurality of holes where catalyst particles (e.g., Cu particles) (130) are located. The patterned hole array (110) is located on a substrate (140), e.g. a p+ Si <111> wafer.

[0016] Wire array growth and processing is then performed. FIGURE 2 shows a wire array after catalyst removal (by using, e.g., a chemical etch), where p-type doping (210) can be achieved in- situ by the introduction of BCI3 during growth (see reference [4], incorporated herein by reference in its entirety) and where thermal oxidation is performed to form a conformal phosphorus diffusion barrier (220) (e.g., a 200 nm thick S1O2 layer) around the wire and substrate surfaces. In case n-doping is desired, PH ₃ can be flown instead of BC1 ₃ .

[0017] With reference now to FIGURE 3, a polymer, e.g. PDMS, is then applied to the wire array. For example, PDMS can be diluted with a low-boiling-point solution of hexamethyltrisiloxane dissolved in dichloromethane and applied to the wire array by spin coating. The controlled evaporation of the low-boiling-point solution results in a uniform contraction of the PDMS infill, yielding a polymer layer (310) at the base of the array, as shown in FIGURE 3, e.g. a roughly 15 μηι-thick layer after curing at 120 °C.

[0018] The thickness of mask layer (310) can be varied by adjusting the ratio of PDMS to the low-boiling-point solution, or by sequential application and curing of diluted PDMS layers. Control of the thickness of the mask layer (310) allows control of the height of the conformal thermal oxide coating after chemical etching (i.e., the phosphorous diffusion barrier in the example at issue). [0019] In order to remove any residual polymer from the wire sidewalls above the mask layer (310), the wire array is etched. For example, a 2 second etch of 1 : 1 dimethylformamide (DMF) : tetrabutylammonium fluoride (TBAF) can be used.

[0020] The thermal oxide (220) not covered by the polymer mask (310) is then removed, e.g. chemically removed using buffered hydrofluoric acid (BHF), selectively exposing Si surfaces (320) at the top and sides of each wire. The cured mask layer (310) prevents the etching of the oxide at the bases of the wires.

[0021] The polymer mask layer (310) is then removed. Such removal can be obtained, for example, by etching in a PDMS etch, 3:1 DMF : TBAF for 10-30 minutes. The wire array can then be etched to remove residual organic contaminants, for example in 1 :1 sulfuric acid:hydrogen peroxide for 1-5 minutes. Native oxide from the exposed Si surfaces can also be removed, for example by etching in 10% HF for 10 seconds.

[0022] N-type regions (410), e.g. emitter regions, beneath the non-masked areas of the wire sidewalls are produced, as shown in FIGURE 4. These regions can be produced, for example, by way of a thermal phosphorous diffusion at 850 °C for 5 minutes. The thermal oxide (e.g., S1O2) functions as a phosphorous diffusion barrier for the lower region of the wires. The temperature and duration of the diffusion step can be adjusted, if desired, to achieve a desired doping profile and junction depth. In order to remove diffusion glass from the wire sidewalls while leaving the oxide diffusion barrier intact, a 10 second buffered HF etch can be performed. Should p-type regions be produced on n-doped silicon wires, they can be produced by diffusing B (boron) into the Si wires from BN (Boron Nitride) source wafers.

[0023] As shown in FIGURE 4, both radial junctions (420) and quasi-axial junctions (430) are formed. Therefore, radial, axial and/or a combination of radial and axial p-n or n-p junctions can be used with such arrangement. [0024] Formation of metal contacts with the wires formed in accordance with the above described method can be obtained by using, for example, the photolithographically aligned metallization technique described in reference [4].

[0025] FIGURE 5 A shows a perspective view of a wire (510) formed in accordance with the above described method, connected to ohmic contacts (520). The ohmic contacts can be achieved using evaporated Al, with Ag evaporated onto the Al to supplement the total metal thickness, and to allow wire bonding to the contact pads.

[0026] A more detailed view of the arrangement of FIGURE 5A is shown in the cross sectional view of FIGURE 5B, where the diffused emitter (530), the thermal oxide (540), and the Si core (550) are shown. If region (530) is an n-type region then the Si core (550) is a p-type Si core and vice versa.

[0027] While FIGURES 5A and 5B show a single contact (520) to either end of the wire, a plurality of contacts can be provided, if desired, to each end.

[0028] The arrangement of FIGURES 5A and 5B can be used to form a single wire solar cell. In this respect, FIGURE 5B shows an antireflection (AR) Si ₃ N ₄ layer (560) on top of a substrate (570), e.g. an n+ Si substrate.

[0029] The I-V characteristics of the single-wire device are described in Figures 12 and 13 and related portions of the specification of the US provisional application 61/265,297 to which the present application claims priority, and are incorporated herein by reference.

[0030] Surface passivation on the wires obtained according to the method of the present disclosure can be achieved using conformally deposited a-Si:H to decrease surface recombination at the wire sidewalls. Surface passivation prevents photo-excited carriers from recombining at the wire surface, thereby allowing the photo-excited carriers to travel to the metal contacts where they can be used to perform an electrical function.

[0031] Wires are first etched for 7 minutes in BHF to remove all surface oxide, then loaded into a plasma-enhanced chemical vapor deposition (PECVD) chamber for deposition of an about 10 nm-thick layer of nominally undoped a-Si:H on the wire sidewalls.

[0032] Further observation, verification and results of surface passivation are described in Figures 14 and 1 and the section 'Surface passivation' of the specification of the US provisional application 61/265,297 to which the present application claims priority, and are incorporated herein by reference.

[0033] As already mentioned in the introductory paragraph of the present application, the present application is also related to US Patent Application S/N for "Semiconductor

Wire Array Structures, and Solar Cells and Photodetectors Based on such Structures" filed on even date herewith, Attorney Docket Number P708-US, incorporated herein by reference in its entirety, and claiming priority to the same US provisional applications of the present application.

US Patent Application S/N describes solar cells and photodetectors comprised of a wire array with anti-reflective coatings on the wire surfaces, light scattering AI2O3 particles within the wire array and a back reflector behind the wire array.

[0034] FIGURE 6 of the present application describes an embodiment where the teachings of the present disclosure are combined with the teachings of US Patent Application S/N

. In particular, shown in FIGURE 6 is a Si wire array solar cell (600) with a transparent top contact (610) (e.g. an indium tin oxide (ITO) contact) and a metallic bottom contact (620) acting as a back reflector. Solar cell (600) is embedded into a polymer encasing or environment (630), e.g. a flexible transparent polymer such as PDMS. Light scattering particles (640) (e.g., AI2O3 particles) are embedded inside the environment (630). The solar cell (600) further comprises an array of mechanically flexible vertically aligned wires (650) as previously shown in FIGURE 4. The wires (650) are coated with a surface passivation antireflective coating (660).

[0035] If desired, both contacts can be placed at the bottom of the solar cell, with one of the acting as a back reflector.

[0036] While some of the above embodiments have described methods to form radial p-n junctions in Si microscale or nanoscale wires, further embodiments applying the teachings of the present disclosure can be provided.

[0037] FIGURES 7A-7E show a further example of a patterning method according to the present disclosure. In particular, FIGURE 7A shows a 3-D micro- or nanostructure (700). As shown in FIGURE 7B, a polymer (e.g. PDMS) (710) is used to protect or isolate a portion of the 3-D microstructure, in this case the base of the wire array. A material (e.g. Al) (720) is then deposed on the portion of the 3-D micro- or nanostructure not isolated by the polymer (710), as shown in FIGURE 7C. Therefore, the presence of the polymer layer (710) allows selective deposition of the material (720) on the 3-D structure (700). A further layer of polymer (730) is then placed as shown in FIGURES 7D and 7E, and then a chemical etch is used to selectively remove the material (740) (Al in the example of the figure) from the portion of the structure above the second layer of polymer (730), thus allowing a desired patterning of the structure (700).

[0038] In addition to not suffering the small parasitic absorption losses of a transparent top contact, the embedded Al contact is likely to be a more robust and flexible contact and serves the additional role of a metallic back reflector. [0039] According to a further embodiment of the present disclosure, the patterning method can also be used to produce selective openings in dielectric (electrically insulating) passivation and/or anti-reflection layers on Si wires in order to allow for electrical contacting of the Si wires. In other words, a 3-D structure of Si wires coated with passivation and/or anti-reflection layers is initially provided. A layer of thermoplastic wax is then deposited on a bottom portion of the coated Si wires, similarly to what was previously shown in FIGURE 7B, leaving a top portion of the coated Si wires exposed. Selective deposition of the thermoplastic wax can occur, for example, by melting the wax into the wire array and then etching the wax to the desired height using an oxygen plasma. In a further step, the passivation and/or anti-reflective layer is then etched away from the top portion, thus allowing contact opening through selective chemical etching.

[0040] FIGURE 8 shows a scanning electron microscope (SEM) image of a plurality of (a- SiN _x :H) coated Si wires (810) with an exposed Si top portion (820). Such embodiment can be useful for wire-array solar cells, which usually are not able to survive the high-temperature (> 500 °C) conditions currently used for contact fire-through.

[0041] According to further embodiments of the disclosure, the patterning can comprise application of a functional coating (e.g., a methyl termination), depositing a semiconductor (e.g., amorphous silicon), and/or depositing an insulator (e.g., silicon nitride) on the top portion of the wires. The patterning can also comprise, if desired, adding a functional element to the space between the top regions or portions of the wires. By way of example, dielectric scattering particles can be added, followed by an infilling with polymer and inversion of the structure, in order to obtain a polymer embedded Si wire array with dielectric scattering particles located only at a base of the wire array. Such structure would minimize or eliminate reflection losses that would occur if dielectric scattering particles were located at the top of the wire array. [0042] The examples set forth above are provided to give those of ordinary skill in the art a complete disclosure and description of how to make and use the embodiments of the selective p- n junction fabrication for semiconductor microstructures and related methods and devices of the disclosure, and are not intended to limit the scope of what the inventors regard as their disclosure. Modifications of the above-described modes for carrying out the disclosure may be used by persons of skill in the art, and are intended to be within the scope of the following claims. For example, the person skilled in the art will understand, upon reading of the present disclosure, that any type of three-dimensional structure is suited to undergo the steps of the method according to the present disclosure. All patents and publications mentioned in the specification may be indicative of the levels of skill of those skilled in the art to which the disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference had been incorporated by reference in its entirety individually.

[0043] It is to be understood that the disclosure is not limited to particular methods or systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. The term "plurality" includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.

[0044] A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims. LIST OF CITED REFERENCES

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