BACKGROUND

[0001] Majority of the electronic computation today is carried out in Boolean logic in digital computers and electronics. Boolean logic is a form of algebra in which all values are reduced to either TRUE (1) or FALSE (0). Boolean logic gates have scaled following the Moore's law as transistor gate lengths have scaled (e.g., to 20 nanometers (nm)). Some limitations to Boolean logic are: limited density of logic gates limited by algebraic constrains in two-level logic (Galois field-2 algebra); limited density of interconnect bandwidth limited by the number representation in base-2 number system; and limited density of memory states limited by the information content per bit. One way to solve the limited density of memory states is to use quaternary or six-state magnets.

[0002] The logic units resulting from such magnets may use three-dimensional (3D) interconnect. To provide a 3D configuration of logic devices, Complementary Metal Oxide Semiconductor (CMOS) structures are built up on a semiconductor device layer supported by a wafer, and bond different such wafers together to achieve the three-dimensional structure. However, wafer-bonding is an expensive process, and offers only a limited number of bonded connections. Such regular metal interconnects and vias are not suitable for spin logic that is implemented within die and when one or more spin logic are stacked on different layers on die.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1 illustrates a plot showing magnetic crystalline energy of a four or quaternary state (4-state) magnet and corresponding 4-state magnet used for three- dimensional (3D) spin torque logic, in accordance with some embodiments of the disclosure.

[0005] Fig. 2 illustrates a plot showing magnetic crystalline energy of a six state (6- state) magnet and corresponding 6-state magnet used for 3D spin torque logic, in accordance with some embodiments of the disclosure.

l [0006] Fig. 3 illustrates a cross-section of a 3D spin torque logic comprising multiple layers of spin logic with vector spin vias to carry information between the layers, according to some embodiments of the disclosure.

[0007] Fig. 4 illustrates a cross-section of a 3D spin torque logic comprising multiple layers of spin logic with supper lattices to carry information between the layers via exchange coupling, according to some embodiments of the disclosure.

[0008] Fig. 5 illustrates a cross-section of a 3D spin torque logic comprising multiple layers of spin logic with nanopillar magnet to carry information between the layers via domain wall propagation, according to some embodiments of the disclosure.

[0009] Fig. 6 illustrates a cross-section of a 3D spin torque logic comprising multiple layers of spin logic with carbon nanotube spin vias to carry information between the layers, according to some embodiments of the disclosure.

[0010] Fig. 7 illustrates a cross-section of a 3D spin torque logic comprising multiple layers of spin logic with wrapped around graphene spin vias to carry information between the layers, according to some embodiments of the disclosure.

[0011] Fig. 8 illustrates flowchart of a method forming a spin logic that uses 3D vias, according to some embodiments of the disclosure.

[0012] Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with 3D spin logic with vector spin vias, according to some embodiments.

DETAILED DESCRIPTION

[0013] Stacking spin logic and 3D interconnects for spin logic may be needed for quaternary and six state based spin logic devices because continued increase in device density (e.g., devices per unit area) may require the adoption of 3D stacking for spin logic. This is due to magnetic stability being related to the size of the nanomagnets. Further reduction in the energy per bit of the spin logic pushes for higher density of devices to be packed in a given volume. Adoption of 3D stacking for spin logic may also be because all metallic logic is amenable to higher heat extraction due to excellent thermal contacts. However, there are barriers to 3D spin logic. These barriers are primarily due to inefficient spin diffusion in a scaled 3D via, and due to spin diffusion across traditional via barrier layers.

[0014] Various embodiments enable 3D integration of spin logic (e.g., 2 state, 4 state, and/or 6 state magnet based spin logic devices). In some embodiments, the 4-state logic has four uniquely defined logic states. In some embodiments, the four states are separated by high energy barrier (e.g., 40 kT or 60 kT) to provide low error rate operation, where 'k' is Boltzmann constant and ' is temperature. As such, the 4-state magnet has twice as high storage density per magnetic recording layer area than a magnet formed of traditional 2-state magnets. In some embodiments, 6-State logic has six uniquely defined logic states. In some embodiments, the six states magnetic states are separated by high energy barrier (e.g., 20 kT, 40 kT, or 60 kT) to provide low error rate operation. In some embodiments, the energy barrier is greater than or at least 10 kT.

[0015] In some embodiments, 3D spin torque logic is provided which comprises of multiple layers of spin logic with spin vias to carry the information between the layers. In some embodiments, the 3D multi-valued logic comprises of 4 or 6 state logic formed with 4 or 6 stable state magnetic elements. In some embodiments, the 3D integration of spin logic comprises of layers of interconnected spin logic with independent or shared power, clocking and ground layers. In some embodiments, the spin signal is carried between the layers using spin currents flowing in spin vias formed with high spin diffusion length materials.

[0016] Some embodiments describe 3D spin torque logic comprising of multiple layers of spin logic with drift assisted spin vias to carry the information between the layers. In one such embodiment, out-of-plane spin currents are assisted with a drift field to increase the spin flow out of plane. In some embodiments, drift assist voltage is provided on a separate voltage rail.

[0017] Some embodiments describe 3D spin torque logic which comprises of multiple layers of spin logic with exchange coupled magnetic vias to carry the information between the layers. In one such embodiment, the ferromagnetic state is carried between the layers using exchange coupled super lattices of ferromagnets.

[0018] In some embodiments, 3D spin torque logic is provided which comprises of multiple layers of spin logic with ferromagnetic nanopillar vias. In one such embodiment, the ferromagnetic state is carried between the layers using intrinsic ferromagnetic exchange.

[0019] In some embodiments, 3D spin torque logic is provided which comprises of multiple layers of spin logic with Carbon Nanotubes (CNT) nanopillar vias. In one such embodiment, the ferromagnetic state is carried between the layers via a CNT array.

[0020] In some embodiments, 3D spin torque logic is provided which comprises of multiple layers of spin logic with wrapped around graphene via. In one such embodiment, the ferromagnetic state is carried between the layers wrap around graphene sheets forming the cladding of the spin via.

[0021] There are many technical effects of various embodiments. For example, stackable 2-state, 4-state, or 6-state stable logic is enabled using the 3D vias of various embodiments. These 3D vias can enable multi -value storage/memory elements to enable very high density memory. The 3D vias enable multi-value logic elements to enable very high logic circuit efficiency. The 3D vias also enable multi-value interconnects to provide high interconnect density per pitch. Other technical effects will be evident from the various embodiments and figures.

[0022] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0023] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0024] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0025] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0026] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0027] Fig. 1 illustrates plot 100 showing magnetic crystalline energy of a four or quaternary state (4-state) magnet and corresponding 4-state magnet used for three- dimensional (3D) spin torque logic, in accordance with some embodiments of the disclosure.

[0028] Here, the x-axis is angle in degrees, and the y-axis is Energy in kT (where 'k' is Boltzmann constant and ' is temperature). Plot 100 illustrates two waveforms— 102 and 103. Waveform 102 illustrates the thermal energy separation or barrier between four magnetic orientations of 4-state magnet 104. In some embodiments, 4-state magnet 104 is formed of a material such that the four magnetic orientations are separated by 40 kT of thermal energy barrier as illustrated by waveform 102. Waveform 103 is similar to waveform 102 except the thermal energy separation between the four magnetic orientations is 60 kT. In some embodiments, the 4-state magnetic recording media has four uniquely defined memory states.

[0029] In some embodiments, the four orientations are defined for the 4-state logic memory element such that orientations '0' and T are separated by 90 degrees, orientations T and '3' are separated by 90 degrees, orientations '3' and '2' are separated by 90 degrees, orientations '0' and '3' are separated by 180 degrees, and orientations T and '2' are separated by 180 degrees. In some embodiments, with reference to a four quadrant 2D vector space, magnetic orientation facing +x direction (e.g., East) is orientation 'Ο'; magnetic orientation facing +y direction (e.g., North) is orientation T, magnetic orientation facing -x direction (e.g., West) is orientation '3', and magnetic orientation facing -y direction (e.g., South) is orientation '2'.

[0030] In some embodiments, 4-state magnet 104 is formed using cubic magnetic crystalline anisotropy magnets. In some embodiments, 4-state magnet 104 is formed by combining shape and exchange coupling to create two equal easy axes for nanomagnets. In some embodiments, 4-state magnet 104 comprises of a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, and Heusler alloys of the form X2YZ. In some embodiments, the magnetic insulators comprises of a material selected from a group consisting of: magnetite Fe ₃ 0 ₄ and Y3AI5O12. In some embodiments, the Heusler alloys comprises of one of: Co ₂ FeSi and MmGa.

[0031] In some embodiments, 4-state magnet 104 is formed with high spin polarization materials. Heusler alloys are an example of high spin polarization materials. Heusler alloys are ferromagnetic metal alloys based on Heusler phase. Heusler phases are intermetallic phases with particular composition and face-centered cubic (FCC) crystal structure. Heusler alloys are ferromagnetic because of double-exchange mechanism between neighboring magnetic ions. The neighboring magnetic ions are usually manganese ions, which sit at the body centers of the cubic structure and carry most of the magnetic moment of the alloy.

[0032] In some embodiments, Heusler alloys such as Co2FeAl and Co2FeGeGa are used for forming 4-state magnet 104. Other examples of Heusler alloys include: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa, Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Fe ₂ Val, Mn ₂ VGa, Co ₂ FeGe, etc.

[0033] In some embodiments, 4-state magnet 104 is formed with a sufficiently high anisotropy (Hk) and sufficiently low magnetic saturation (M _s ) to increase injection of spin currents. For example, Heusler alloys of high Hk and low M _s are used to form 4-state magnet 404.

[0034] Magnetic saturation Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material (i.e., total magnetic flux density B substantially levels off). Here, sufficiently low M _s refers to M _s less than 200 kA/m (kilo- Amperes per meter). Anisotropy Hk generally refers to the material property which is directionally dependent. Materials with Hk are materials with material properties that are highly directionally dependent. Here, sufficiently high Hk in context of Heusler alloys is considered to be greater than 2000 Oe (Oersted). For example, a half metal that does not have bandgap in spin up states but does have bandgap in spin down states (e.g., at the energies within the bandgap, the material has 100% spin up electrons). If the Fermi level of the material is in the bandgap, injected electrons will be close to 100% spin polarized. In this context, "spin up" generally refers to the positive direction of

magnetization, and "spin down" generally refers to the negative direction of magnetization. Variations of the magnetization direction (e.g. due to thermal fluctuations) result in mixing of spin polarizations. [0035]

[0036] Fig. 2 illustrates a plot showing magnetic crystalline energy of a six state (6- state) magnet and corresponding 6-state magnet used for 3D spin torque logic, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0037] In some embodiments, the 6-state magnet has six uniquely defined memory states. For plot 201a, the x-axis is in-plane angle in degrees, and the y-axis is Energy in kT (where 'k' is Boltzmann constant and 'T' is temperature). Plot 201a illustrates two waveforms— 202 and 203. Waveforms 202 and 203 illustrate the thermal energy separation or barrier between four in-plane magnetic orientations of the 6-State magnet 207, where waveform 202 has a barrier separation of 40 kT and waveform 203 has a barrier separation of 60 kT. A side-view of 6-State magnet 207 is illustrated as a stack of layers 209, in accordance with some embodiments. The stack of layers 209 are also referred to as side-view 209.

[0038] The other two magnetic orientations of the 6-State magnet 207 are out-of- plane as shown by plot 201b. For plot 201b, the x-axis is out-of-plane angle in degrees, and the y-axis is Energy in kT. Plot 201b illustrates three waveforms— 204, 205, and 206.

Waveforms 204, 205, and 206 illustrates the thermal energy separation or barrier between two out-of-plane magnetic orientations of the 6-state magnet 207, where waveform 204 has a barrier separation of 20 kT, waveform 205 has a barrier separation of 40 kT, and waveform 206 has a barrier separation of 60 kT. While the embodiments described here assume a barrier separation of 40 kT, materials and shape anisotropy for 6-State magnet 207 can be selected to have other barrier separations which are large enough to provide zero error rate between states. For example, the energy barrier can be greater than or at least 10 kT.

[0039] In some embodiments, the six orientations are defined for the 6-State logic memory element such that orientations '0' and T are separated by 90 degrees, orientations T and '3' are separated by 90 degrees, orientations '3' and '2' are separated by 90 degrees, orientations '0' and '3' are separated by 180 degrees, orientations T and '2' are separated by 180 degrees, orientations '0' and '4', '4' and Ί ', '4' and '3', and '4' and '2' are separated by 90 degrees each, orientations '5' and 'Ο', '5' and '2', '5' and '3', and '5' and T, are separated by 90 degrees each, and orientations '5' and '4' are separated by 180 degrees.

[0040] In some embodiments, with reference to an eight quadrant three dimensional

(3D) vector space, magnetic orientation facing +x direction (e.g., East) is orientation 'Ο'; magnetic orientation facing +y direction (e.g., North) is orientation T, magnetic orientation facing -x direction (e.g., West) is orientation '3', magnetic orientation facing -y direction (e.g., South) is orientation '2', magnetic orientation facing -z direction is orientation '4', and magnetic orientation facing +z direction is orientation '5. '

[0041] In some embodiments, 6-State magnet 207 is formed using cubic magnetic crystalline anisotropy magnets. In some embodiments, 6-State magnet 207 is formed using shape, crystalline and strain assisted magnetization. One such example is illustrated as a side view 209 of top view of 6-State magnet 207. In the side view 209, 6-State magnet is formed by combining a magnetostrictive (MS) ferromagnet (FM) 207a with a piezo-electric (PZe) layer 208. MS FM 207a is formed of ferromagnetic materials that causes the materials to change their shape or dimensions during the process of magnetization.

[0042] PZe layer 208 causes piezo-electric effect in magnetostrictive ferromagnet

(FM) 507a when a voltage is applied to PZe layer 208. The applied voltage across PZe layer 208 causes change in the magnetic field in MS FM 207a and so it stresses magnetostrictive FM 207a. The stress in turn causes magnetostrictive FM 207a to have six magnetic states. In some embodiments, magnetostrictive FM 207a is formed of any one of the materials:

Terfenol-D (an alloy of the formula Tb _x Dyi- _x Fe2 (x ~ 0.3)), galfenol (an alloy of iron and gallium), amorphous alloy Fe8iSi3.5B13.5C2, or Ni.

[0043] In some embodiments, PZe layer 208 is formed of any one of the materials:

Barium titanate (BaTi03), Lead zirconate titanate (PZT), Potassium niobate (KNb03), Sodium tungstate (Na2W03), Ba2NaNb505, Pb2KNb50i5, Zinc oxide (ZnO)-Wurtzite structure, Sodium potassium niobate ((K,Na)Nb03) (or NKN), Bismuth ferrite (BiFe03), Sodium niobate NaNb03, Bismuth titanate Βΐ4Τΐ3θΐ2, Sodium bismuth titanate Nao.5Bio.5Ti03, any bulk or nanostructured semiconductor crystal having non central symmetry, such as the Group III-V and II-VI materials, Polyvinylidene fluoride (PVDF), diphenylalanine peptide nanotubes (PNTs), etc.

[0044] In some embodiments, 6-State magnet 207 is formed using shape, exchange coupling and strain assisted magnetization. In some embodiments, 6-State magnet 207 is formed using in-plane bi-axial anisotropy and strain assisted magnetization. In some embodiments, 6-State magnet 207 is formed using tri-axial anisotropy magnet.

[0045] In some embodiments, 6-State magnet 207 is formed of a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, andHeusler alloys of the form X2YZ. In some embodiments, the magnetic insulators are formed of a material selected from a group consisting of: magnetite Fe ₃ 0 ₄ and Y3AI5O12. In some embodiments, the Heusler alloys is one of: Co ₂ FeSi and MmGa.

[0046] In some embodiments, 6-State magnet 207 is formed with high spin polarization materials. Heusler alloys are an example of high spin polarization materials. In some embodiments, 6-State magnet 207 is formed with a sufficiently high Hk and sufficiently low Ms to increase injection of spin currents. For example, Heusler alloys of high Hk and low Ms are used to form 6-State magnet 207. In some embodiments, Heusler alloys such as Co2FeAl and Co2FeGeGa are used for forming 6-state magnet 207. Other examples of Heusler alloys include: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa, Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Fe ₂ Val, Mn ₂ VGa, Co ₂ FeGe, etc.

[0047] Fig. 3 illustrates cross-section 300 of a 3D spin torque logic comprising multiple layers of spin logic with spin vias to carry information between the layers, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0048] The 3D spin torque logic of Fig. 3 is a sample logic to illustrate the structure and function of the 3D vias for carrying information between two vertical layers. The same concepts can be extended to any number of layers and spin torque logic. Here, cross- sectional view 300 of a 3D spin torque logic comprises a first layer of spin channels 301a, 301b, and 301c, second layer of spin channels 301d, 301e, and 301f; oxide barriers 302a, 302b, 302c, and 302d; magnets 303a, 303b, 303c, and 303d; non-magnetic conductor 304 (e.g., to provide a ground plane); shared supply or ground vias 305a, 305b, and 305c; nonmagnetic conductors 306a and 306b; non-magnetic conductor 307 (e.g., to provide supply voltage plane); interlay er vias 308a and 308b, oxide region 309, and shared supply/ground plane 310. Here, for sake of simplicity, when a property for an identifier is the same, it may be referred to by its identifying number without the following letter. For example, 3D interlay er vias 308a and 308b can be referred to as via 308.

[0049] In some embodiments, the material(s) used for forming non-magnetic metal conductors 301, 304, 305, 306, 307, and 308 is/are the same. For example, Copper (Cu) can be used for forming metal layers non-magnetic metal conductors 301, 304, 305, 306, 307, and 308. Other material examples are Ag, Al, Au, and similar non-magnetic conductors. In other embodiments, material(s) used for forming conductors 204, 305, 306, 307, channel 301, and via 305 are different. For example, non-magnetic metal conductors 301, 304, 305, 306, 307 may be formed of Cu while via 308 may be formed of graphene. Any suitable metal or combination of metals can be used for forming metal layers 301 , 304, 305, 306, 307, and 308. For example, spin Channel 301 can be formed of Silver (Ag), Aluminum (Al), Graphene, and other two-dimensional (2D) conducting materials. In some embodiments, the 2D conducting materials are selected from a group consisting of: graphene, M0S2, MoSe2, WS2, and \VSe2.

[0050] In some embodiments, magnets 303a/b/c/d are one of 2-state, 4-state, or 6- state free magnets. The term "free magnet" here generally refers to a magnet whose magnetization is not fixed or predetermined, and can be modified by an external stimulus such as spin torque. A 2-state magnet can have two possible magnetization directions (e.g., +/- x or +/- y directions). In some embodiments, magnets 303 are formed using cubic magnetic crystalline anisotropy magnets. In some embodiments, magnets 303 are formed by combining shape and exchange coupling to create two equal easy axes for a nanomagnets. In some embodiments, magnets 303 may be hybrid magnets. For example, magnet 302a may be a 4-state magnet such as that described with reference to Fig. 1, while magnet 303c is a 6- state magnet such as that described with reference to Fig. 2.

[0051] Referring back to Fig. 3, in some embodiments, first spin channel (on the first layer) is partitioned into segments or regions 301a, 301b, and 301 c such that oxide regions 302a and 302b form a barrier between the channel segments. In some embodiments, second spin channel (on the second layer above the first layer) is partitioned into segments or regions 301d, 301 e, and 301f such that oxide regions 302c and 30db form a barrier between the channel segments. One purpose of the barrier is to control the transfer of spin to charge. The magnets are positioned between the spin channel gaps or segments, in accordance with some embodiments. In this example, magnet 303a is positioned over oxide barrier 302a such that it couples channel segment 301 a with channel segment 301b; magnet 303b is positioned over oxide barrier 302b such that it couples channel segment 301b with channel segment 301b; magnet 303c is positioned over oxide barrier 302c such that it couples channel segment 30 I d with channel segment 301 e; and magnet 303d is positioned over oxide barrier 302d such that it couples channel segment 301 e with channel segment 301f.

[0052] In some embodiments, non-magnetic metal layer is deposited over the magnets to form magnet contacts. These non-magnetic metal layers can provide input, output, or bias contacts to the magnets. For example, non-magnetic metal layer 306a is coupled to magnet 303a; non-magnetic metal layer 306b is coupled to magnet 303b, and nonmagnetic metal layer 307 is coupled to magnets 303c and 303d. In this example, nonmagnetic metal layers 306a and 306b may provide input to spin torque logic while non- magnetic layer 307 provides a switching supply to magnets 303c and 303d. Here, the term "switching supply" generally refers to a power supply or ground supply which is not constant but provided according to a switching clock signal. For example, one or more transistors (e.g., p-type transistors) are coupled to non-magnetic layer 307 and controllable by a clock signal provided to its gate terminal, while the source/drain terminal of the p-type transistor is coupled to a power supply or ground and the drain/source terminal of the p-type transistor is coupled to non-magnetic metal layer 307. Here, the gaps indicated by 309 can be filed with an insulating material such as silicon oxide, MgO, etc.

[0053] In some embodiments, via hole(s) are etched in oxide 309 to couple ground plane 304 to channel section 301b. The via hole is then filled with a conducting metal to form via 305a. The same process can be used for forming vias 305b and 305c that couple channel sections 301e and 301f, respectively, to a shared supply or ground plane 310, in accordance with some embodiments.

[0054] While the embodiments here illustrate the magnets being formed above the spin channel segments, these magnets can be formed below the spin channel segments. In one such embodiment, the oxide barriers are formed by etching the spin channel to form the spin channel segments.

[0055] In some embodiments, filter layers (not shown) are sandwiched between the magnets and the channel regions. For example, a filter layer (not shown) is sandwiched between 4-state magnet 303a and channel regions 301a and 301b. As such, unlike the case where magnets are directly coupled or adjacent to the portions of channel regions (or segments), the magnets are coupled to or adjacent to their respective filter layers. In some embodiments, the filter layers comprises of a material selected from a group consisting of: MgO, AI2O3, BN, MgAl ₂ 0 ₄ , ZnAl ₂ 0 ₄ , SiMg ₂ 0 ₄ , and SiZn ₂ 0 ₄ , and NiFeO. One purpose of the filter layers is to provide high tunneling magnetoresistance, for example.

[0056] In some embodiments, engineered interfaces (not shown) are formed between magnets and the spin channels. For example, an engineered interface layer (not shown) is sandwiched between 4-state magnet 303a and channel regions 301a and 301b. As mentioned here, the magnets can be 4-state or 6-state magnets. However, the embodiments are applicable to 2-state magnets also. As such, unlike the case where magnets are directly coupled or adjacent to the portions of channel regions (or segments), the magnets are coupled to or adjacent to their respective engineered interface layers. In some embodiments, the engineered interfaces are formed of non-magnetic material(s) such that the interface layers and the magnets together have sufficiently matched atomistic crystalline layers. For example, the non-magnetic material has a crystal periodicity which is matched through rotation or by mixing of elements.

[0057] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (e.g., the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For instance, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (e.g., matching gets closer to perfect matching), spin injection efficiency from spin transfer from 4- state magnet 303 to spin channel 301 increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device. In some embodiments, the non-magnetic material is Ag with a crystal lattice constant a=4.05A which is matched to Heusler alloys CFA (i.e., Co ₂ FeAl) and CFGG (i.e., Co ₂ FeGeGa with a=5.737A) provided the direction of the crystal axes is turned by 45 degrees. Then the projection of the lattice constant is expressed as:

As such, the magnetic structure stack (e.g., stack of 303a and the engineered interface layer) allows for interfacial matching of Heusler alloys interfaces with the spin channel. In some embodiments, the stack also allows for templating of the bottom surface of the Heusler alloy.

[0058] In some embodiments, the engineered interface layers (e.g., Ag) provide electrical contact to magnets 303 (e.g., magnets 303a/b/c/d). As such, a template is provided with the right crystal orientation to seed the formation of the Heusler alloy (which may form magnets 303).

[0059] One technical effect of the engineered interface layers (e.g., Ag) between

Heusler alloy based magnets 303 and spin channel 301 is that it provides for higher mechanical barrier to stop or inhibit the inter-diffusion of magnetic species with spin channel 301. In some embodiments, the engineered interface layers maintain high spin injection at the interface between spin channel 301 and magnets 303. As such, engineered interface layers improve the performance of the spin logic device. In some embodiments, the fabrication of Heusler alloy and the matching layer is via the use of an in situ processing flow. Here, in situ processing flow refers to a fabricating processing flow that does not break vacuum. [0060] Various embodiments here are described with reference to the magnet being a

4-state magnet. However, the embodiments are also applicable to 2-state and 6-state magnets. In some embodiments, the 4-state Magnet 303a dictates the flow of the spin current in channel 301b. This is realized by the asymmetry of 4-state input magnet 303a overlap with channel 301b. Here, 4-state magnet 303a overlaps more with channel 301b than 301a. For example, overlap 1 is greater than overlap2. This asymmetry in the overlap sets the direction of spin through channel 301b, in accordance with some embodiments.

[0061] In some embodiments, 3D spin vias 308a and 308b are provided to carry spin signals between first channel (e.g., 301 a and 301b) to second channel (e.g., 301e and 301f) using spin current flowing through the 3D spin vias 308a/b comprising high spin diffusion length materials. In this example, via 308a couples channel section 301b with 301 e while via 308b couples channel section 301f with 301 c.

[0062] In some embodiments, when ground supply is provided to metal layer 304 and power supply is provided to metal layer 306a, then a potential difference is developed between layer 304 and layer 306a. This potential difference guides the flow of electrons into channel 301b and results in diffusion of spin polarized electrons injected from magnet 303a towards magnet 303d through channel segment 301b, 3D via 308a and channel segment 301e. Spin torque of spin polarized electrons can switch magnet 303d. In this example, spin current also flows along channel 301b towards magnet 306b and flows along the channel 30 le towards magnet 303c. If subsequently supply voltage is applied to layer 306b, spin current may also make its way into channel 301 c through magnet 303b, in accordance with some embodiments. If subsequently supply voltage is applied to layer 307, and ground voltage is applied to layer 310, spin polarized electrons can be injected by magnet 303d into channel segment 301f and flow through via 308d to channel section 301 c. In some embodiments, when metal planes 307 and 310 are coupled to supply, then spin current from magnet 303c is not inj ected into the channel 30 l e.

[0063] In some embodiments, vias 308a and 308b are formed of high spin diffusion length materials such as copper, silver, or gold. In some embodiments, vias 308a and 308b are formed of the same metal as spin channels (e.g., 301 a-f). For example, vias 308a and 308b are formed of one of Cu, Ag, Au, graphene, or Al.

[0064] In some embodiments, out-of-plane spin currents (e.g., spin currents in the +/- z direction) are assisted with a drift field to increase the spin flow out-of-plane. In some embodiments, supply voltage is applied to layers 306a and 304 and ground is connected to layer 307. Then a potential difference between layers 306a and 304 causes the drift flow of spin polarized currents from magnet 303a through channel 301b, via 308a, channel 301e towards magnets 303d and 303c. Spin torque of the spin polarized electrons can switch magnets 303d and 303c.

[0065] Fig. 4 illustrates cross-section 400 of a 3D spin torque logic comprising multiple layers of spin logic with exchange supper lattices to carry information between the layers using exchange coupling, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 4, differences between Fig. 3 and Fig. 4 are described. In this case, via 305b is removed. In some embodiments, an exchange coupling via 401 is provided which couples magnet 303b to magnet 303d and provides an information exchange path from channel segment 301b to channel segment 301f. Via 401 carries the ferromagnetic state from magnet 303b to 303d (or the other way around) using exchange super lattices in via 401.

[0066] In some embodiments, exchange coupling via 401 comprises a super lattice having alternate layers of metal 402 and ferromagnet 403. For example, exchange coupling via 401 includes metal layer 402a adjacent to or coupled to ferromagnet 403a, metal layer 402b adjacent to or coupled to ferromagnets 403a and 403b, metal layer 402c adjacent to or coupled to ferromagnets 403b and 403c, and metal layer 402d adjacent to or coupled to ferromagnets 403c and 303d. While the embodiment of Fig. 4 illustrates four layers of metal and three layers of magnets forming the exchange coupling via 401, any number of metal layers and magnets can be stacked to form the super lattice of via 401. In some embodiments, exchange layer 403c causes magnetization of e.g. ferromagnets 403b and 403c to be the same. In some embodiments, exchange layer 403c of certain thickness causes magnetization of e.g. ferromagnets 403b and 403c to be opposite, the so-called synthetic anti-ferromagnets (SAF) effect. In some embodiments, depending on the number of layers of metal layers and magnets forming via 401, via 401 can cause magnetizations in 303d and 303b to be opposite, or it can cause magnetizations in 303d and 303b to be the same.

[0067] In some embodiments, the metal layers (e.g., 402a-d) of super lattice 401 are formed of a material selected from a group consisting of: Cu, Ru, Ag, and Pt. In some embodiments, the magnets (e.g., 403a-c) of the super lattice 401 are of the same type and material as magnets 303b and 303d. In some embodiments, magnets (e.g., 403a-c) are 4-state magnets. In some embodiments, magnets (e.g., 403a-c) of super lattice 401 are 6-state magnets. In some embodiments, magnets (e.g., 403a-c) of super lattice 401 comprise Co, Fe, and B. For example, magnets (e.g., 403a-c) of super lattice 401 comprises Co _x FeyB _z , where 'x,' 'y,' and 'z' are fractions of elements in the alloys.

[0068] Fig. 5 illustrates cross-section 500 of a 3D spin torque logic comprising multiple layers of spin logic with domain wall nanopillar magnet to carry information between the layers using domain wall propagation, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 5, differences between Fig. 4 and Fig. 5 are described.

[0069] In some embodiments, via 401 is replaced with via 501a which is a ferromagnetic nanopillar. In some embodiments, via 501a comprises a single layer 4-state or 6-state magnet 501. In some embodiments, the magnet for via 501a is the same magnet as that used for magnets 303b and 303d. For example, magnets 303b and 303d are 4-state magnets and via 501a is formed with 4-state magnet. In some embodiments, ferromagnet 501 is an electrical insulator in order to prevent undesired currents between layers.

[0070] In some embodiments, the thickness t _c of the magnets may determine its magnetization direction. For example, when the thickness of a ferromagnetic layer is above a certain threshold (depending on the material of the magnet, e.g., approximately 1.5 nm for CoFe), then the ferromagnetic layer exhibits magnetization direction which is in-plane.

Likewise, when the thickness of the ferromagnetic layer is below a certain threshold

(depending on the material of the magnet), then the ferromagnetic layer exhibits

magnetization direction which is perpendicular to the plane of the magnetic layer. Other factors may also determine the direction of magnetization.

[0071] For example, factors such as surface anisotropy (depending on the adjacent layers or a multi-layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC (face centered cubic) lattice, BCC (body centered cubic) lattice, or Llo-type of crystals, where Llo is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.

[0072] In some embodiments, ferromagnet nanopillar 501 is formed with multiple layers in a stack. The multiple thin layers can be layers of Cobalt and Platinum (i.e., Co/Pt), for example. Other examples of the multiple thin layers include: Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, MgO; Mn _x Ga _y ; Materials with Llo crystal symmetry; or materials with tetragonal crystal structure. In some embodiments, the perpendicular magnetic layer is formed of a single layer of one or more materials. In some embodiments, the single layer is formed of MnGa. In some embodiments, the perpendicular magnetic layer is formed of one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, YIG (Yttrium iron garnet), or a combination of them.

[0073] Compared the operation of via 401 of Fig. 4, here via 501a uses domain wall propagation as the mechanism for transferring information from magnet 303 a to spin channel 301f. The term "domain wall" generally refers to a propagation mechanism which is an interface separating magnetic domains. Domain wall is a transition between different magnetic moments and usually undertakes an angular displacement of 90° or 180°. A domain wall is a gradual reorientation of individual moments across a finite distance.

[0074] Fig. 6 illustrates cross-section 600 of a 3D spin torque logic comprising multiple layers of spin logic with carbon nanotube spin vias to carry information between the layers, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 6, differences between Fig. 3 and Fig. 6 are described. In some embodiments, via 308a and via 308b are placed with vias 608a and 608b, respectively. In some embodiments, vias 608a and 608b comprise carbon nanotubes (CNT) which are allotropes of carbon with a cylindrical nanostructure. CNTs are also referred to as multi-walled carbon nanotubes. In some embodiments, the structure of a CNT for vias 608a/b can be conceptualized by wrapping a one-atom-thick layer of graphite called graphene into a seamless cylinder. In some embodiments, CNT for vias 608a/b comprise of multiple rolled layers (concentric tubes) of graphene. In some embodiments, CNT for vias 608a/b are graphenated CNTs which combines graphitic foliates grown along the sidewalls of multi-walled or bamboo style CNTs. In some embodiments, CNT for vias 608a/b are nitrogen doped CNTs.

[0075] Fig. 7 illustrates a cross-section 700 of a 3D spin torque logic comprising multiple layers of spin logic with wrapped around graphene spin vias to carry information between the layers, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 7, differences between Fig. 6 and Fig. 7 are described. In some embodiments, via 608a is replaced with via 701 comprising a metal pillar with layers of graphene wrapped around it forming the cladding of the metal nanopillar. In some embodiments, via 701 comprises layers of graphene along the sidewalls 701a with Cu 708 sandwiched between the sidewalls (e.g., Cu 708 forming the core of the via). In some embodiments, the wrapping comprises of M0S2 or other transition metal di-chalcogenides. In some embodiments, the metal nanopillar comprises Al, Ag, or Au. In some embodiments, a thin layer of graphene is also placed at the bottom part 701b of via 701. Forming the sidewalls with graphene mitigates any electro-migration issues caused by via 701.

[0076] The various kinds of 3D vias shown with reference to Figs. 3-7 can be used in the same spin logic device. In some embodiments, all vias do not have to be of the same type. For example, some 3D vias can be CNTs while others can be super lattice based vias.

[0077] Fig. 8 illustrates flowchart 800 of a method forming a spin logic that uses 3D vias, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. The various blocks can be executed in parallel or sequential order. The order of the blocks of flowchart 800 can be altered without changing the essence of the various embodiments.

[0078] At block 801, a first magnet (e.g., 303a) is formed. The first magnet can be one of 2-state, 4-state, or 6-six state magnet as described with reference to various embodiments. At block 802, a first channel (e.g., 301a) is formed adjacent to the first magnet. At block 803, a second channel (e.g., 301b) is formed adjacent to the first magnet such that there is a gap (e.g., 302a) between the first and second channels. At block 804, a second magnet (e.g., 303d) is formed. At block 805, a third channel (e.g., 301e) is formed adjacent to the second magnet. At block 806, a fourth channel (e.g., 301f) is formed adjacent to the second magnet such that there is a gap (e.g., 302d) between the third and fourth channels. At block 807, a 3D via (e.g., 308a) is formed which is coupled to the second and third channels. The 3D via can be according to any one of 3D vias described with reference to Figs. 3-7.

[0079] Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with 3D spin logic with vector spin vias, according to some embodiments. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. [0080] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0081] Fig. 9 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0082] In some embodiments, computing device 1600 includes first processor 1610 and network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0083] In some embodiments, processor 1610 (and/or processor 1690) can include 3D spin logic with vector spin vias and one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. In some embodiments, various other blocks of SoC 1600 can also include 3D spin logic with vector spin vias. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O. [0084] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0085] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0086] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0087] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640. [0088] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0089] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0090] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0091] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0092] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0093] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0094] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0095] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0096] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0097] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0098] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0099] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00100] Example 1 is an apparatus which comprises: a first magnet; a first channel adjacent to the first magnet; a second magnet; a second channel adjacent to the second magnet; and a via coupled to the first and second channels.

[00101] Example 2 includes all features of example 1, wherein at least one of the first and second magnets is one of: a 2-state magnet; a 4-state magnet; or a 6-state magnet.

[00102] Example 3 includes all features of example 1, wherein the first, second, third, and fourth channels comprise Cu. [00103] Example 4 includes all features of example 1 , wherein the via comprises a material which is one of: non-magnetic metal; super lattice comprising alternate layers of magnets and non-magnetic materials; a ferromagnet; a ferromagnetic insulator; carbon nanotubes; or graphene wrapped around non-magnetic metal.

[00104] Example 5 includes all features of example 4, wherein the non-magnetic metal comprises Cu.

[00105] Example 6 includes all features of example 4, wherein the alternate layers of magnets comprises one of: a 2-state magnet; a 4-state magnet; or a 6-state magnet, and wherein the non-magnetic materials of the super lattice comprise Ru.

[00106] Example 7 includes all features of example 4, wherein the non-magnetic metal, which is wrapped by the graphene, comprises Cu.

[00107] Example 8 includes all features of example 1 , wherein the first magnet overlaps the second channel more than it overlaps the first channel.

[00108] Example 9 includes all features of example 1 , wherein the apparatus of example 9 comprises: a first non-magnetic contact adjacent to the first magnet; and a second non-magnetic contact adjacent to the second magnet, wherein the first non-magnetic contact is to provide a signal for propagation through the via, and wherein the second non-magnetic contact is coupled to a transistor which is to provide a switchable power supply.

[00109] Example 10 includes all features of example 2, wherein the 4-state magnet comprises a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, and Heusler alloys of the form X2YZ.

[00110] Example 11 includes all features of example 10, wherein the magnetic insulators comprise a material selected from a group consisting of: magnetite Fe ₃ 0 ₄ and

[00111] Example 12 includes all features of example 10, wherein the Heusler alloys is one of: Co ₂ FeSi or MmGa.

[00112] Example 13 includes all features of example 2, wherein the 4-state magnet is configured to have four stable magnetic states including zero state, first state, second state, and third state, wherein the zero state is to point in a +x-direction, wherein the first state is to point in a +y-direction, wherein the second state is to point in a -y-direction, and wherein the third state is to point in a -x-direction.

[00113] Example 14 includes all features of example 13, wherein a thermal barrier between the zero, first, second, and third states is greater than or equal to 10 kT. [00114] Example 15 includes all features of example 2, wherein the 6-state magnet is configured to have six stable magnetic states including zero state, first state, second state, third state, fourth state, and fifth state, wherein the zero state is to point in a +x-direction, wherein the first state is to point in a +y-direction, wherein the second state is to point in a - y-direction, wherein the third state is to point in a -x-direction, wherein the fourth state is to point in a -z-direction, and wherein the fifth state is to point in a +z-direction.

[00115] Example 16 includes all features of example 15, wherein the 6-state magnet is one of: magnetostrictive ferromagnets adjacent to corresponding piezoelectric layers; tri-axial anisotropy magnets; or in-plane bi-axial anisotropy magnets adjacent to corresponding piezoelectric layers.

[00116] Example 17 includes all features of example 15, wherein a thermal barrier between the zero, first, second, third, fourth, and fifth states is greater than or equal to 10 kT.

[00117] Example 18 includes all features of example 2, wherein the 6-state magnet comprises a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, and Heusler alloys of the form X?YZ.

[00118] Example 19 includes all features of example 18, wherein the magnetic insulators comprises a material selected from a group consisting of: magnetite Fe ₃ 0 ₄ and

Y3AI5O12, and wherein the Heusler alloys is one of: Co ₂ FeSi or M Ga.

[00119] Example 20 is system which comprises: a processor; a memory coupled to the processor, the memory including an apparatus according to any one of apparatus examples 1 to 19; and a wireless interface for allowing the processor to communicate with another device.

[00120] Example 21 is a method which comprises: forming a first magnet; forming a first channel adj acent to the first magnet; forming a second magnet; forming a second channel adjacent to the second magnet; and forming a via coupled to the first and second channels.

[00121] Example 22 includes all features of example 21 , wherein at least one of the first and second magnets is one of: a 2-state magnet; a 4-state magnet; or a 6-state magnet.

[00122] Example 23 includes all features of example 21 , wherein the first, second, third, and fourth channels comprise Cu.

[00123] Example 24 includes all features of example 21 , wherein the via comprises a material which is one of: non-magnetic metal; super lattice comprising alternate layers of magnets and non-magnetic materials; a ferromagnet; a ferromagnetic insulator; carbon nanotubes; or graphene wrapped around non-magnetic metal. [00124] Example 25 includes all features of example 24, wherein the non-magnetic metal comprises Cu.

[00125] Example 26 includes all features of example 24, wherein the alternate layers of magnets comprises one of: a 2-state magnet; a 4-state magnet; or a 6-state magnet, and wherein the non-magnetic materials of the super lattice comprise Ru.

[00126] Example 27 includes all features of example 24, wherein the non-magnetic metal, which is wrapped by the graphene, comprises Cu.

[00127] Example 28 includes all features of example 21 , wherein the first magnet overlaps the second channel more than it overlaps the first channel.

[00128] Example 29 includes all feature of example 21, wherein the method of example 29 which comprises: forming a first non-magnetic contact adjacent to the first magnet; and forming a second non-magnetic contact adjacent to the second magnet, wherein the first non-magnetic contact is to provide a signal for propagation through the via, and wherein the second non-magnetic contact is coupled to a transistor which is to provide a switchable power supply.

[00129] Example 30 includes all features of example 22, wherein the 4-state magnet comprises a material which includes one of: Fe, Ni, Co and their alloys, magnetic insulators, or Heusler alloys of the form X?YZ.

[00130] Example 31 includes all features of example 30, wherein forming the magnetic insulators comprise forming a material which includes one of: magnetite Fe ₃ 0 ₄ or Y3AI5O12.

[00131] Example 32 includes all features of example 30, wherein the Heusler alloys is one of: Co ₂ FeSi or MmGa.

[00132] Example 33 includes all features of example 32, wherein the 4-state magnet is configured to have four stable magnetic states including zero state, first state, second state, and third state, wherein the zero state is to point in a +x-direction, wherein the first state is to point in a +y-direction, wherein the second state is to point in a -y-direction, and wherein the third state is to point in a -x-direction.

[00133] Example 34 includes all features of example 33, wherein a thermal barrier between the zero, first, second, and third states is greater than or equal to 10 kT.

[00134] Example 35 includes all features of example 36, wherein the 6-state magnet is configured to have six stable magnetic states including zero state, first state, second state, third state, fourth state, and fifth state, wherein the zero state is to point in a +x-direction, wherein the first state is to point in a +y-direction, wherein the second state is to point in a - y-direction, wherein the third state is to point in a -x-direction, wherein the fourth state is to point in a -z-direction, and wherein the fifth state is to point in a +z-direction.

[00135] Example 36 includes all features of example 35, wherein the 6-state magnet is one of: magnetostrictive ferromagnets adjacent to corresponding piezoelectric layers; tri-axial anisotropy magnets; or in-plane bi-axial anisotropy magnets adjacent to corresponding piezoelectric layers.

[00136] Example 37 includes all features of example 35, wherein a thermal barrier between the zero, first, second, third, fourth, and fifth states is greater than or equal to 10 kT.

[00137] Example 38 includes all features of example 36, wherein the 6-state magnet comprises a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, and Heusler alloys of the form X?.YZ.

[00138] Example 39 includes all features of example 38, wherein the magnetic insulators comprises a material selected from a group consisting of: magnetite Fe ₃ 0 ₄ and Y3AI5O12, and wherein the Heusler alloys is one of: Co ₂ FeSi or M Ga.

[00139] Example 40 is an apparatus which comprises: a first metal layer; a second metal layer; and a via coupled to the first and second metal layers, wherein the via comprises a super lattice comprising alternate layers of magnets and non-magnetic materials to form a synthetic anti-ferromagnets (SAF).

[00140] Example 41 includes all features of example 24, wherein the alternate layers of magnets comprises one of: a 2-state magnet; a 4-state magnet; or a 6-state magnet, and wherein the non-magnetic materials of the super lattice comprise Ru.

[00141] Example 42 is a method which comprises: forming a first metal layer; forming a second metal layer; and forming a via coupled to the first and second metal layers, wherein the via comprises a super lattice comprising alternate layers of magnets and non-magnetic materials to form a synthetic anti-ferromagnets (SAF).

[00142] Example 43 includes all features of example 42: wherein the alternate layers of magnets comprises one of: a 2-state magnet; a 4-state magnet; or a 6-state magnet, and wherein the non-magnetic materials of the super lattice comprise Ru.

[00143] Example 44 includes an apparatus which comprises: a first metal layer; a second metal layer; and a via coupled to the first and second metal layers, wherein the via comprises graphene wrapped around non-magnetic metal.

[00144] Example 45 includes all features of example 26, wherein the non-magnetic metal, which is wrapped by the graphene, comprises Cu. [00145] Example 46 is a method which comprises: forming a first metal layer; forming a second metal layer; and forming a via coupled to the first and second metal layers, wherein the via comprises graphene wrapped around non-magnetic metal.

[00146] Example 47 includes all features of example 26, wherein the non-magnetic metal, which is wrapped by the graphene, comprises Cu.

[00147] Example 48 is a system which comprises: a processor; a memory coupled to the processor, the memory including an apparatus according to any one of apparatus examples 40 to 41 or 44 to 45; and a wireless interface for allowing the processor to communicate with another device.

[00148] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.