Title:
THREE-DIMENSIONAL STACKED DRAM ARRAY AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2023/191445
Kind Code:
A1
Abstract:
The present invention relates to a three-dimensional stacked DRAM array and a manufacturing method therefor, wherein, by vertically stacking a "U"-shaped drain-BL connection structure having two connection lines, a plurality of horizontal active lines are formed on one connection line while the plurality of horizontal active lines are stacked on the other connection line in a stepped shape and connected to bit lines, and accordingly, space can be efficiently used by sharing a ground electrode of a capacitor, and cell capacitance can be horizontally increased as much as possible and can be expanded as much as possible with a unit structure, such that difficulties in a metal wiring process such as bit lines due to vertical stacking can be solved.
Inventors:
KIM YOON (KR)
Application Number:
PCT/KR2023/004099
Publication Date:
October 05, 2023
Filing Date:
March 28, 2023
Export Citation:
Assignee:
UNIV SEOUL IND COOP FOUND (KR)
International Classes:
H10B12/00; H01L29/423
Foreign References:
| KR20130097562A | 2013-09-03 | |||
| KR20220031321A | 2022-03-11 | |||
| KR20210098198A | 2021-08-10 | |||
| KR20210030969A | 2021-03-18 | |||
| KR20090118299A | 2009-11-18 |
Attorney, Agent or Firm:
KWON, O Jun (KR)
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