FIELD OF THE INVENTION

[0001] The present invention relates to the field of integrated circuit chips; more specifically, it relates to through wafer vias for use in integrated circuit chips and the method of fabricating the through wafer vias.

BACKGROUND OF THE INVENTION

[0002] To increase the density of devices using integrated circuit chips it is desirable to allow interconnections to be made to both the top and bottom surfaces of the integrated circuit chip. This requires formation of through wafer vias from the top to the bottom surface of the integrated chip that are compatible with carrying both high frequency and DC signals. Many existing through via schemes are either difficult to integrate into existing integrated circuit fabrication processes or result in unacceptable degradation of signals propagating from/to the front surface of the integrated circuit chip to/from the bottom surface of the integrated circuit chip. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

SUMMARY OF THE INVENTION

[0003] A first aspect of the present invention is a structure, comprising: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate.

[0004] A second aspect of the present invention is a method, comprising: forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate.

[0005] A third aspect of the present invention is a method, comprising: (a) forming a first trench and a second trench in a semiconductor substrate, the first and second trenches independently extending from a top surface of the substrate toward an opposite bottom surface of the substrate a distance less than a thickness of the substrate; (b) simultaneously completely filling the first trench with a dielectric material and forming a liner of the dielectric material on sidewalls of the second trench; (c) filling remaining space in the second trench with an electrically conductive material; and (d) thinning the substrate from the bottom surface of the substrate to form a new bottom surface of the substrate, the dielectric material of the first trench and the liner and electrically conductive material of the second trench exposed in the new bottom surface of substrate.

[0006] A fourth aspect of the present invention is a signal transmission line through a semiconductor substrate, the substrate having a top surface and an opposite bottom surface, comprising: a conductive through wafer via extending from the top surface of the substrate to the bottom surface of the substrate, sidewalls of the conductive through via electrically insulated from the substrate; and a non-conductive through via extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate, the nonconductive through via proximate to and separated from the conductive through wafer by a region of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

[0008] FIGs. IA through IO are cross-sectional drawings illustrating initial steps in the fabrication of an array of through wafer vias according embodiments of the present invention;

[0009] FIGs. 2 A through 2 J are cross-sectional drawings illustrating completion of the fabrication of the array of through wafer vias according to embodiments of the present invention and fabrication of a three-dimensional device using arrays of through wafer vias according to embodiments of the present inventions;

[0010] FIGs. 3A through 3D are plan views of through wafer vias according to embodiments of the present inventions;

[0011] FIGs. 4 A through 4D are schematic plan views of waveguide models using through wafer vias according to embodiments of the present invention; [0012] FIG. 5 is a cross-sectional drawing illustrating an alternative structure to that illustrated in FIG. IB; and

[0013] FIG. 6 is a cross-sectional drawing illustrating an alternative structure to that illustrated in FIG. 21. DETAILED DESCRIPTION OF THE INVENTION

[0014] The term through wafer via defines a structure that extends from a top surface of a substrate, through the substrate, to an opposite bottom surface of the substrate of the packaged integrated circuit or chip. A through wafer via according to the embodiments of the present invention may be electrically conductive or electrically non-conductive. Although in the description infra, both conductive and non-conductive (i.e., insulating) through vias are described and illustrated as extending from the top to the bottom surface of the chip, the present invention may be practiced where the conductive through via extends entirely through the chip, but the non-conductive only extends partially through the chip because one purpose of the non-conductive through vias is for isolation and not passing electrical signals between the top and bottom surfaces of the chip. An electrically conductive through via includes at least one electrically conductive element and may include non-electrically conductive elements. An electrically non-conductive through via includes at least one electrically non-conductive element and may include electrically conductive elements that are surrounded completely by electrically non-conductive elements. The "wafer" of through wafer via derives from the fact that the via is formed before integrated circuits have been singulated from a semiconductor substrate called a wafer. The term " three dimensional device" defines a device comprising two or more individual substrates electrically connected and in physical contact by being stacked one upon another.

[0015] FIGs. IA through IO are cross-sectional drawings illustrating initial steps in the fabrication of an array of through wafer vias according embodiments of the present invention. In FIG. IA, a semiconductor substrate 100 has a top surface 105. Formed on top surface 105 is a first dielectric layer 110. Formed on a top surface 115 of first dielectric layer 110 is a second dielectric layer 120. First and second dielectric layers 110 and 120 are exemplary and there may be a few as one dielectric layer or more than two dielectric layers formed over top surface 105 of substrate 100. In one example, substrate 100 is a bulk silicon substrate. In one example first dielectric layer 110 is silicon dioxide and second dielectric layer 120 is silicon nitride.

[0016] In FIG. IB, trenches 125 and 130 are etched through first and second dielectric layers 110 and 120 and into substrate 100. Trenches 125 and 130 may be formed using a photolithographic/etching process. An exemplary photolithographic/etching process comprises (1) forming a photoresist layer on second dielectric layer 120, (2) forming openings in the photoresist layer by exposing the photoresist layer to actinic radiation through a patterned photomask and developing away either the exposed or unexposed regions of the photoresist, (4) etching through, the first and second dielectric layers using, for example, a reactive ion etch (RIE) process, (5) removing the patterned photoresist layer, and (6) etching substrate 100 using, for example, an RIE process using the pattern in the first and second dielectric layers as a patterned hardmask. Although trenches 125 and 130 are shown etched to the same depth in FIG. IB, trenches 125 and 130 may be etched to different depths. For example, an etch process commonly referred to as the "Bosch" silicon etch process will etch trenches having wide (W2) openings deeper then trenches having narrow openings (Wl). See FIG. 5. Etching trench 130 deeper would result in the structure of FIG. 6. Thus, trenches 125 and 130 may independently extend from 105 to between greater than halfway to and all the way to the bottom surface of substrate 100.

[0017] However, if substrate 100 is a silicon-on-insulator (SOI) substrate (i.e., a silicon substrate having a buried oxide layer or BOX layer) with the top surface of the buried oxide layer located a distance Dl from top surface 105 of substrate 100 then trenches 125 and 130 will be etched to the same depth even if a "Bosch" etch process is used since the BOX layer will act as an etch stop. In one example, the BOX layer comprises silicon dioxide.

[0018] Trenches 125 and 130 extend into substrate 100 the distance Dl from top surface 105 of the substrate. Trenches 125 have a width Wl and trench 130 has a width W2. W2 is greater than Wl . In one example, Wl is about 1 micron to about 3 microns. In one example, W2 is about 3 microns to about 10 microns. In one example Dl is about 50 microns to about 200 microns. In one example Wl is about 2 microns, W2 is about 5 microns and Dl is about 150 microns. Since trenches 125 and 130 may be elongated in and out of the plane of the drawings (i.e., are rectangles when viewed from above), Wl and W2 measure minimum widths of trenches 125 and 130 (i. e, the short side of the rectangle).

[0019] In FIG. 1C, a polysilicon layer 135 is deposited on top surfaces 140 of second dielectric layer 120, sidewalls 145 and bottoms 150 of trenches 125 and 130. In one example, polysilicon layer 135 comprises an N or a P-type doped polysilicon. In one example, polysilicon layer 135 comprises boron doped polysilicon. Polysilicon layer 135 has a thickness Tl. In one example, Tl is about 0.8 microns to about 2.4 microns.

[0020] In FIG. ID an oxidation is performed to convert polysilicon layer 135

(see FIG. 1C) to a silicon dioxide layer 155. Silicon dioxide layer 155 has a thickness T2. Silicon dioxide layer 155 completely fills trenches 125, but does not completely fill trench 130 because the width W2 of trench 130 is greater than twice the thickness T2 of silicon dioxide layer 155. Silicon dioxide layer conformally covers the sidewalls and bottom of trench 130. In one example, T2 is about equal to half of Wl. In one example, the oxidation of polysilicon layer 135 (see FIG. 1C) to form silicon dioxide layer 155 is performed using a high pressure oxidation (HIPOX) process. [0021] HIPOX of boron doped polysilicon (i.e., layer 135 of FIG. 1C) is preferred because of the high oxidation rate of born doped polysilicon and the ability of HIPOX to form uniform oxide thicknesses in deep trenches. [0022] Alternatively, the structure illustrated in FIG. ID may be formed by oxidation (e.g., in a furnace) of the sidewalls and bottoms of trenches 125 and 130 of FIG. IB or by deposition (e.g., by chemical vapor deposition (CVD) or atomic layer deposition (ALD)) of oxide on the sidewalls and bottom of trenches 125 and 130. Alternatively, any suitable dielectric, such as silicon nitride, alumina; or combination of multiple dielectrics would be suitable.

[0023] In FIG. IE, a polysilicon layer 170 is formed top surface 175 of silicon dioxide layer 155 and completely fills the remaining space in trench 130. In one example, polysilicon layer 170 comprises intrinsic (i.e., undoped) polysilicon. In a second example, the polysilicon is in-situ doped, with any known dopant such as phosphorus, arsenic, or boron.

[0024] In FIG. IF, a CMP is performed to remove polysilicon layer 170 from over silicon dioxide layer 155, so top surface 175 silicon dioxide layer 155 is coplanar with a top surface of polysilicon layer 170 in trench 130. Alternatively, any combination of CMP or lithographically patterned etch back process could be employed to planarize the wafer, as known in the art.

[0025] In FIG. IG, a polysilicon recess process is performed which removes all of polysilicon layer 170 from top surface 175 of dielectric layer 155 and from an upper region of trench 130. A top surface of polysilicon layer 170 remaining in trench 130 after the recess process is below top surface 105 of substrate 100. The polysilicon recess process may be performed using an RIE, a wet etch, or a combination of an RIE etch and a wet etch. In the preferred embodiment, this recess extends below dielectric layer 110, to facilitate the capping of the trench with layer 185, as shown in

Figure II.

[0026] In FIG. IH, a dielectric layer 185 is formed on top of surface 175 of silicon dioxide layer 155 and in trench 165. Dielectric layer 185 completely fills the space created in trench 130 by the polysilicon recess etch of FIG. IF. Alternatively, dielectric layer 185 fills the space created in trench 130 such that a void does not extend to the surface 105 after the planarization shown in Figure II. In one example dielectric layer 185 comprises TEOS oxide (i.e., oxide formed by CVD using tetraethoxysilane precursor), silane oxide (i.e., oxide formed by CVD using silane precursor), or any dielectric deposited using LPCVD (i.e., low pressure CVD) or HDPCVD )i.e., high density plasma CVD) or any other known method. [0027] In FIG. II, a CMP and/or other etching is performed to remove dielectric layer 185, silicon dioxide layer 155, second dielectric layer 120 from over top surface 105 of substrate 100 leaving a cap of dielectric layer 185 in trench 130. Silicon dioxide layer 155 also remains in trenches 125. After the CMP, top surfaces of silicon dioxide layer 155 in trenches 125, edges of silicon dioxide layer 155 in trench 130, a top surface of dielectric layer 185 in trench, and top surface 105 of substrate 100 are all coplanar or substantially coplanar. Although the complete removal of all layers above substrate 100 is shown, partial removal or selective partial removal may also be performed.

[0028] In FIG. IJ, a new first dielectric layer 190 and a new second dielectric layer 195 are formed on top surface 105 of substrate 100. Silicon dioxide layer 155 remains in trenches 125 and silicon dioxide layer 155, polysilicon layer 170 and dielectric layer 185 remain in trench 130 protected by dielectric layers 190 and 195. The purpose of dielectric layers 190 and 195 are to facilitate the formation of integrated circuit structures such as shallow trench isolation (STI), deep trench capacitors, MOSFET transistors, bipolar junction transistors, diodes, varactors, thin film resistors, MOS capacitors, etc. as known in the art. Alternatively, any known set of methods and structures could be employed to form the integrated circuit structures. [0029] In FIG. IK, STI 200 has been formed in substrate 100 by a photolithographic/etching process in combination new first and second dielectric layers 190 and 195 (see FIG. IH) similar to that described supra followed by a TEOS CVD followed by a CMP.

[0030] Next, additional photolithographic/etching process/deposition process has been performed to form a FET 205 and a trench capacitor 210. FET 205 and trench capacitor are examples of integrated circuit devices that may be formed at this point in fabrication. Other devices that may be formed at this point include bipolar transistors, BiCMOS SiGe transistors, diodes MOS capacitors, and resistors. FET 205 includes source/drains 215, a gate dielectric 220, a gate electrode 225, and suicide contacts 230. Trench capacitor 210 includes an inner plate 235 and a dielectric layer 238. New first and second dielectric layers 190 and 195 are removed prior to forming gate dielectric layer 220 and an interlevel dielectric layer 240 is formed over top surface 105 of substrate 100 after forming suicide layers 230. Interlevel dielectric layer 240, by way of example, comprises a lower dielectric layer 245 and an upper dielectric layer 250. Interlevel dielectric layer 240 may be a single layer or may include more than two layers. In one example, lower dielectric layer 245 comprises silicon nitride and upper dielectric layer 250 comprises boro-phosphosilicate glass (BPSG).

[0031] In FIG. IK and subsequent FIGs. IL through 10, lower dielectric layer

245 is shown as not covering gate 225 of FET 205 for clarity. In actuality, lower dielectric layer 245 covers gate 225 of FET 205 as well. [0032] In FIG. IL, an opening 255 through lower and upper dielectric layers

245 and 250 over suicide layer 230 of FET 205 is formed using a photolithographic/etching process as described supra.

[0033] In FIG. IM, an electrically conductive stud contact 265 is formed to suicide layer 230 in opening 255 and a protective layer 270 is formed on contact 265 and upper dielectric layer 250. Contact 265 may be formed, for example, by forming an electrically conductive layer (e.g., by evaporation, sputtering or deposition) over upper dielectric layer 250, which completely fills trench 255 and is followed by a CMP. Then protective layer 270 is formed. Contact 265 may independently comprise any of the material combinations described infra for through wafer via core 275 (see FIG. 10) and through wafer via contact 280 (see FIG. 10). In one example, protective layer 270 is a dielectric layer. In one example, protective layer 270 comprises silicon nitride.

[0034] It should be understood, that many other stud contacts 265 are formed at this time to other devices in substrate 100. It should be understood that many other methods exist for forming and metallizing stud contact 265. It should be understood that there are many methods and structures used to form stud contacts to integrated circuit devices, as known in the art.

[0035] In FIG. IN, an opening 132 is formed through protective layer 270 and upper and lower dielectric layers 245 and 250 over trench 130 using a photolithographic/etching process as described supra. Then, an RIE is performed to remove dielectric layer 185 (see FIG. IL) from trench 130. Next, a RIE etch, a wet etch or a combination of wet and RIE is used to remove polysilicon layer 170 (see FIG. IL) from trench 130. Note that, during these polysilicon layer 170 etches, dielectric layer 155 protects substrate 100 (when substrate 100 is silicon) from being etched. To avoid etching substrate 100, opening 132 over trench 130 must not fall outside dielectric layer 155 and, in a preferred embodiment, is aligned such that opening 132 falls inside layer 155 (i.e., when layers 270, 250 and 240 are etched the opening is fully landed on layer 185, see FIG. IM) such that when polysilicon layer 170 is exposed in opening 132 after layer 185 is etched dielectric layer 155 is not exposed in the opening under polysilicon layer 170 is etched away. [0036] In FIG. 10, a through wafer via core 275 is formed in trench 130 and an integrally formed (with through wafer via core 275) through wafer via contact 280 is formed in the opening in protective layer 270 (see FIG. IN) and interlevel dielectric layer 240 over trench 130. Through wafer via core 275 and through wafer via contact 280 may be formed, for example, by forming an electrically conductive layer (e.g., by evaporation, sputtering or deposition) over upper dielectric layer 250 which completely fills trench 130 and the opening in protective layer 270 (see FIG. IN) and interlevel dielectric layer 240 and is which followed by a CMP. In FIG. 10, the CMP has completely removed all of protective layer 270 (see FIG. IN). Alternatively, a thinned layer of protective layer 270 may remain after the CMP. Top surfaces of through wafer via contact 280 and stud contact 265 are coplanar with the top surface of upper dielectric layer 250.

[0037] In one example, through wafer via core 275 and through wafer via contact 280 comprise a metal. In one example, through wafer via core 275 and through wafer via contact 280 comprise tungsten (W) or tungsten and titanium nitride (TiN). In one example, through wafer via core 275 and through wafer via contact 280 comprise a first deposited conformal layer of titanium nitride and a second deposited layer of tungsten. In one example, through wafer via core 275 and through wafer via contact 280 comprise a first deposited conformal layer of titanium nitride, a second deposited layer of conformal titanium (Ti) and a third deposited layer of tungsten.

Titanium, titanium nitride and tungsten may be deposited using CVD. [0038] In one example, through wafer via core 275 and through wafer via contact 280 comprise tungsten or tungsten and tantalum nitride (TaN). In one example, through wafer via core 275 and through wafer via contact 280 comprise a first deposited conformal layer of tantalum nitride and a second deposited layer of tungsten. In one example, through wafer via core 275 and through wafer via contact 280 comprise a first deposited conformal layer of tantalum nitride, a second deposited layer of conformal tantalum (Ta) and a third deposited layer of tungsten. Tantalum and tantalum nitride and may be deposited using CVD.

[0039] Other metallurgical combinations that may be used for through wafer via core 275 and through wafer via contact 280 include combinations of copper (Cu), ruthenium (Ru), Ta and TaN. Those combinations include the following combinations, each of which is in the order of formation: Ta/Cu, TaN/Cu, Ru/Cu, TaN/Ta/Cu/, TaN/Ru/Cu, Ta/Ru/Cu, Ru/Ta/Cu, Ru/TaN/Cu, TaN/Ta/Ru/Cu. [0040] It should be understood that stud contacts 265 may be formed of the same or different materials then through wafer via core 275 and through wafer via contact 280 are formed of. Again, stud contact may b e formed of any of the material combinations listed supra for through wafer via core 275 and through wafer via contact 280. It should be understood, that many through wafer vias cores 275 and through wafer via contacts 280 are formed at this time. It should be understood that many other methods exist for forming and metallizing both through wafer via cores 275 and through wafer via contacts 280. For example, electroplated copper could be used in place of tungsten; and tantalum or tantalum nitride could be used in place of titanium nitride. It should be also understood that by thinning substrate 100 from the bottom, a through wafer via will be formed as illustrated in FIGs. 2 A through 2 J and described infra. Through wafer via core 275 is electrically isolated from substrate

100, by silicon dioxide layer 155. Both through wafer via core 275 and the portions of silicon dioxide layer 155 on the sidewalls of trench 130 will become a conductive through wafer via (through wafer via core 275 being an electrically conductive portion and silicon dioxide layer being a non-conductive portion). Silicon dioxide layers 155 in trenches 125 will become non-conductive through wafer vias. [0041] FIGs. 2 A through 2 J are cross-sectional drawings illustrating completion of the fabrication of the array of through wafer vias according to embodiments of the present invention and fabrication of a three-dimensional device using arrays of through wafer vias according to embodiments of the present inventions.

[0042] In FIG. 2A, (not drawn to scale) formed in a set of interlevel dielectric layers 300 are corresponding wires and vias 305. An optional terminal pad 310 is formed on a top surface 315 of the set of interlevel dielectric layers 300 and is in electrical contact with an uppermost wire 305 in an uppermost interlevel dielectric layer of the set of interlevel dielectric layers 300. Wires in a lowermost interlevel dielectric layer of the set of interlevel dielectric layers are in physical and electrical contact with stud contacts 265 and integral contact regions 280. Individual interlevel dielectric layers of the set of interlevel dielectric layers 300 are not illustrated in FIG. 2A. A handle substrate 325 is attached to top surface 315 of the set of interlevel dielectric layers 300. Handle wafer 325 is attached using a layer of adhesive (not shown). In one example, handle substrate 325 is a quartz wafer. [0043] In FIG. 2B, substrate 100 is thinned from the bottom (for example, by grinding) to form a new bottom surface 320 that is a distance D2 from trenches 125 and 130. In one example, D2 is about 5 microns to about 50 microns. In one example, D2 is about 20 microns. After thinning, the thickness of substrate 100 is D3. In one example, D3 is about 50 microns to about 200 microns. In one example, D3 is about 170 microns. [0044] In FIG. 2C, a RIE or wet etch selective to silicon is preformed to recess bottom surface 320 (see FIG. IB) of substrate 100 so the fill material of trenches 125 and 130 protrudes above a new top surface 320A.

[0045] In FIG. 2D, a CMP is performed to remove the fill material protruding above top surface 320A (see FIG. 2C) to form through wafer via arrays 330. In the example of FIG. 2D, each through wafer via array 330 includes two non-conductive through wafer vias 125A and one conductive through via 130A. After the CMP, the electrically conductive through wafer region 275 and silicon dioxide layers 155 (see

FIG. 2C) are exposed at bottom surface 320 of substrate 100.

[0046] In FIG. 2E, a RIE or wet etch selective to preferentially etch silicon over silicon dioxide is preformed to recess bottom surface 320A (see FIG. 2D) below the bottoms of through wafer via arrays 330 and to form a new bottom surface 335 of substrate 100.

[0047] In FIG. 2F, a dielectric layer 340 is formed over bottom surface 335 of substrate and over through wafer via arrays 330. In one example, dielectric layer 340 is a plasma enhanced chemical vapor deposition (PECVD) silicon oxide.

[0048] In FIG. 2G, a CMP is performed to remove dielectric layer 340 from over the bottom surfaces of through wafer via arrays 330. Dielectric layer 340 remains on bottom surface 335 of dielectric layer 340 and dielectric layer 340 fills any spaces between through wafer via arrays 330 between individual through wafer vias

125 A and 130A of each of the through wafer via arrays. Bottom surfaces of through wafer vias 125 A and 130A are coplanar or substantially coplanar with a top surface

350 of dielectric layer 340.

[0049] Alternatively, the backside grind process illustrated in FIG. 2B and described supra, can be continued until non-conductive through wafer vias 125 A and conductive through wafer vias 130A of FIG. 2D are formed directly (skipping the processes of FIG. 2C) or after grinding and a "clean-up" CMP to remove any grinding damage to the through wafer vias and surface 320A (see FIG. 2D). This alternative is advantageously applied when trenches 125 have not been etched significantly deeper into substrate 100 then trenches 130 (see FIG. 2A). If trenches 130 are etched significantly deeper than trenches 125 (see FIG. 5), then the grinding could expose conductive through via 130A but not non-conductive through vias 125 A as illustrated in FIG. 6.

[0050] It should be noted that through wafer via 125 A comprises a first trench filled only with an insulator and through wafer via 130A comprises a second trench having a filling only consisting of a dielectric liner surrounding an electrically conductive core.

[0051] In FIG. 2H, electrically conductive pads 345 are formed on top surface

350 of dielectric layer 340 on through wafer via arrays 330 and electrically conductive solder bumps 355 are formed on pads 345. In one example, pads 345 and solder bumps 355 are formed by electroplating through a patterned photoresist layer or by evaporation through a metal mask. If pads 345 are formed by plating, a thin electrically seed layer is first deposited, which is removed after the photoresist layer is removed, by RIE or wet etching.

[0052] In FIG. 21, handle wafer 325 (see FIG. 2G) is removed, either prior to or after chip dicing. An exemplary method of removing handle wafer 325 is to expose the adhesive to ultraviolet radiation as is well known in the art. In a preferred embodiment, handle wafer 325 is removed after dicing to minimize the potential for breaking the thinned wafer.

[0053] FIG. 2J is an exploded view prior to a solder reflow step. In FIG. 2J, an upper substrate 360 containing electrical components is aligned to terminal pad 310 by electrically conductive solder bumps 365, and substrate 100 is aligned to a lower substrate 370 having electrically conductive pads 375 and containing electrical components (not shown) by solder bumps 355. This arrangement allows for self alignment of the three components prior to the anneal which melts the solder bumps, electrically wires substrates 100, 360 and 370 together and completes the fabrication process. Examples of electrical components include but are not limited to, transistors, diodes, resistors, capacitors, inductors and wires.

[0054] While pad to solder bump connections are illustrated in FIG. 2J, other connection types such as pad to pad may be used (i) between substrate 360 and substrate 100, (ii) between substrate 100 and substrate 370 or (iii) between substrate 360 and substrate 100 and between substrate 100 and substrate 370 substrate. While solder bumps are shown on substrate 360 and pads on substrate 100, pads may be formed on substrate 360 and solder bumps on substrate 370. While the solder bumps are shown on substrate 100 and pads on substrate 370, pads may be formed on substrate 100 and solder bumps on substrate 370. Substrate 360 may be replaced with wire or tab bonds. If the solder bumps and pads of substrate 100 are swapped, then substrate 370 may be replaced with wire or tab bonds.

[0055] FIGs. 3A through 3D are exemplary plan views of through wafer vias according to embodiments of the present inventions. In FIG. 3A, a single through wafer via array 330A consists of an electrically non-conductive through wafer via 125 A filled with silicon dioxide layer 155 and a single electrically conductive through wafer via 130A consisting of silicon dioxide layer 155 intervening between conductive through via region 275 and substrate 100.

[0056] In FIG. 3B, a through wafer via array 330B consists of two electrically non-conductive through wafer vias 125 A filled with silicon dioxide layer 155 on opposite sides of electrically conductive through wafer via 130A consisting of silicon dioxide layer 155 intervening between conductive through via region 275 and substrate 100.

[0057] In FIG. 3C, a through wafer via 330C comprises four trenches electrically non-conductive through wafer vias 125 A filled with silicon dioxide layer 155 on opposite each of the four sides of electrically conductive through wafer via 130A consisting of silicon dioxide layer 155 intervening between conductive through via region 275 and substrate 100.

[0058] In FIG. 3D, through wafer via 330C consists of seven electrically non- conductive through wafer vias 125 A filled with silicon dioxide layer 155 and two electrically conductive through wafer via 130A consisting of silicon dioxide layer 155 intervening between conductive through via region 275 and substrate 100. Three of through wafer vias 125 A are positioned between the two through wafer vias 130A. Four of the through wafer vias 125 A are positioned opposite each of the four sides formed by the combination the first three through wafer vias 125 A and the two through wafer vias 130. Through wafer vias 330B, 330C and 330D function as coplanar waveguides.

[0059] In each of FIGs. 3A, 3B, 3C and 3D every through wafer via 125A and

130A is surrounded by a region of substrate 100. Through wafers vias of the present embodiment of the present invention includes at least one electrically conductive element extending from the top surface of the substrate, through the substrate, to the bottom surface of the substrate and at least one non-electrically conductive (i.e., dielectric or insulator) element also extending from the top surface of the substrate, through the substrate, to the bottom surface of the substrate.

[0060] It should be understood that very many other through wafer via arrays having different numbers and configurations of through wafers vias 125 A and 130A are possible and are not limited to those illustrated in FIG. 3A, 3B, 3C and 3D. [0061] FIGs. 4 A through 4D are schematic plan views of waveguide models using through wafer vias according to embodiments of the present invention. In FIGs. 4A, 4B, 4C and 4D, G indicates an electrical conductor filled trench that is not insulated from the substrate and that is connected to ground, S indicates an electrical conductor filled trench that is not insulated from the substrate and is connected to a signal source, I indicates an electrical insulator filled trench, IG indicates an electrical conductor filled trench connected to ground and that is insulated from the substrate and IS indicates an electrical conductor filled trench connected to a signal source and that is insulated from the substrate. The space between the G, S. I, IG and IS structures is substrate.

[0062] The structures of FIG. 4A, 4B, 4C and 4D were modeled as signal waveguides for characteristic impedance, propagation loss and effective dielectric constant (Er). Low propagation loss and small effective dielectric constant are preferred. The model was based on a silicon substrate with a relative dielectric constant of 11.9 and a conductivity of 7.41 Siemens/meter; tungsten with a conductivity of 1.82E7 Siemens/meter for the electrical conductor for the G, IG, S and IS structures; and silicon dioxide with a relative dielectric constant of 4.1 for the insulator of the I, IG and IS structures.

[0063] The dimensions of the G and S structures in top view was 50 by 3 microns. The dimensions of the IG and IS structures in top view was 52 by 5 microns (the G and S structures with a surrounding insulator 1 micron thick). The dimensions of the I structures in top view was 52 by 5 microns. Simulation was performed on an Ansoft HFSS-3D full wave EM simulator. Table I gives the result of the simulation for each of the structures of FIGs. 4A, 4B 4C and 4D. TABLE I

[0064] The following conclusions can be reached as a result of the simulation.

For coplanar waveguides, insulated through wafer vias have a higher characteristic impedance, less propagation loss, lower effective dielectric constant and is better for signal propagation with less potential un-wanted coupling. The reasons are, silicon is lossy, but silicon dioxide is not. The higher dielectric constant of silicon causes higher parasitic capacitance relative to parasitic capacitance of the lower dielectric constant silicon dioxide.

[0065] Thus, a through wafer via that contacts the substrate directly (G structure) as in the embodiments of the present invention, may be used for the ground structure as long as the voltage across the through wafer via is low enough for little or no current is conducted through the substrate. For the signal structure, an insulated conductor (IS structure) such as in the second and third embodiments of the present invention is preferred to reduce signal conduction through the substrate. [0066] FIG. 5 is a cross-sectional drawing illustrating an alternative structure to that illustrated in FIG. IB. In FIG. 5, trench 130B extend a distance D3 into substrate 100 from top surface 105, while trenches 125 extend into substrate 100 from top surface 105 the distance D2 as described supra with respect to FIG. IB. D3 is greater than D2, while D2 is equal to Dl (see FIG. IB).

[0067] FIG. 6 is a cross-sectional drawing illustrating an alternative structure to that illustrated in FIG. 21. The structure of FIG 6 results if the structure of FIG. IB is replaced by the structure of FIG. 5. In FIG. 6, conductive through vias 130B contact pads 345 while non-conductive through vias 125B (a misnomer in this case, they are partial-through vias) do not contact pads 345. Regions of substrate 100 and dielectric layer 340 intervene between non-conductive through vias and pad 345. [0068] Thus, the embodiments of the present invention provide a structure and method to integrate through wafer vias into existing integrated circuit fabrication processes having in good propagation of signals from/to the front surface of the integrated circuit chip to/from the bottom surface of the integrated circuit chip. [0069] The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.