TIME-TO-DIGITAL CONVERTER AND DIGITAL PHASE-LOCKED LOOP

WIPO Patent Application WO/2017/197581

A1

Provided are a time-to-digital converter and a digital phase-locked loop. The time-to-digital converter comprises N stages of conversion circuits, where N is greater than or equal to 2, and N is an integer. Each stage of conversion circuit comprises a first delayer and an arbiter. An output end of the first delayer of each stage of conversion circuit outputs a delay signal of this stage of conversion circuit. The arbiter of each stage of conversion circuit receives a sampling clock and the delay signal of this stage of conversion circuit and compares same to obtain an output signal of this stage of conversion circuit. The output signal of the N stages of conversion circuits form a non-linear binary number for indicating a time difference between a clock signal and a reference signal. Since the first delayers of the N stages of conversion circuits all have the same first delay unit circuit for ensuring the stability of a delay ratio and the accuracy of a delay time of each stage of conversion circuit, and the number of first delay unit circuits in each of the first delayers can be flexibly set, the number of stages of circuits can be effectively reduced in the case of a large dynamic range, thus reducing the circuit area and power consumption.

YAN HAO (CN)
HUANG JIALE (CN)
LU LEI (CN)

PCT/CN2016/082334

November 23, 2017

May 17, 2016

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HUAWEI TECH CO LTD (CN)

H03M1/50

CN104935344A	2015-09-23
CN103957005A	2014-07-30
CN103986461A	2014-08-13
JP5577232B2	2014-08-20

See also references of EP 3273601A4
None

CHINABLE IP (CN)

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