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Patent Searching and Data


Title:
TIME-TO-DIGITAL CONVERTING CIRCUIT AND PHASE-LOCKED LOOP
Document Type and Number:
WIPO Patent Application WO/2019/146177
Kind Code:
A1
Abstract:
According to the present invention, power consumption is suppressed in a time-to-digital converting circuit (TDC) used in a phase-locked loop. The time-to-digital converting circuit is provided with an analog-to-digital converting circuit and a current source circuit. The analog-to-digital converting circuit is provided with a prescribed charge capacitor. The current source circuit supplies a charge current that charges an electric charge to the charge capacitor of the analog-to-digital converting circuit. The charge current is supplied by the current source circuit such that a charged voltage has a constant slope over a charge time while the charge capacitor of the analog-to-digital converting circuit is charged by the charge current,.

Inventors:
ETOU, Shinichirou (4-14-1 Asahi-cho Atsugi-sh, Kanagawa 14, 〒2430014, JP)
FUJIWARA, Tetsuya (4-16-1 Okata Atsugi-sh, Kanagawa 21, 〒2430021, JP)
Application Number:
JP2018/038313
Publication Date:
August 01, 2019
Filing Date:
October 15, 2018
Export Citation:
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Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORPORATION (4-14-1 Asahi-cho, Atsugi-shi Kanagawa, 14, 〒2430014, JP)
International Classes:
H03L7/085; H03K5/26; H03L7/08
Domestic Patent References:
WO2016104464A12016-06-30
Foreign References:
US20160373120A12016-12-22
JP2014207569A2014-10-30
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (Craft Intellectual Property, Keio Shinjuku 3-chome 2nd Bldg.5F, 3-3-2 Shinjuku, Shinjuku-k, Tokyo 22, 〒1600022, JP)
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