Title:
TIMING COMPARATOR, DATA SAMPLING DEVICE, AND TEST DEVICE
Document Type and Number:
WIPO Patent Application WO/2005/050231
Kind Code:
A1
Abstract:
A data sampling device includes: a first variable delay element of multiple stages for successively delaying a data signal with a first delay amount; a second variable delay element of multiple stages for successively delaying a strobe signal with a second delay amount which is greater than the first delay amount; and a plurality of timing comparators for sampling data signals delayed by the first variable delay element of multiple stages by the strobe signal delayed by the second variable delay element of the same stage. Each of the timing comparators includes: a dynamic D-FF circuit for latching a data signal by a parasitic capacity according to the strobe signal and outputting it; a buffer for delaying the strobe signal; and a positive feedback D-FF circuit for latching the output signal from the dynamic D-FF circuit by a positive feed back circuit according to the delayed strobe signal and outputting it.
Inventors:
SUDA MASAKATSU (JP)
SUDOU SATOSHI (JP)
OKAYASU TOSHIYUKI (JP)
SUDOU SATOSHI (JP)
OKAYASU TOSHIYUKI (JP)
Application Number:
PCT/JP2004/005664
Publication Date:
June 02, 2005
Filing Date:
April 28, 2004
Export Citation:
Assignee:
ADVANTEST CORP (JP)
SUDA MASAKATSU (JP)
SUDOU SATOSHI (JP)
OKAYASU TOSHIYUKI (JP)
SUDA MASAKATSU (JP)
SUDOU SATOSHI (JP)
OKAYASU TOSHIYUKI (JP)
International Classes:
G01R31/319; H03K5/13; H03K5/135; H03L7/07; H03L7/081; H03L7/091; H04L7/00; (IPC1-7): G01R31/3181
Domestic Patent References:
| WO2003036796A1 | 2003-05-01 |
Foreign References:
| JPH05223891A | 1993-09-03 | |||
| JPH1041789A | 1998-02-13 | |||
| JPH09200000A | 1997-07-31 | |||
| US6072336A | 2000-06-06 | |||
| US5544203A | 1996-08-06 | |||
| US4929850A | 1990-05-29 |
Other References:
See also references of EP 1686388A4
CHAPMAN J ET AL.: "A LOW-COST HIGH-PERFORMANCE CMOS TIMING VERNIER FOR ATE" PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE (ITC)", PROCEDDINGS OF THE INTERNATIONAL TEST CON-VERENCE (ITC), 21 October 1995 (1995-10-21), pages 459 - 468
CHAPMAN J ET AL.: "A LOW-COST HIGH-PERFORMANCE CMOS TIMING VERNIER FOR ATE" PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE (ITC)", PROCEDDINGS OF THE INTERNATIONAL TEST CON-VERENCE (ITC), 21 October 1995 (1995-10-21), pages 459 - 468
Attorney, Agent or Firm:
Ryuka, Akihiro (24-12 Shinjuku 1-chom, Shinjuku-ku Tokyo, JP)
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