Title:
TIMING CONSTRAINT METHOD AND APPARATUS FOR INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE AND CHIP
Document Type and Number:
WIPO Patent Application WO/2023/051217
Kind Code:
A1
Abstract:
A timing constraint method and apparatus for an integrated circuit, and an electronic device and a chip. The method comprises: if it is determined, on the basis of the current delay constraints of a plurality of modules, that there is a module that does not meet a timing closure condition, determining a target module, and performing logical comprehensive processing on the target module, so as to obtain a first comprehensive result corresponding to function description information of the target module; determining an actual delay time of the target module on the basis of the first comprehensive result; and updating the current delay constraint of the target module on the basis of the actual delay time, so as to obtain a target delay constraint.
Inventors:
CHEN WENJIE (CN)
XU NINGYI (CN)
XU NINGYI (CN)
Application Number:
PCT/CN2022/118057
Publication Date:
April 06, 2023
Filing Date:
September 09, 2022
Export Citation:
Assignee:
SHANGHAI SENSETIME INTELLIGENT TECH CO LTD (CN)
International Classes:
G06F30/3312; G06F30/327
Foreign References:
| CN113868992A | 2021-12-31 | |||
| CN109948221A | 2019-06-28 | |||
| CN104182570A | 2014-12-03 | |||
| CN103631315A | 2014-03-12 | |||
| US20060053395A1 | 2006-03-09 |
Attorney, Agent or Firm:
BEIJING BESTIPR INTELLECTUAL PROPERTY LAW CORPORATION (CN)
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