The invention is related to the technology of microelectronic circuits that comprise internal moni toring for detecting timing events. In particular, the invention concerns an advantageous circuit-element- level implementation of a timing event detector cir cuit.

BACKGROUND OF THE INVENTION

Time borrowing in a microelectronic circuit means that a circuit element is temporarily allowed to borrow time from a subsequent stage, i.e. change a digital value later than expected, if the subsequent circuit element(s) on the same processing path can handle it without corrupting the data that is being processed. Time borrowing may be combined for example with AVS (Advanced Voltage Scaling), so that the oc currence of time borrowing is detected as a timing event, and an increasing number of detected timing events causes an increase in the operating voltage and vice versa. The number of detected timing events may also trigger other compensating actions, typically in volving changes in the values of other operating pa rameters of the circuit, like the clock frequency for example, or temporarily changing the clock waveform. Processing paths in the microelectronic cir cuit go through logic units and register circuits, so that a register circuit stores the output value of a preceding logic unit at the rising or falling edge of a triggering signal (if the register circuit is a flip-flop) or at a high or low level of the triggering signal (if the register circuit is a latch). A trig- gering edge or some other controlling event of the triggering signal defines an allowable time limit be fore which a digital value must appear at a data input of the register circuit to become properly stored. The allowable time limit is not necessarily the exact mo ment of the triggering edge, but defined in some rela tion to it due to physical effects such as the finite rate at which a voltage level can change. The logic units may also be referred to as pieces of combinato rial logic.

Monitor circuits are used to detect timing events. They can alternatively be called timing event detector circuits, but the term monitor circuit is more practical because it is short. A monitor circuit is a circuit element or functionality typically added to or associated with a register circuit and config ured to produce a timing event observation (TEO) sig nal as a response to a change in the input digital value that took place later than said allowable time limit. In addition to the actual monitor circuits, the microelectronic circuit must comprise an OR-tree and/or other structures for collecting, processing, and analyzing the TEO signals from the monitor cir cuits. Monitor circuits can also be used as standalone devices for other applications, such as edge detectors within digital phase-locked loops.

A major drawback of monitor circuits is that they consume circuit area and operating power. Many known monitor circuit implementations also involve compromises concerning performance.

Additional complexity to the task of design ing a microelectronic circuit comes from the require ment of testability. The concept of DFT (Designed For Testability, or Design-For-Test) has become a de facto industrial standard that defines certain procedures for testing a microelectronic circuit. As an example, it should be possible to selectively couple the regis- ter circuits contained in the microelectronic circuit into long chains that operate essentially as shift registers: a string of digital values can be fed in from one end and read out from the other end. Passing a known test pattern through such a chain of register circuits and checking its form at the output tells whether all register circuits in the chain are chang ing their states as desired or whether there are reg ister circuits that are stuck at some particular value (stuck-at fault test). An at-speed fault test involves feeding in a test pattern slowly at a low clock speed, then giving one or more clock pulses at the full oper ating speed so that the test pattern proceeds in the chain at functional logic speed by as many steps as there are clock pulses, and finally clocking the test pattern out again at a low clock speed. The at-speed test may give information about register circuits that are slower than intended. If there are monitor cir cuits and time borrowing capability involved, also these should be testable.

SUMMARY

It is an objective of the invention to pre sent a timing event detector, a microelectronic cir cuit, and a method for operating a microelectronic circuit that enable monitoring for timing events while simultaneously requiring only limited silicon area and consuming only a limited amount of power. A further objective is to enable the detection of timing events in a reliable manner even with very low operating voltage levels. A yet further objective is to make the monitoring of timing events compatible with the stand ard practices of DFT.

The objectives of the invention are achieved by using a monitor arrangement based on parallel uni directional latches, and equipping the monitor ar rangement with a comparator comparing the outputs of such latches, so that the result of such comparison can be selectively frozen with an external control signal.

According to a first aspect there is provided a timing event detector circuit for producing a timing event observation signal as a response to a change in a digital value at an input of an associated register circuit that took place later than an allowable time limit defined by a triggering signal. The timing event detector circuit comprises a data input configured to receive said digital value, a clock signal input con figured to receive said triggering signal, and a tim ing event observation output configured to output said timing event observation signal. The timing event de- tector circuit is configured to store, in relation to said allowable time limit, a corresponding momentary value of said digital value in differential form that comprises said momentary value and its complement val ue. The timing event detector circuit is configured to toggle, during a timing event detection window follow ing said allowable time limit, one of said stored mo mentary value or its stored complement value in re sponse to an observed change of said digital value, so that each of said stored momentary value or its stored complement value is only toggled in response to ob serving the digital value change in respective one di rection. The timing event detector circuit is config ured to compare, during said timing event detection window, said stored momentary value to its stored com- plement value and to output said timing event observa tion signal in response to said comparing showing that said stored momentary value and its stored complement value have become equal.

According to a second aspect there is provid- ed a timing event detector circuit for producing a timing event observation signal as a response to a change in a digital value at an input of an associated register circuit that took place later than an allowa ble time limit defined by a triggering signal. The timing event detector circuit comprises a data input configured to receive said digital value, a clock sig nal input configured to receive said triggering sig nal, and a timing event observation output configured to output said timing event observation signal. The timing event detector circuit is configured to store, in relation to said allowable time limit, a corre sponding momentary value of said digital value in par allel double form that comprises two copies of said momentary value. The timing event detector circuit is configured to toggle, during a timing event detection window following said allowable time limit, one of said copies of the stored momentary value in response to an observed change of said digital value, so that the first copy is only toggled in response to observ ing the digital value change in one direction and the second copy is only toggled in response to observing the digital value change in the opposite direction. The timing event detector circuit is configured to compare, during said timing event detection window, said stored copies of the momentary value and to out put said timing event observation signal in response to said comparing showing that the stored copies of said momentary value have become unequal.

According to an embodiment the timing event detector circuit comprises a first unidirectional latch circuit and a second unidirectional latch cir cuit, each having a respective latch data input cou pled to said data input, a respective output, and a respective latch clock input coupled to said clock signal input. A unidirectional latch circuit of this kind is a circuit element configured to store its in put data at the beginning of an enabling pulse in the triggering signal, and toggle its output only if its input data changes value in a predetermined direction during said enabling pulse in the triggering signal. This involves the advantage that a particularly simple implementation with only a limited number of transis tors can be provided.

According to an embodiment, both of said first and second unidirectional latch circuits are configured to toggle their output only if the corre sponding input data changes value in a direction that is the same for them both, and the timing event detec tor circuit comprises an inverter between said data input and one of the first and second unidirectional latch circuits, for storing said corresponding momen tary value of said digital value in said differential form that comprises said momentary value in one of the unidirectional latch circuits and said complement val ue in the other unidirectional latch circuit. This in volves the advantage that exactly similar circuit ele ments can be used as both of said two unidirectional latch circuits, which simplifies the design.

According to an embodiment said storing of the corresponding momentary value of said digital val ue in differential form that comprises said momentary value and its complement value is implemented with voltage-mode CMOS logic. This involves the advantage that floating nodes and other drawbacks of current mode logic are avoided.

According to an embodiment:

- each of the first and second unidirectional latch circuits comprises respectively: a first tran sistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh tran sistor, and an eighth transistor, of which the first, fourth, fifth, and seventh transistors are PMOS tran sistors and the second, sixth, and eighth transistors are NMOS transistors,

- the timing event detector circuit comprises an upper voltage rail, a lower voltage rail, and an NMOS-type enabler transistor, the source of which is coupled to the lower voltage rail and the gate of which is coupled to said clock signal input;

- in each of the first and second unidirec tional latch circuits:

-- the source of the first transistor is cou pled to the higher voltage rail,

-- the drain of the first transistor is cou pled to the source of the fourth transistor,

-- the drain of the fourth transistor is cou pled to the drain the second transistor,

-- the source of second transistor is coupled to the drain of the enabler transistor,

-- the gates of the first and second transis tors are coupled together and constitute the latch da ta input of the respective unidirectional latch cir cuit,

-- the source of the fifth transistor is cou pled to the upper voltage rail,

-- the drain of the fifth transistor is cou pled to the drain of the sixth transistor,

-- the source of the sixth transistor is cou pled to the drain of the enabler transistor,

-- the gates of the fifth and third transis tors are coupled together and constitute the latch clock input of the respective unidirectional latch circuit,

-- the gates of the fourth and sixth transis tors are coupled together,

-- the source of the seventh transistor is coupled to the higher voltage rail, the drain of the seventh transistor is coupled to the drain of the eighth transistor, the source of the eighth transistor is coupled to the lower voltage rail,

-- the gates of the seventh and eighth tran sistors are coupled together, -- a point between the drain of the seventh transistor and the drain of the eighth transistor is coupled to the gates of the fourth and sixth transis tors,

- the output of the respective unidirectional latch circuit is constituted by a coupling to the gates of the seventh and eighth transistors, the drains of the fifth and fourth transistors, and the drains of the sixth and second transistors.

This involves the advantage that the timing event detector circuit can be implemented with a rela tively low number of transistors, saving silicon area and lowering power consumption.

According to an embodiment the timing event detector circuit comprises a control signal input and is configured to respond to a first control signal value in said control signal input by resetting said timing event observation signal at a predetermined mo ment during each pulse cycle in said triggering sig nal, and respond to a second control signal value in said control signal input by maintaining said timing event observation signal for the duration when said second control signal value appears at said control signal input. This involves the advantage that the timing event detector circuit can be made DFT compati ble.

According to an embodiment the timing event detector circuit is configured to reset the stored values to fixed default values at the end of a detec tion window, said end of the detection window being defined in relation to the triggering signal and tak ing place after the allowable time limit. This in volves the advantage that the monitoring cycle can be conveniently restarted for each moment when timing events can occur.

According to a third aspect there is provided a microelectronic circuit that comprises a processing path that comprises logic units and register circuits, of which said register circuits are configured to tem porarily store output values of said logic units in synchronism with a triggering signal. The microelec tronic circuit comprises at least one timing event de tector circuit of the kind described above, said tim ing event detector circuit being associated with one of said register circuits and configured to produce a timing event observation signal as a response to a change in a digital value at an input of the associat ed register circuit that took place later than an al lowable time limit defined by the triggering signal.

According to a fourth aspect there is provid ed a method for operating a microelectronic circuit. The method comprises:

- temporarily storing, in synchronism with a triggering signal, a digital value in a register cir cuit,

- storing, in relation to an allowable time limit defined by said triggering signal, a correspond ing momentary value of said digital value in differen tial form that comprises said momentary value and its complement value,

- toggling, during a timing event detection window following said allowable time limit, any of said stored momentary value or its stored complement value so that each of said stored momentary value or its stored complement value is only toggled in re sponse to observing the digital value change in re spective one direction,

- comparing, during said timing event detec tion window, said stored momentary value to its stored complement value and

- outputting a timing event observation sig nal in response to said comparing showing that said stored momentary value and its stored complement value have become equal. According to a fifth aspect there is provided a method for operating a microelectronic circuit. The method comprises:

- temporarily storing, in synchronism with a triggering signal, a digital value in a register cir cuit,

- storing, in relation to an allowable time limit defined by said triggering signal, a correspond ing momentary value of said digital value in two cop ies,

- toggling, during a timing event detection window following said allowable time limit, any of said two copies so that each copy is only toggled in response to observing the digital value change in re spective one direction,

- comparing, during said timing event detec tion window, said two copies and

- outputting a timing event observation sig nal in response to said comparing showing that said stored momentary value and its stored complement value have become different.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this specification, illus trate embodiments of the invention and together with the description help to explain the principles of the invention. In the drawings:

Figure 1 illustrates a monitor circuit asso ciated with a register circuit,

Figure 2 illustrates a monitor circuit asso ciated with a register circuit,

Figure 3 illustrates a logic gate level im plementation of an exemplary monitor circuit Figure 4 illustrates a state diagram of a monitor circuit,

Figure 5 illustrates a timing diagram of sig nals in a monitor circuit,

Figure 6 illustrates a timing diagram of sig nals in a monitor circuit,

Figure 7 illustrates a transistor-level im plementation of a monitor circuit,

Figure 8 illustrates an alternative implemen tation of a monitor circuit,

Figure 9 illustrates a method, and Figure 10 illustrates a method.

DETAILED DESCRIPTION

In the following, microelectronic circuits and methods for their designing and operating will be described. A typical microelectronic circuit comprises a plurality of logic units and register circuits, ar ranged into a plurality of processing paths. A pro cessing path is a sequence of circuit elements through which digital data may pass, so that it gets processed in logic units and temporarily stored in register cir cuits that are located between consecutive logic units on said processing paths. The software that the micro electronic circuit executes defines, which processing paths are used at any given time and in which way.

Fig. 1 illustrates a register circuit 101 and an associated monitor circuit 102. A data input of the register circuit 101 is marked with the letter D, and a data output of the register circuit 101 is marked with the letter Q. The register circuit 101 and its associated monitor circuit 102 may be part of a pro cessing path in a microelectronic circuit, so that a preceding element on the processing path produces the digital value that appears at the data input D and a subsequent element on the processing path receives the digital value that appears at the data output Q. Tem porary storing of data in the register circuit 101 takes place in synchronism with a clock pulse signal CKP, which can be called a clock signal for short. As the clock signal can be said to trigger the temporary storing of data, it may also be referred to as a trig gering signal. The monitor circuit 102 may be alterna tively called a timing event detector circuit.

In order to ensure correct operation of the microelectronic circuit, every change in the digital value that is to be temporarily stored in the register circuit 101 must take place before a respective allow able time limit defined by the clock signal CKP (or, more generally, defined by the appropriate triggering signal). It is common to consider e.g. a rising and/or falling edge in the clock signal CKP as the allowable time limit, but it is possible that the actual allowa ble time limit does not coincide exactly with such an edge, due to e.g. the finite time it takes for semi conductor switches to change from non-conductive to conductive state and vice versa. For the purpose of this description it is sufficient to assume that a known relationship exists between the form of the triggering signal and the occurrence of an allowable time limit.

The purpose of the monitor circuit 102 is to produce a timing event observation signal TEO as a re sponse to a change in a digital value at the input D of the associated register circuit 101 that took place later than the allowable time limit defined by the triggering signal (clock signal) CKP. For this pur pose, the monitor circuit 102 comprises a data input 103 configured to receive the digital value D, a clock signal input 104 configured to receive the triggering signal CKP, and a timing event observation output 105 configured to output the timing event observation sig nal TEO. The monitor circuit 102 is configured to store, in relation to the allowable time limit, a cor responding momentary value of the digital value D in differential form. This means that the monitor circuit 102 is configured to store both the momentary value of the digital value D and its complementary value. In side the monitor circuit 102 the actual momentary val ue is marked as D, and the complementary value is marked as ~D (tilde-D). In order to produce the com plementary value ~D, the monitor circuit 102 of fig. 1 is schematically shown to comprise an inverter 106 coupled to the data input 103.

The two parallel circuit elements 107 and 108 that are used to temporarily store the data value D and its complementary value ~D are called unidirec tional latch circuits in fig. 1. For the purpose of this description, a unidirectional latch circuit is a circuit element configured to store its input data at the beginning of an enabling pulse in a triggering signal, and toggle its output only if its input data changes value in a predetermined direction during the enabling pulse in the triggering signal. The output signals from the unidirectional latch circuits 107 and 108 are marked as A and B respectively. For simplici ty, we may assume here that A and B are directly the digital values that were last stored into the respec tive unidirectional latch circuits 107 and 108.

In the example embodiment of fig. 1 the clock signal CKP acts as the triggering signal to both uni directional latch circuits 107 and 108. As an example, let us assume that an enabling pulse of the kind meant above is an active pulse in the clock signal CKP (i.e. CKP=1). Let us further assume that the unidirectional latch circuits 107 and 108 are only responsive to 0 -> 1 changes in their input data; in other words, they are unidirectional in the rising direction. If the digital value D was 0 at the rising edge of the clock signal CKP, the first unidirectional latch 107 stores D = 0 and the second unidirectional latch 108 stores ~D = 1. The stored values become visible at their outputs, i.e. A = 0 and B = 1. If now the digi tal value D changes from 0 to 1 while the clock signal CKP remains high, the upper unidirectional latch cir cuit 107 toggles its stored value, because it sees a 0 -> 1 change in its input data. To the contrary, the lower unidirectional latch circuit 108 does not toggle its stored value, because it sees a 1 -> 0 change in its input data. As a result, after the 0 -> 1 change in the digital value D that occurred during the ena bling pulse in the clock signal CKP, the outputs of the unidirectional latch circuits 107 and 108 are A = 1 and B = 1.

As another example, we may maintain all other assumptions as above but assume that the digital value D was 1 at the rising edge of the clock signal CKP and fell to 0 during the active clock pulse. Thus the first unidirectional latch 107 initially stored D = 1 and the second unidirectional latch 108 stored ~D = 0. The stored values again became visible at their out puts, i.e. A = 1 and B = 0. When the digital value D changes from 1 to 0 while the clock signal CKP remains high, the upper unidirectional latch circuit 107 does not toggle its stored value, because it sees a 1 -> 0 change in its input data. The lower unidirectional latch circuit 108 does toggle its stored value, be cause it sees a 0 -> 1 change in its input data. As a result, after the 1 -> 0 change in the digital value D that occurred during the enabling pulse in the clock signal CKP, the outputs of the unidirectional latch circuits 107 and 108 are again A = 1 and B = 1.

Generalizing that above we may say that the monitor circuit 102 is configured to toggle, during a timing event detection window following the allowable time limit, one of the stored momentary value or its stored complement value in response to an observed change of the digital value D. Said toggling is condi tional so that each of the stored momentary value or its stored complement value is only toggled in re sponse to observing the digital value D change in re spective one direction: one of the stored values tog gles if the digital value D changes in a first direc tion, and the other of the stored values toggles if the digital value changes in the second, opposite di rection during the timing event detection window.

The comparator 109 in the monitor circuit represents the ability to compare, during the timing event detection window, the stored momentary value to its stored complement value. As was explained above, one of these may toggle during the timing event detec tion window if there is a corresponding change in the digital value D during the timing event detection win dow. The output TEO comes from the comparator 109; the comparator 109 will produce a timing event observation signal in response to the comparing showing that the stored momentary value and its stored complement value have become equal.

The operation of the monitor circuit 102 fol lows essentially the same lines also in another exam ple where the unidirectional latch circuits 107 and 108 are only responsive to 1 -> 0 changes in their in put data; in other words, they are unidirectional in the falling direction. In this case, if the digital value D was 0 at the rising edge of the clock signal CKP, the first unidirectional latch 107 again stores D = 0 and the second unidirectional latch 108 stores ~D = 1, so that initially A = 0 and B = 1. If now the digital value D changes from 0 to 1 while the clock signal CKP remains high, the upper unidirectional latch circuit 107 does not toggle its stored value, because it sees a 0 -> 1 change in its input data. To the contrary, the lower unidirectional latch circuit 108 does toggle its stored value, because it sees a 1 -> 0 change in its input data. As a result, after the 0 -> 1 change in the digital value D that occurred during the enabling pulse in the clock signal CKP, the outputs of the unidirectional latch circuits 107 and 108 are A = 0 and B = 0. It is easy to show how the same result is arrived at if the digital value D was 1 at the rising edge of the clock signal CKP and then changed to 0 during the timing event detection window.

Fig. 2 illustrates another example that shares many features with that of fig. 1. However, the unidirectional latch circuits 207 and 208 are respon sive to changes of their input data in different di rections; hence the use of the tilde sign (~) in the second unidirectional latch circuit 208. There is no inverter between the data input 103 and the input of any of the unidirectional latch circuits 207 and 208. Thus the monitor circuit 202 of fig. 2 is configured to store, in relation to the allowable time limit, a corresponding momentary value of the digital value D in parallel double form that comprises two copies of the momentary value: one in the first unidirectional latch circuit 207 and the other in the second unidi rectional latch circuit 208.

Due to the mutually opposite reacting capa bility of the unidirectional latch circuits 207 and 208, the monitor circuit 202 is configured to toggle, during the timing event detection window following the allowable time limit, one of said copies of the stored momentary value in response to an observed change of the digital value D. The first copy, stored in the first unidirectional latch circuit 207, is only tog gled in response to observing the digital value D change in one direction. The second copy, stored in the second unidirectional latch circuit 208, is only toggled in response to observing the digital value change in the opposite direction. As an example, we may assume that the digital value D was D = 0 at the rising edge of the clock sig nal CKP. At the beginning of the timing event detec tion window this same value was stored in both unidi rectional latch circuits 207 and 208 and made to ap pear at their outputs, i.e. A = B = 0. If the first unidirectional latch circuit 207 was the one respon sive to 0 -> 1 changes in its input data, and if one occurred during the timing event detection window, the result would be A = 1 and B =0. If the digital value D was D = 1 at the rising edge of the clock signal CKP, A = B = 1 at first, and then a change 1 -> 0 occurred in the digital value D during the timing event detec tion window, the result would be A = 1 and B =0. As the arrangement is symmetric with respect to the in puts, it is trivial to consider the further example where the response directions of the unidirectional latch circuits 207 and 208 were switched.

In the embodiment of fig. 2 the monitor cir cuit 202 is configured to compare, using the compara tor 209 and during the timing event detection window, the stored copies of the momentary value. It is con figured to output a timing event observation signal TEO in response to the comparison showing that the stored copies of the momentary value have become une qual.

The functionality that has been explained above can be implemented in practice also with differ ent circuit elements than the unidirectional latch circuits 107, 108, 207, and 208, as is common with digital circuits: after having been taught a desired functionality it may be within the capability of the person skilled in the art to present several alterna tive implementations that differ in e.g. polarity of signals and the resulting need to use circuit elements such as inverters, properly selected logic gates, and the like. Figs. 1 and 2 show a possibility of taking the triggering signal (i.e. the clock signal CKP) or some derivative thereof also that part of the monitor circuit that does the comparing. This may result in advantages concerning e.g. the ensuring of strict syn chronism of also the comparing operation with the known features of the timing event detection signal. As an example, even if the temporary storing of copies and possible complement values of the digital value in circuit elements like the unidirectional latch cir cuits 107, 108, 207, and 208 (and the possible tog gling that depends on the selected directions of reac tion) may take place for the whole duration of an ac tive pulse in the clock signal CKP, it may be advanta geous to construct a separate, somewhat shorter clock pulse for the comparison. This would enable focusing the actual production of timing event observation sig nals to only a part of the active pulse in the clock signal. In other words, the actual timing event detec tion window can be delimited in a different way than the active pulse in the clock signal CKP.

Figs. 1 and 2 show also the possibility of directing other kinds of controlling signals to the monitor circuit, here in particular to that part thereof that does the comparison and produces the tim ing event observation signal. Control signal input 110 can be used for such other kinds of control signals. Examples of such other kinds of controlling signals and their use are discussed in more detail later in this text.

Fig. 3 illustrates an example of a monitor circuit, also called a timing event detector circuit, in which both of the first and second unidirectional latch circuits 107 and 108 are configured to toggle their output only if the corresponding input data changes value in a direction that is the same for both of them. The monitor circuit of fig. 3 comprises an inverter 106 between the data input 103 and one of the first and second unidirectional latch circuits 107 and 108. Thus, the monitor circuit of fig. 3 implements similar functionality as that explained above with reference to fig. 1, storing the momentary value of the digital value D in the differential form that com prises the momentary value D as such in the first uni directional latch circuit 107 and its complement value ~D in the second unidirectional latch circuit 108.

The detailed structure selected for the first and second unidirectional latch circuits 107 and 108 is such where the input of the unidirectional latch circuit comes to one input of an OR gate. The output of the OR gate goes to one input of a NAND gate, to the other input of which comes the clock signal CKP. The output of the NAND gate constitutes the output of the unidirectional latch circuit. An inverted version thereof is taken to the other input of the OR gate. This type of a unidirectional latch circuit reacts on ly to 0 -> 1 changes in its input. It should be noted that the output of this kind of an unidirectional latch circuit is actually the inverse of the digital value that it read in at the rising edge of the clock signal CKP, but this has no significance to the dis cussion here because the following comparisons are in any case only sensitive to whether the two compared values are the same or not.

Fig. 4 illustrates the operation of the moni tor circuit of fig. 3 in the form of a state diagram. Before the rising edge of the clock pulse CKP, the circuit is in the leftmost state 401, where A = 1, B = 1, and TEO = 0. The clock pulse becoming active (CKP) causes a transition either to state 402 or to state 403, depending on the value of the digital signal D: here a value D = 0 (marked as ~D) causes a transition to state 402, while a value D = 1 (marked as D) causes a transition to state 403. As explained above, the particular structure selected for the unidirectional latch circuits 107 and 108 in fig. 3 makes their out puts to be inverted with reference to their inputs, so in state 402 A = 1, B = 0 and TEO = 0, while in state 403 A = 0, B = 1, and TEO = 0.

If now the digital value D changes while the clock signal CKP is still active, a further transition to state 404 takes place. The upper intermediate state 402 was the result of the digital signal having been D = 0 in the beginning of the active clock pulse, so the transition from there to the rightmost state 404 oc curs if the digital value D changes to 1 while still CKP = 1. Similarly, the lower intermediate state 403 was the result of the digital signal having been D = 1 in the beginning of the active clock pulse, so the transition from there to the rightmost state 404 oc curs if the digital value D changes to 0 while still CKP = 1. In any case, in state 404 A = B = 0, which results in the comparator 109 setting TEO = 1.

The line labeled TMTEOH (Test Mode; Timing Event Observation; High) in fig. 3 is an example of a control signal of the kind the possible existence of which was briefly mentioned above. It is also a mani festation of the circuit in fig. 3 being DFT compati ble. If the value of TMTEOH is low, the TEO signal will reset to TEO = 0 at the falling edge of each clock pulse. If, however, the value of TMTEOH is high, a TEO signal that was once set to TEO = 1 will remain that way until the control signal TMTEOH goes low sim ultaneously with the clock signal CKP being low. Both of these possibilities are represented in fig. 4 by the transition from state 404 to the initial state 401, which takes place under the condition -CKP & -TMTEOH (which means that CKP = 0 and TMTEOH = 0 sim ultaneously).

The dependency on the value of TMTEOH may be generalized so that the monitor circuit is configured to respond to a first control signal value in its con trol signal input 110 by resetting the timing event observation signal at a predetermined moment during each pulse cycle in the triggering signal. The monitor circuit is also configured to respond to a second con trol signal value in the control signal input by main taining the timing event observation signal for the duration when that second control signal value appears at the control signal input.

Figs. 5 and 6 illustrate examples of signal timing in certain cases, assuming again that the moni tor circuit is of the kind illustrated above in fig. 3. In fig. 5, the active clock pulses that begin at moments 501 and 502 were both preceded by timely changes in the digital value D, so the condition of having the A and B values unequal is maintained throughout the duration of the respective active clock pulses. At moment 503 a further clock pulse begins, but the change in the digital signal D occurs only slightly later, at moment 504. As the change in the digital signal D was 0 -> 1, the first unidirectional latch circuit toggles but the second unidirectional latch circuit does not, causing A = B = 0, which in turn makes the TEO signal go high. No TMTEOH signal is present in fig. 5, so the TEO signal resets to TEO = 0 at each falling edge of the clock signal CKP. A simi lar cycle of events follows at moments 505 and 506, with the exception that since the late-arriving change in the digital value D is now 1 -> 0, the first unidi rectional latch circuit does not toggle but the second unidirectional latch circuit does. The result is of course again A = B = 0, which in turn makes the TEO signal go high.

In fig. 6 the cycle of events at moments 601, 602, 603, and 604 is similar to that at moments 503, 504, 505, and 506 in fig. 5, because the TMTEOH signal (which is now present) remains low. Before moment 605, the TMTEOH signal goes high. When a late change in the digital value D arrives at moment 606, the first re sult is A = 0, B = 0, and TEO = 1 just like at moment 602. However, as long as the high value of TMTEOH pre vails, it prevents any further changes in the TEO sig nal, so whether or not there occurs a timing event al so at moment 608 is actually of no importance. In the example of fig. 6 the TMTEOH signal eventually goes low before the falling edge in the clock signal CKP at moment 609, which results in resetting the TEO signal at moment 609.

So-called standard cell implementations can be used to construct a transistor-level implementation of any microelectronic circuit, carefully following a presentation of its functionality as a combination of ordinary logic gates. A standard cell is a group of transistor and interconnect structures that provides a boolean logic function (e.g., AND, OR, XOR, XNOR, in verters) or a storage function (flipflop or latch). The simplest cells are direct representations of the elemental NAND, NOR, and XOR boolean function, alt hough cells of much greater complexity can also be used such as a various adders, multiplexed flip-flops, and the like.)

Fig. 7 illustrates an example of how a simi lar functionality as that explained above with refer ence to figs. 1 and 3-6 can be implemented in practice without standard cell implementations. For comparison, widely used standard cell CMOS implementations of log ic gates such as those in fig. 3 may include two tran sistors for an inverter; four for a NAND gate; and six for an OR gate. Using such standard cell implementa tions the circuit of fig. 3 would take 40 transistors. The example implementation in fig. 7 includes only 27 transistors.

The two transistors M9 and M10 between the upper and lower voltage rails VDD and VSS in fig. 7 constitute the inverter 106 that produces the comple ment value ~D of the digital value D. As such, this configuration follows what is also a standard cell CMOS implementation of an inverter, which takes only two transistors anyway.

The transistor-level implementations of the unidirectional latch circuits 107 and 108 are identi cal in fig. 7 when one notes that the transistor M3 is common to them both. Transistor M3, the source of which is coupled to the lower voltage rail VSS, may be called the enabler transistor, because a high value of the clock signal CKP at its gate enables the active operation of the unidirectional latch circuits 107 and 108. Similarly, transistor M5 in the first unidirec tional latch circuit 107 and transistor M15 in the second unidirectional latch circuit 108 may be called disabler or reset transistors, because a low value of the clock signal CKP at their gate connects the re spective output (A in the first unidirectional latch circuit 107, B in the second unidirectional latch cir cuit 108) directly to the higher voltage rail VDD and disables the respective unidirectional latch circuit by making transistor M8 or M18 respectively conduc tive. For completeness, the illustrated CMOS implemen tation of a unidirectional latch circuit is explained in the following with reference to the first unidirec tional latch circuit 107 in fig. 7.

The source of PMOS Ml is coupled to the high er voltage rail VDD. The drain of Ml is coupled to the source of PMOS M4, the drain of which is coupled to the drain of NMOS M2, the source of which is coupled to the drain of the enabler NMOS M3. The gates of Ml and M2 are coupled together and constitute the data input of the unidirectional latch circuit. The source of PMOS M5 is coupled to VDD. The drain of M5 is cou pled to the drain of NMOS M6, the source of which is coupled to the drain of the enabler NMOS M3. The gates of M5 and M3 are coupled together and constitute the clock input of the unidirectional latch circuit. The gates of M4 and M6 are coupled together. The source of PMOS M7 is coupled to VDD. The drain of M7 is coupled to the drain of NMOS M8, the source of which is cou pled to VSS. The gates of M7 and M8 are coupled to gether. The point between the drain of M7 and the drain of M8 is coupled to the gates of M4 and M6. The output of the unidirectional latch circuit is consti tuted by a coupling to the gates of M7 and M8; the drains of M5 and M4; and the drains of M6 and M2.

For completeness, the illustrated CMOS imple mentation of a comparator 109 is explained in the fol lowing. The sources of PMOS's M21, M22, M25, and M28 are coupled to VDD. The sources of NMOS's M24 and M27 are coupled to VSS. The gates of M21 and M24 are cou pled together and constitute the TMTEOH control input of the comparator 109. The drains of M21 and M22 are coupled to the gates of M25 and M27 and to the drain of NMOS M23. The gates of M22 and M23 are coupled to gether. The source of M23 is coupled to the drain of M24. The drain of M25 is coupled to the drain of NMOS M26. The drain of M28 is coupled to the source of PMOS M29. The drain of M29 is coupled to the drain of NMOS M30. The sources of M26 and M30 are coupled to the drain of M27. The gates of M28 and M26 are coupled to gether and constitute a first data input A of the com parator 109. The gates of M29 and M30 are coupled to gether and constitute the second data input B of the comparator 109. The TEO output of the comparator 109 is a connection to the drains of M29 and M25, the drains of M30 and M26, and the gates of M22 and M23.

The storing of the digital value D in differ ential form that comprises a momentary value and its complement value is implemented with voltage-mode CMOS logic in fig. 7. As a comparison, fig. 8 illustrates a monitor circuit of the kind known from a previous pa- tent application number PCT/FI2017/050290, published as W02018/193150, which stores a digital value D at the rising edge of a clock signal CLK in differential form using current-mode logic. There is also the fun damental difference that in the prior art implementa tion of fig. 8 neither the stored momentary value nor its complement value can change ("or toggle") during the active pulse in the clock signal CLK; at the ris ing edge of the clock signal they are stored as VC1 and VC2, both of which remain constant until the end of the active pulse in the clock signal CLK. The actu al detection of a timing event during the active pulse in the clock signal CLK takes place in the XNOR gate 801, which compares the stored complement value VC2 to the actual digital value D at the input of the monitor circuit. If these two become equal it means that the actual digital value D has changed from what it was at the beginning of the active clock pulse, which indi cates a timing event.

The voltage-mode logic utilized in fig. 7 in volves inherently higher reliability than the current mode logic of fig. 8, because the latter includes floating nodes: in fig. 8, when the clock signal CLK is low, nodes 802 and 803 are floating independent of the digital value D. When CLK and D are both high, node 802 is floating, and when CLK is high and D is low, node 803 is floating. In particular if very low- voltage operation is attempted, floating nodes may cause undesired logic states due to leakage.

The use of unidirectional latch circuits for storing the momentary value and its complement value of D allows the implementation of fig. 7 to have fewer transistors than if standard latch circuits would be used. Considering the first unidirectional latch cir cuit 107 for example, in comparison to a standard latch circuit it does not have a pull-up network con nection from the output of the inverter formed by transistors Ml, M2, and M3 to the output A. The unidi rectional functionality of the latch circuits also en ables savings in the transistor count of the circuitry the task of which is to activate the TEO signal in the case of a detected timing event. As a comparison, if one would count 11 transistors for a CMOS implementa tion of an XOR or XNOR gate (as in the widely used logic circuits CD4070B and CD4077B of Texas Instru ments for example), 12 transistors for a CMOS imple mentation of a two-input AND gate (like in the circuit CD4081B of Texas Instruments) and 2 transistors for an inverter, an implementation of the circuit in fig. 8 could require as many as 49 transistors. That is more than even the standard cell implementation of the functionality of fig. 3, which was earlier in this text calculated to have 40 transistors. Naturally, the 27-transistor implementation in fig. 7 is even more efficient in transistor count.

Fig. 9 illustrates a method embodiment that corresponds to the description given above with refer ence to figs. 1 and 3-7. As a beginning point of the method fig. 9 shows the opening of the detection win dow at step 901. The detection window is related to the task of monitoring for timing events, which in turn is associated with temporarily storing, in syn chronism with a triggering signal, a digital value in a register circuit. The temporary storing of the digi tal value should take place before the opening of the detection window in step 901. A change in the digital value after the opening of the detection window, i.e. during the time the detection window remains open, represents a timing event. To be quite exact, a timing event is a change in the digital value later than an allowable time limit defined by the triggering signal.

As illustrated by steps 902 and 903, the method comprises storing, in relation to the allowable time limit defined by the triggering signal, a corre- sponding momentary value of the digital value in dif ferential form that comprises the momentary value (step 902) and its complement value (step 903). The checks in steps 904 and 905 involve monitoring for change in a predefined direction. Only if one is de tected, the corresponding stored value is toggled cor respondingly at either step 906 or step 907. This part of the method may be characterized as toggling, during a timing event detection window following the allowa ble time limit, any of said stored momentary value or its stored complement value so that each of said stored momentary value or its stored complement value is only toggled in response to observing the digital value change in respective one direction.

Step 908 represents comparing, still during the timing event detection window, the stored momen tary value to the stored complement value. If no tim ing event has occurred during this detection window so far, but the detection window is still open, there oc curs a transition through step 910 back to the moni toring steps 904 and 905. A positive finding at step 908 means that exactly one of the stored values has toggled, and the values have become equal. As repre sented by step 909 the method comprises outputting a timing event observation signal in response to the comparing of step 908 showing that the stored momen tary value and its stored complement value have become equal.

The method of fig. 9 ends when the detection window closes at step 911, either any time after acti vating the TEO signal at step 909 or because the end of the detection window was found as the positive con clusion of step 910. As a possible addition, fig. 9 illustrates checking at step 912 whether a control signal (called here the TMTEOH signal) is active. If not, the TEO signal is reset at step 913 before re turning to step 901 at the beginning of the next de- tection window. If the control signal is active, the return to step 901 takes place without resetting the TEO signal.

Fig. 10 illustrates a method embodiment that corresponds to the description given above with refer ence to fig. 2. The method of fig. 10 is in many re spects similar to that of fig. 9, but there are dif ferences related to the storing and comparing stages. The storing steps 1002 and 1003 comprise storing, in relation to the allowable time limit defined by the triggering signal, a corresponding momentary value of the digital value in two copies. The monitoring steps 1004 and 1005 are complements of each other in the sense that one of them monitors for changes in one di rection while the other monitors for changes in the other, opposite direction. These monitoring steps and their associated toggling steps 906 and 907 may be characterized as toggling, during a timing event de tection window following the allowable time limit, any of the two copies so that each copy is only toggled in response to observing the digital value change in re spective one direction. Steps 1008 and 909 comprise comparing, during the timing event detection window, the two copies and outputting a timing event observa tion signal in response to said comparing showing that the stored momentary value and its stored complement value have become different.

It is obvious to a person skilled in the art that with the advancement of technology, the basic idea of the invention may be implemented in various ways. A feature typical to logic circuits is that log ic functionalities can be replaced with structurally different but operationally equivalent functionali ties, by taking into account the possible inversions and logic conversions that are needed. The invention and its embodiments are thus not limited to the exam- pies described above, instead they may vary within the scope of the claims.