Title:
TIMING RECOVERY CIRCUIT AND RECEIVER CIRCUIT PROVIDED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2013/065208
Kind Code:
A1
Abstract:
In the present invention, a timing recovery circuit is provided with the following: a clock generating circuit (10) for generating clock signals of different cycles by using first and second operation modes; phase compensation circuits (21a-21f) for outputting, in the first operation mode, a sample timing signal in which a phase between two clock signal phases is adjusted, and for outputting, in the second operation mode, either of two clock signals as a sample timing signal; sampling circuits (31a-31f) for latching a data signal using a sample timing signal; and a phase control circuit (40) for instructing selection of a clock signal and phase adjustment of the sample timing signal.
Inventors:
ARIMA YUKIO
SHINMYO AKINORI
SHINMYO AKINORI
Application Number:
PCT/JP2012/002429
Publication Date:
May 10, 2013
Filing Date:
April 06, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
ARIMA YUKIO
SHINMYO AKINORI
ARIMA YUKIO
SHINMYO AKINORI
International Classes:
H04L7/02
Domestic Patent References:
| WO2009069244A1 | 2009-06-04 | |||
| WO2007099678A1 | 2007-09-07 |
Foreign References:
| JP2002353947A | 2002-12-06 | |||
| JP2007067573A | 2007-03-15 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
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Claims: