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Patent Searching and Data


Title:
TRACK AND HOLD CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/200482
Kind Code:
A4
Abstract:
The present invention relates to an improvement to a track and hold circuit. A jitter-free track and hold function independent of signal amplitude is achieved by a circuit which fixes the sample voltage to the charge on a flying sampling capacitor and sets maintains that charge prior to isolation through applying application of the sample voltage to a utilization circuit. This may be done by adding an extra switch to the standard track and hold circuit and operating the switches in a timed sequence manner to provide the sample aperture based on the charge on the flying sampling capacitor common to the circuit.

Inventors:
SCHOBER SUSAN MARYA (US)
SCHOBER ROBERT C (US)
Application Number:
PCT/US2018/029084
Publication Date:
December 06, 2018
Filing Date:
April 24, 2018
Export Citation:
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Assignee:
CIRCUIT SEED LLC (US)
International Classes:
G11C27/02; H03M1/12
Attorney, Agent or Firm:
CIMINELLO, Dominic P. et al. (US)
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Claims:
AMENDED CLAIMS

received by the International Bureau on 01 November 2018 (01.11.2018)

1. A track and hold circuit having an input terminal, comprising: a. a plurality of switches; b. a capacitor having a first side and a second side; c. a controller connected to the plurality of switches in a manner to supply a sample voltage to a utilization circuit by sequencing the operation of the plurality of switches, wherein, i. at a first sequence, the control circuit configures the

plurality of switches to track an input voltage across the capacitor by referring to a common mode voltage; ii. at a second sequence, the control circuit configures the plurality of switches to isolate a charge on the capacitor; iii. at a third sequence, the control circuit configures the

plurality of switches to disconnect the input voltage from the capacitor; iv. at a fourth sequence, the control circuit configures the

plurality of switches to supply the voltage held on the capacitor as the sample voltage to the utilization circuit for processing.

2. A jitter free track and hold circuit comprising the circuit recited in claim 1.

3. A differential track and hold circuit having positive and negative input terminals, comprising: a. a first switch; b. a second switch; c. a first capacitor having a first side and a second side, the first side of the first capacitor is connected to the positive input terminal via the first switch; the second side of the first capacitor is connected via the second switch to a common mode voltage source; and the first side of the first capacitor is further connected to a utilization circuit; d. a third switch; e. a fourth switch; f. a second capacitor having a first side and a second side, the first side of the second capacitor is connected to the negative input terminal via the first switch; the second side of the second capacitor is connected via the second switch to the common mode voltage source; and the first side of the second capacitor is further connected to the utilization circuit; g. a controller connected to the first, second, third and fourth switches in a manner to supply a sample voltage to the utilization circuit by sequencing the closure of the first, second, third and fourth switches, wherein, i. at a first sequence, the first, second, third and fourth

switches are closed such that input voltages at the positive and negative input terminals are tracked across the first and second capacitors;

11. at a second sequence, the first and third switches are closed and the second and fourth switches are opened, such that charges on the first and second capacitors are isolated; 25 iii. at a third sequence, the first, second, third and fourth

switches are opened, such that the input voltages at the positive and negative input terminals are disconnected from the first and second capacitors; iv. at a fourth sequence, the first and third switches are opened and the second and fourth switches are closed, such that the voltages on the first and second capacitors are supplied as the sample voltage to the utilization circuit for processing.

4. A track and hold circuit having an input terminal, comprising: a plurality of switches; a charge capacitor, having top plate and bottom plate; and a control circuit that controls the plurality of switches to carry out a process comprising: a. tracking an input voltage by connecting the top plate of the charge

capacitor to the input terminal and the bottom plate of the charge capacitor to a common mode voltage source; b. isolating and capturing a sampled voltage on the charge capacitor by

disconnecting the bottom plate from the common voltage source; c. disconnecting the top plate of the charge capacitor from the input terminal to separate the input voltage; d. reconfiguring the capacitor by connecting the top plate of the charge

capacitor to a low impedance; and e. rearranging and reconnecting the bottom plate of the charge capacitor to the common mode voltage source in high impedance to compute and sample a hold voltage on the charge capacitor. 26

5. A track and hold circuit comprising:

a first switch; a second switch: a capacitor having a first side and a second side, said first side is connected to an input terminal via said first switch, said second side of said capacitor is connected via said second switch to a common mode voltage source, said first side of said capacitor is connected to a utilization circuit; and

27 a controller connected to said first and second switches in a manner to supply a sample voltage to said utilization circuit to operate said first switch and said second switch in a sequence comprising the steps of Tl , T2, T3, T4 and T5 as follows:

6. A jitter-free track and hold circuit comprising: | a capacitor having a first side and a second side; a first switch connected between an input terminal and said first side of said capacitor, said first side of said capacitor is connected to a utilization circuit; and 28 a second switch connected between said second side of said capacitor and a common mode signal source; and a controller connected to said first and second switches, said controller being responsive to a system command to supply a sample voltage to said utilization circuit for operating said first switch and said second switch in a sequence comprising the steps of Tl, T2, T3, T4 and T5 as follows: