Title:
TRACK AND HOLD CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/189602
Kind Code:
A1
Abstract:
Provided is a track and hold circuit that can lower power consumption while preserving the broadband unchanged (without narrowing the bandwidth) in a differential amplifier circuit. A track and hold circuit 1 comprising a differential amplifier circuit 10, a switch circuit 20, and a holding capacitor C21, wherein the differential amplifier circuit 10 includes: a first resistor R11 connected by one end to the collector electrode of a first transistor Q11 that constitutes part of a differential pair; a second resistor R12 connected by one end to the collector electrode of a second transistor Q12 that constitutes part of the differential pair; and a third resistor R13 to which the other end of the first resistor R11 and the other end of the second resistor R12 are connected, and which is connected between the other ends and a power supply VCC.
Inventors:
FUKUYAMA HIROYUKI (JP)
MIURA NAOKI (JP)
NOSAKA HIDEYUKI (JP)
MIURA NAOKI (JP)
NOSAKA HIDEYUKI (JP)
Application Number:
PCT/JP2019/013657
Publication Date:
October 03, 2019
Filing Date:
March 28, 2019
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H03M1/12; H03F3/45
Domestic Patent References:
| WO2010032726A1 | 2010-03-25 |
Foreign References:
| JPH07336225A | 1995-12-22 | |||
| JPH07115376A | 1995-05-02 | |||
| JPH09162721A | 1997-06-20 | |||
| JP2018014580A | 2018-01-25 |
Attorney, Agent or Firm:
MIYOSHI Hidekazu et al. (JP)
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