DESCRIPTION

A TRANSCONDUCTOR

The invention relates to transconductors, and particularly to low voltage transconductors.

WO 2004/073162 discloses an approach to enabling lower supply operation for CMOS analogue circuits.

The low voltage transconductor of WO 2004/073162 includes complementary PMOS and NMOS transistors having their source-drain paths connected in series between first and second voltage supply rails.

An output terminal is coupled to a junction of said series connected source-drain paths. Gate electrodes of the PMOS and NMOS transistors are coupled to an input node by way of a bias voltage supply circuit. The quiescent gate voltages of the PMOS and NMOS transistors are offset from the quiescent input voltage by equal and opposite bias voltages, thereby reducing the apparent threshold voltage of the PMOS and NMOS transistors by the value of the bias voltages.

The circuit above has been shown to work in the design of a channel filter for a wireless consumables system. However, some drawbacks to the approach are now apparent.

The network for generating the bias voltages must be designed with a high value of resistance so that the current passing through it is low, in order to reduce power consumption. This can create extra white noise from both resistors and from bias transistors. A capacitor may be needed to avoid the extra pole caused by the resistors and the gate capacitances of the PMOS and NMOS transistors, especially in higher frequency applications.

The currents in the bias transistors must be well matched to provide the correct bias voltages and to minimize output offset currents.

The discussion of a prior-published document in this specification should not necessarily be taken as an acknowledgement that the document is part of the state of the art or is common general knowledge.

An object of the invention may be to mitigate or overcome some or all of the above-described problems.

According to a first aspect of the invention, there is provided a transconductor circuit comprising a main transconductor including an output node and an input node for receiving an input signal; a bias control circuit being operable to produce higher and lower bias voltages at respective higher and lower outputs, the bias voltages being independent of the input signal; and a coupling network for coupling the input signal to the bias voltages and feeding the resulting level-shifted signals to the main transconductor. By independent is meant that the bias voltages (as appearing at the outputs of the bias control circuit) and the input signal are not combined to form a level-shifted signal, as is the case in the prior art arrangement.

By producing the bias voltages independently of the input signal, several advantages can be obtained. Firstly, producing the bias voltages independently of the input signal provides the opportunity to determine whether the bias voltages are incorrect and therefore resulting in output offset currents, and consequently to provide a means of control whereby the output offset currents are reduced. Secondly, the input signal can be coupled to the bias voltages in the main transconductor by an RC network, thereby improving the noise performance of the transconductor.

Thirdly, the same bias control circuit can be used to supply the bias voltages to multiple transconductors, thereby saving on circuit space and reducing the number of noise-producing components which a number of bias voltage supply circuits would entail.

Furthermore, the capacitors of the prior art are not needed in the bias control circuit because it does not handle signals, only dc.

In respect of the first advantage, in a preferred embodiment of the invention, the main transconductor is connected between first and second voltage supply rails; and the bias control circuit is operable to control a voltage of the first voltage supply rail such that a quiescent current in the main transconductor is maintained at a desired quiescent current (J*).

Ideally, the various devices of the bias control circuit, which may include such things as bias transistors, current sources, resistors and capacitors, have parameters of the required value to generate the correct bias voltages. However, in the real world, imperfect IC processing and changes in environmental conditions such as temperature and ageing result in random mismatches between devices. Thus, when a quiescent input voltage is applied to the transconductor, the drain currents of the PMOS and NMOS transistors are not equal, resulting in a non-zero, dc output current, referred to as an output offset current. By controlling the voltage of the first voltage supply rail of the transconductor, the invention provides a way of significantly reducing the problems caused by such device mismatch. For example, if there is a positive output offset current in the main transconductor, the voltage of the first voltage supply rail is reduced in order to counteract that output offset current.

Although variations in the parameters of the transistors in the transconductor still cause offset errors, the total error is much less than with the prior art arrangement.

As the bias control circuit only deals with dc voltages, i.e. independently of signals, it is possible to match currents in the bias control circuit exactly using the feedback network described to produce little or no output offset error in the transconductors.

The bias control circuit preferably includes a bias voltage supply circuit for producing the bias voltages; a replica transconductor being connected between the first and second voltage supply rails and being supplied with the bias voltages; and a current matching circuit being operable to adjust the voltage of the first voltage supply rail such that a

current in the replica transconductor is maintained at the desired quiescent current.

By providing a replica transconductor, the effect of the bias voltages produced by the bias voltage supply circuit can be examined to determine whether an output offset current is being produced. This is only possible because the replica transconductor is not supplied with an input signal, instead dealing only with dc voltages. Based on the effect of the bias voltages on the replica transconductor, the current matching circuit makes appropriate adjustments to the voltage of the first voltage supply rail. As the main transconductor is also supplied by the first voltage supply rail, the effect of such control is to counteract output offset currents in the main transconductor.

In the preferred embodiment, the current matching circuit includes a source follower connected between the first voltage supply rail and a third voltage supply rail, the current matching circuit being operable to increase or decrease a voltage at a gate electrode of the source follower according to an output current of the replica transconductor.

Preferably, the current matching circuit includes a charge pump having an input connected to an output node of the replica transconductor and an output connected to the gate electrode of the source follower.

Alternatively, an OTA (operational transconductance amplifier) may be used in place of the charge pump for circuits in which the gate voltage of the source follower is below the third supply voltage. In this case, the current matching circuit (150) includes an operational transconductance amplifier having a first input connected to an output node of the replica transconductor, a second input receiving a quiescent input voltage, and an output connected to the gate electrode of the source follower.

The bias voltage supply circuit may include a PMOS current source, a resistor and a NMOS transistor connected in series between a third voltage supply rail and the second voltage supply rail, a drain electrode of the PMOS current source forming the higher output to supply the higher bias voltage and a drain electrode of the NMOS transistor forming the lower output to supply the lower bias voltage.

The drain electrode of the PMOS current source may be connected to a gate electrode of the NMOS transistor.

In respect of the second advantage, in the preferred embodiment of the invention, the coupling network includes first and second RC networks coupling the input signal to the bias voltages, each RC network having a cut-off frequency above which the input signal is not significantly attenuated by the coupling network. Although the bias control circuit may produce similar noise to that of the prior art arrangement, the noise is isolated by the RC networks (for frequencies above the cut-off frequency of the RC networks). In this way, the noise performance of the transconductor and its ability to block offsets are improved.

The main transconductor may include complementary PMOS and NMOS transistors connected in series between the first and second voltage supply rails. The first RC network may include a resistor being connected between a gate electrode of the PMOS transistor and a lower output of the bias control circuit supplying a lower bias voltage, and a capacitor being connected between the gate electrode of the PMOS transistor and the input node of the main transconductor. The second RC network may include a resistor being connected between a gate electrode of the NMOS transistor and a higher output of the bias control circuit supplying a higher bias voltage, and a capacitor being connected between the gate electrode of the NMOS transistor and the input node. Preferably, the capacitance of each capacitor is significantly larger than a gate capacitance of the PMOS and NMOS transistors, in order to minimise attenuation and consequent increase in power consumption.

Preferably, the capacitors comprise poly-Nwell capacitors with their gate electrodes connected respectively to gate electrodes of the PMOS and NMOS transistors and their common drain-source-Nwells connected to the input node of the transconductor. Thus, the capacitors operate in cut-off and eliminate attenuation from Nwell bottom plate capacitance.

Alternatively, any other type of capacitor available in the CMOS process may be used.

In respect of the third advantage, the transconductor circuit preferably includes at least one further main transconductor, the bias control circuit supplying the or each further main transconductor with the bias voltages.

In this way, the bias control circuit creates the bias voltages once, and the same bias voltages are reused for multiple transconductors, thereby avoiding the need for multiple bias control circuits each having the ability to produce noise and offsets as a result of imperfect components. The bias voltages are added to the input signal by the coupling network to produce the same level-shifted signals that are applied to the transconductor in the prior art arrangement.

According to a second aspect of the invention, there is provided a balanced transconductor circuit comprising first and second transconductor circuits according to the first aspect of the invention and operated differentially.

The balanced transconductor circuit may include a common-mode feedback circuit, useful in stabilising the first and second transconductors.

In order that the invention may more readily be understood, a description is now given, by way of example only, reference being made to the accompanying drawings, in which:-

Figures 1 (a) and 1 (b) are schematic diagrams of prior art transconductors;

Figure 2(a) is a schematic diagram of a single-ended transconductor circuit according to the invention;

Figure 2(b) is a schematic diagram of a first embodiment of a bias control circuit according to the invention; Figure 3 is a schematic diagram of a balanced transconductor circuit according to the invention;

Figure 4 is a graph showing the simulated transconductance of the balanced transconductor circuit of Figure 3;

Figure 5 is a schematic diagram of a second embodiment of a bias control circuit according to the invention.

Figure 1 (a) shows a known, single-ended CMOS transconductor 10 including a PMOS transistor 12 and an NMOS transistor 14 connected in series between first and second voltage supply rails 16, 18. The transconductor 10 includes an input node 20 connected to gate electrodes of each of the PMOS and NMOS transistors 12, 14, and an output node 22 connected between the PMOS and NMOS transistors 12, 14. Assuming identical parameters for the PMOS and NMOS transistors

12, 14, the design is optimal when the transistor gate overdrive voltage is set to V _g t = Vt/2 where Vt is the threshold voltage, and the analogue supply is set to Vdda = 3.V _t . The quiescent input voltage is then V _cm = 3.V _t /2 = Vdda/2. The transistors 12, 14 should be sized so that they have equal transconductance, i.e. G _mp = G _mπ = 2.JA/ _g t where J is the quiescent bias current, and the overall transconductance is G _m = 2.G _mp = 2G _mπ .

Figure 1 (b) shows the low voltage transconductor circuit 40 proposed in WO 2004/073162. The transconductor circuit 40 is identical to that of Figure 1 (a) except that it includes a bias voltage supply circuit 42 being operable to add respective bias voltages to the input signal V _in to produce two level-shifted signals V _in + V _cm - V _b and V _in + V _cm + V _b , where Vcm is the quiescent input voltage, which are applied to the gate electrodes of the PMOS and NMOS transistors 12, 14 for low voltage operation. Clearly, the bias voltages from their creation are inextricably linked to the input signal, and are not at any stage independent of the input signal. In effect, the arrangement connects a 'battery' with voltage V _b =lι _> R in series with the gate electrodes of both the PMOS and NMOS transistors 12, 14 with a polarity to reduce the effective gate threshold voltage to Vt ^* = Vt-Vb. This circuit is optimally designed when the gate overdrive is set to V _g t ^* = k.Vgt where 3.Vt ^* = k.Vdda- With the quiescent current set to J ^* = J/k, the transconductance

becomes G _m ^* = G _m /k ² . The power consumption is unchanged because P ^*

Ideally, with the PMOS and NMOS transistors 12, 14 having identical parameters, the transistors of the bias voltage supply circuit 42 supplying equal currents and the resistors having identical value, when the input voltage is V _cm = Vdda/2, the drain currents of the PMOS and NMOS transistors 12, 14 are equal and the output current is I ₀ Ut=O, i.e. there is zero offset current. In the real world, individual devices have spreads resulting in device mismatches so that when V _cm =V _d da/2, the drain currents are not equal and l _ou t does not equal zero. This (dc) output current that flows in a particular circuit is called its offset current. In a balanced circuit, this may be resolved into common-mode and differential-mode components of offset current.

As the dc bias currents Ib from the transistors of the bias voltage supply circuit 42 flow through the resistors, the 'battery' voltages are If the currents or the resistors are unequal then so are the 'battery' voltages. The currents are determined mainly by the gate voltages and the parameters of the bias transistors. Deviations from the ideal result from imperfect IC processing which results in random mismatches between devices, and from changes in environmental conditions such as temperature changes and ageing.

In a system, for example a filter, every transconductor cell has this level-shifting capability and the noise and offsets produced by the imperfect transistors in the bias voltage supply circuit 42 occur many times.

Figure 2(a) shows a transconductor circuit according to the invention.

The transconductor circuit includes a main transconductor 100 having complementary PMOS and NMOS transistors 12, 14, the drain electrodes of which are connected together and to an output node 22. The source electrodes of the PMOS and NMOS transistors 12, 14 are connected respectively to first and second voltage supply rails 16, 18.

The transconductor circuit includes a coupling network 80 for coupling the input signal to the bias voltages and feeding the resulting level-shifted signals to the main transconductor 100. The coupling network 80 includes first and second RC networks 60, 70 coupling the input signal Vin to the bias voltages V _cm + V _b , V _cm - V _b , each RC network 60, 70 having a cut-off frequency above which the input signal is not significantly attenuated by the coupling network.

The first RC network 60 includes a resistor 62 connected between the gate of the PMOS transistor 12 and the lower output 132 of the bias control circuit 110, and a capacitor 64 connected between the gate of the PMOS transistor 12 and the input node 20. The second RC network 70 includes a resistor 72 connected between the gate of the NMOS transistor 14 and the higher output 134 of the bias control circuit 110, and a capacitor 74 connected between the gate of the NMOS transistor 14 and the input node 20. The resistors 62, 72 each have resistance Ri, and the capacitors 64, 74 each have capacitance Ci.

Figure 2(b) shows the bias control circuit 110. The bias control circuit 110 includes a bias voltage supply circuit 50 and a current matching circuit 150. The bias control circuit 110 is unaffected by the input signal, regardless of its frequency.

The bias voltage supply circuit 50 includes a PMOS current source 54, the source electrode of which is connected to a third voltage supply rail 19, and the gate electrode of which is connected to a reference voltage V _p . The drain electrode of the PMOS current source 54 is connected via a resistor 58, having a resistance 2R, to the drain electrode of a NMOS transistor 56, the source electrode of which is connected to the second voltage supply rail 18 and the gate electrode of which is connected back to the drain electrode of the PMOS current source 54. The connection between the gate of the NMOS transistor 56 and the drain of the PMOS current source 54 effectively 'diode' connects the NMOS transistor 56 so that it sinks the current from the PMOS current source 54. The sizing of

the PMOS current source 54 together with the bias current sets a higher bias voltage of V _C m ⁺ V _b at the higher output 134, which is at the drain of the PMOS current source 54. The resistor 58 and the bias current create a voltage drop of 2Vb, which sets a lower bias voltage of V _cm -Vb at the lower output 132, which is at the drain of the NMOS transistor.

The current matching circuit 150 includes a replica transconductor 160 comprising complementary PMOS and NMOS transistors 112, 114, which are identical to PMOS and NMOS transistors 12, 14 of the main transconductor 100. The drain electrodes of the PMOS and NMOS transistors 112, 114 are connected together and to an output node 122. The source electrode of the PMOS transistor 112 is connected to the first voltage supply rail 16. The source electrode of the NMOS transistor 114 is connected to the second voltage supply rail 18. The gate electrode of the PMOS transistor 112 is connected to the lower output 132 and the gate electrode of the NMOS transistor 114 is connected to the higher output 134, the gate electrodes thus being fed with the lower and higher bias voltages. The current matching circuit 150 includes a charge pump 154 having its input connected to the output node 122 and its output connected to the gate electrode of a source follower 152, the source follower 152 being an NMOS FET. The source electrode of the source follower 152 is connected to the first voltage supply rail 16 and to the source electrode of the PMOS transistor 112. The drain electrode of the source follower 152 is connected to the third voltage supply rail 19. The charge pump 154 receives a clock input 156. Thus, the bias control circuit 110 provides higher and lower bias voltages in series with the gates of the PMOS and NMOS transistors 12, 14 so as to reduce their effective threshold voltages. The PMOS current source 54 generates the required bias current J ^* which flows through the resistor 58 into the NMOS transistor 56, which is identical to the NMOS transistor 114. With R = Vb/J ^* , this creates the higher and lower bias voltages V _cm ⁺ Vb and V _cm - Vb. When the bias voltages are applied to the PMOS and NMOS transistors 112, 114, an identical current J ^* is set up in

the NMOS transistor 114. The current matching circuit 150, including a loop with the charge pump 154 and source follower 152, ensures that the same bias current also flows in the PMOS transistor 112. This can be understood by considering the event in which the current in the PMOS transistor 112 is larger than J*. In that event, the output node 122 goes high and disables the charge pump 154, causing the voltage of the first voltage supply rail 16, V _dc ia, to fall until the current in the PMOS transistor 12 decreases to J ^* . Conversely, if the current in the PMOS transistor 112 is smaller than J ^* , the output node 122 goes low and enables the charge pump 154, causing Vdda to rise until the current in the PMOS transistor 12 increases to J ^* .

With the bias voltages V _cm - Vb and V _cm ⁺ Vb and the voltage of the first voltage supply rail 16 Vdda applied to the main transconductor 100, as shown in Figure 2(b), the required voltages are applied to the gates of the PMOS and NMOS transistors 12, 14 in order to generate the required quiescent current J*. The first and second RC networks 60, 70 transmit signals at frequencies significantly above W _C0 =1/RiCi to the gates of the PMOS and NMOS transistors 12, 14 but with an attenuation of Ci/(Ci + Cg), where C ₉ is the gate capacitance of the PMOS and NMOS transistors 12, 14. If 2.G _mp ^* = 2.G _mn ^* = G _m ^* (= GJk ² ), then the effective transconductance is G _m ^* eff = G _m ^* -Ci/(Ci + C ₉ ). The transconductance value can be restored to G _m ^* by increasing the widths of the PMOS and NMOS transistors 12, 14 by the factor (Ci + C ₉ )/Ci, but this increases the power consumption by the same factor. For the lowest power consumption, Ci » C ₉ is required. Signals with frequencies below W _co are attenuated, giving the main transconductor 100 the ability to block offsets and reduce low frequency noise. The capacitors 64, 74 preferably are made from poly-Nwell capacitance made from PMOS transistors with their gates connected to the gates of the PMOS and NMOS transistors 12, 14 and the common drain-source-Nwell connected to the input node 20. For practical values of V _b , this operates the capacitors 64, 74 in cut-off and eliminates the extra attenuation from Nwell bottom plate capacitance. The

resistors 62, 72 preferably are made from MOS transistors operated in their linear region, but may be any other type of resistor available in the CMOS process.

Figure 3 shows a balanced transconductor circuit 200 according to the invention.

The balanced transconductor circuit includes two parallel, single- ended transconductor circuits each in the form shown in Figure 2. The PMOS and NMOS transistors 12, 12', 14, 14' form the main transconductors 100, 100' while transistors P _c and N _c form a conventional common-mode feedback circuit needed to stabilise the main transconductors 100, 100' when connected as gyrators for use in filters.

The balanced transconductor circuit 200 has been designed in CMOS18 according to the rules for transforming from a transconductor with a quiescent current J = 312nA and a differential G _m of 3μS when operated from V _dc ia of 1.162V. With V _b set to 10OmV, the average V _t of 413mV transformed to Vt ^* of 313mV i.e. k = 0.76. The transformed design operated from V _dc ia ^* = 0.841V with a quiescent current of J ^* = 413.6nA and Gm ^* = 5μS. The power consumption is similar to the conventional design but the reduction in Vdda if applied to the digital domain would reduce the digital power consumption by (0.841/1.162) ² = 0.52.

Figure 4 shows the simulated transconductance of the balanced transconductor circuit 200 of Figure 3 using Ri=10Mohms and Ci = IOpF, giving a 3dB cut-off frequency of 1.6KHz. The transconductor circuit 200 has a high frequency differential transconductance value of G _m ^* eff = 4.46μS. The difference with G _m ^* =5μS is due to the expected attenuation of the capacitive divider at the input.

The low-voltage CMOS transconductor circuits described have been developed for use in an integrated channel filter within an ultra low power radio transceiver design. However, it should be recognised that the invention has more general applicability and could be applied to almost any situation where available supply voltages are inherently low, or where low voltage operation may offer an advantage to other associated circuitry (e.g. reduced power operation).

Figure 5 shows an alternative bias control circuit 210, which is identical to bias control circuit 110 except that the charge pump 154 is replaced by an operational transconductance amplifier (OTA) 254.

A first input of the OTA 254 being a negative input is connected to the output node 122, while a second input being a positive input receives the quiescent input voltage V _cm - The output of the OTA 254 is connected to the gate electrode of the source follower 152.