BACKGROUND

[0001] A memory controller is a digital circuit which manages the flow of data payloads to and from memory devices of a computing system. The flow may be executed by a memory command cycle. The memory command cycle may include a number of commands such as a data payload command, an activate command, and a read command or a write command. The read command may read data payloads from the memory devices. The write command may write the data payloads to the memory devices. The memory devices may be dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), non-volatile memory such as flash memory, other memory devices, or combinations thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings illustrate various examples of the principles described herein and are a part of the specification. The examples do not limit the scope of the claims.

[0003] Fig. 1 is a diagram of a system for transferring a variable data payload, according to one example of principles described herein.

[0004] Fig. 2 is a diagram of a system for transferring a variable data payload, according to one example of principles described herein.

[0005] Fig. 3 is a flowchart of a method for transferring a variable data payload, according to one example of principles described herein.

[0006] Fig. 4 is a flowchart of a method for transferring a variable data payload, according to one example of principles described herein. [0007] Fig. 5 is a diagram of a transferring system, according to one example of principles described herein.

[0008] Fig. 6 is a diagram of a transferring system, according to one example of principles described herein.

[0009] Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

DETAILED DESCRIPTION

[0010] As mentioned above, a memory controller is a digital circuit which manages the flow of data payloads to and from memory devices.

Further, the data payloads may be associated with a size. The size may be in terms of bytes. If the size of a data payload is sixty-four bytes, the memory controller may read or write the sixty-four bytes to or from the memory devices.

[0011] Often, the sizes of the data payloads transferred to and from the memory devices may vary. Further, memory controllers limit the number of bytes transferred for each data payload based on a read command or a write command to a fixed number of bytes, such as sixty-four bytes. Transferring larger amounts of data payloads increases the demand on the memory controller and the memory devices. Further, the memory controller may be optimized for transferring a burst length of the data payload or a block of the data payload. If the memory controller transfers a burst length of the data payload to a memory device optimized for blocks of the data payload, the memory controller may experience delays. As a result, the data payload is not transferred to and from the memory devices at an optimal rate.

[0012] The principles described herein include a method for transferring a variable data payload. Such a method includes receiving a data payload command to transfer a variable data payload from a memory controller to a memory device, determining, based on a size of the variable data payload, a number of cache lines for the variable data payload, assigning the variable data payload to the number of cache lines, and transferring each of the cache lines with a cyclic redundancy check (CRC) character from the memory controller to the memory device. Such a method allows the transfer of variable data payloads between the memory controller and memory devices and enables multiple memory technologies to be attached to the same memory controller as long as they are using the same protocol. As a result, the method improves the performance of the memory controller by reducing the demand on a command/address bus (C/A) of the memory controller.

[0013] In the present specification and in the appended claims, the term "data payload command" means a mechanism to control the transfer of a variable data payload between a memory controller and a memory device. The data payload command may include a start address for transferring each of the cache lines of the variable data payload to the memory device, a length of the variable data payload, a termination character associated with the variable data payload, or combinations thereof.

[0014] In the present specification and in the appended claims, the term "variable data payload" means information transferred between a memory controller and a memory device. The variable data payload may be associated with a size, the size varying depending on the amount of information associated with each variable data payload. The size of the variable data payload may be sent to the memory devices.

[0015] In the present specification and in the appended claims, the term "memory controller" means is a digital circuit which manages the flow of variable data payloads to and from at least one memory device. The flow may be executed by a memory command cycle. The memory command cycle may include a number of commands such as a data payload command, an activate command, and a read command or a write command.

[0016] In the present specification and in the appended claims, the term "memory device" means a mechanism to store a variable data payload as cache lines in memory. The memory devices may include dynamic random- access memory (DRAM), synchronous dynamic random-access memory (SDRAM), non-volatile memory such as flash memory, other memory devices or combinations thereof. [0017] In the present specification and in the appended claims, the term "cache line" means a portion of the variable data payload that is transferred to a memory device. The cache line is fixed in size and ranges from 16 to 256 bytes.

[0018] In the present specification and in the appended claims, the term "CRC Character" means a mechanism used to detect accidental changes made to a cache line while transferring the cache line from a memory controller to a memory device. A CRC character may be a short, fixed-length binary sequence that is concatenated to a cache line before the cache line is transferred to the memory device.

[0019] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough

understanding of the present systems and methods. It will be apparent, however, to one skilled in the art that the present apparatus, systems, and methods may be practiced without these specific details. Reference in the specification to "an example" or similar language means that a particular feature, structure, or characteristic described in connection with that example is included as described, but may not be included in other examples.

[0020] Referring now to the figures, Fig. 1 is a diagram of a system for transferring a variable data payload, according to one example of principles described herein. As will be described below, a transferring system is in communication with a memory controller and memory devices to receive a data payload command to transfer a variable data payload from a memory controller to a memory device. The transferring system determines, based on a size of the variable data payload, a number of cache lines for the variable data payload. Further, the transferring system assigns the variable data payload to the number of cache lines. The transferring system transfers each of the cache lines with a CRC character from the memory controller to the memory device.

[0021] As illustrated, the system (100) includes a memory controller (102). The memory controller (102) may be a digital circuit which manages the flow of variable data payloads to and from memory devices (106). The flow may be executed by a memory command cycle. Further, the variable payload data may be transferred via a bus (108). More information about the memory controller (102) will be described in other parts of this specification.

[0022] The system (100) further includes the memory devices (106). The memory devices (106) may include a number of types of memory technologies as long as the memory devices (106) use the same protocol. Further, the memory devices (106) may be attached to the memory controller (102) via the bus (108). The bus (108) may include a C/A bus and a data bus. More information about the memory devices (106) will be described in other parts of this specification.

[0023] As illustrated, the system (100) further includes a transferring system (104). The transferring system (104) is in communication with the memory controller (102) and the memory devices (106).

[0024] The transferring system (104) receives a data payload command to transfer a variable data payload from a memory controller (102) to at least one of the memory devices (106). The data payload command may be sent on predefined address lanes of the bus (108) and encoded in hex.

[0025] Further, the transferring system (104) determines, based on a size of the variable data payload, a number of cache lines for the variable data payload. The size of the variable data payload may be sent to the memory devices (106) or a memory buffer depending on the architecture of the memory devices (106).

[0026] The transferring system (104) further assigns the variable data payload to the number of cache lines. If the transferring system (104) determines five cache lines are needed for transferring the variable data payload, portions of the variable data payload are assigned to the five cache lines. As a result, the five cache lines contain the entire variable data payload.

[0027] Further, the transferring system (104) transfers each of the cache lines with a CRC character from the memory controller (102) to the memory devices (106). A transferring engine (114) may be used to transfer each of the cache lines with a CRC character from the memory controller (102) to the memory device (106). Such a system (100) allows the transfer of variable payloads between the memory controller (102) and the memory devices (106) as long as the memory devices (106) use the same protocol. As a result, the system (100) improves the performance of the memory controller (102) by reducing the demand on the bus (108) of the memory controller (102). More information about the transferring system (104) will be described later on in this specification.

[0028] While this example has been described with reference to the transferring system being located between the memory controller and the memory devices, the transferring system may be located in any appropriate location according to the principles described herein. For example, the transferring system may be located on the memory controller, the memory devices, other locations, or combinations thereof.

[0029] Fig. 2 is a diagram of a system for transferring a variable data payload, according to one example of principles described herein. As mentioned above, a transferring system is in communication with a memory controller and memory devices to receive a data payload command to transfer a variable data payload from a memory controller to a memory device. The transferring system determines, based on a size of the variable data payload, a number of cache lines for the variable data payload. Further, the transferring system assigns the variable data payload to the number of cache lines. The transferring system transfers each of the cache lines with a CRC character from the memory controller to the memory device.

[0030] As illustrated, the system (200) includes a memory controller (202). As mentioned above, the memory controller (202) may be a digital circuit which manages the flow of a variable data payload to and from memory devices (206) of the system (200). The flow may be executed by a memory command cycle. The memory command cycle may include a number of commands such as a data payload command, an activate command, and a read command or a write command. The read command may read the variable data payload from the memory devices (206). The variable data payload may be read from the memory devices (206) by the memory controller (206) via a bus (208). Further, the write command may write the variable data payload to the memory devices (206). The variable data payload may be written to the memory devices (206) by the memory controller (202) via the bus (208). The bus (208) may include a C/A bus and a data bus. The C/A bus may transfer commands between the memory controller (202) and the memory devices (206). The data bus may transfer variable data payloads between the memory controller (202) and the memory devices (206). As a result, the variable payload data may be transferred based on the memory command cycle, via the bus (208).

[0031] As illustrated, the memory controller (202) may include variable data payloads (212). The variable data payloads (212) may be information that is to be transferred between the memory controller (202) and the memory devices (206). In Fig. 2, the variable data payloads (212) includes variable data payload A (212-1 ), variable data payload B (212-2), and variable data payload C (212-3). The variable data payload may be associated with a size. The size of the variable data payloads (212) may vary. For example, variable data payload A (212-1 ) may be one-kilobyte. Variable data payload B (212-2) may be sixty-four bytes. Variable data payload C (212-3) may be thirty- two bytes. Further, the size of the variable data payload may be sent to the memory devices (206).

[0032] As illustrated, the memory controller (202) may include a number of data payload commands (216). The data payload commands (216) may be a mechanism to control the transfer of the variable data payloads (212) between the memory controller (202) and the memory devices (206). As illustrated, the data payload commands (216) include data payload command A (216-1), data payload command B (216-2), and data payload command C (216- 3). Data payload command A (216-1 ) may include a write command to write variable data payload A (212-1 ) to memory device A (206-1 ). Data payload command B (216-2) may include a write command to write variable data payload B (212-2) to memory device B (206-2). Data payload command C (216-3) may include a write command to write variable data payload C (212-3) to memory device B (206-2).

[0033] Further, the data payload commands (216) may include a start address for transferring each of the cache lines to the memory devices (206). For example, data payload command A (216-1 ) may indicate to transfer variable data payioad A (212-1) starting at address of 0x002 F of memory device A (206-1). As a result, a first cache line associated with variable data payioad A (212-1) is transferred to the start address of 0x002F for memory device A (206-

1)-

[0034] Further, the data payioad commands (216) may further include a length of the variable data payloads (212). The length of the variable data payloads (212) may be representative of the size of the variable data payloads (212). The length of the variable data payloads (212) may be represented in hexadecimal, binary, other representations, or combinations thereof.

[0035] Further, the data payioad commands (216) may include a termination character associated with the variable data payloads (212). The termination character may be a special character that allows the transferring system (204) to determine the size of each of the variable data payloads (212). The transferring system (204) may determine the size of the variable data payloads (212) by starting at the first byte of the variable data payloads (212) and counting the number of bytes until reaching the termination characters.

[0036] The system (200) further includes the memory devices (206). The memory devices (206) may include a number of types of memory technologies as long as the memory devices (206) use the same protocol. The types of memory devices (206) may include DRAM, SDRAM, non-volatile memory such as flash memory, other memory devices, or combinations thereof. As a result, some of the memory devices (206) may be optimized for variable data payloads that are transferred in burst length while some of the memory devices (206) may be optimized for variable data payloads that are transferred in blocks.

[0037] As illustrated, the memory devices (206) include memory device A (206-1) and memory device B (206-2). As will be described below, memory device A (206-1 ) stores, in memory, cache lines (218) associated with variable data payioad A (212-1 ). Further, memory device B (206-2) stores, in memory, cache lines (220) associated with variable data payioad B (212-1).

[0038] The system (200) further includes a transferring system (204). The transferring system (204). In one example, the transferring system (204) includes a processor and computer program code. The computer program code is communicatively coupled to the processor. The computer program code includes a number of engines (214). The engines (214) refer to program instructions for performing a designated function. The computer program code causes the processor to execute the designated function of the engines (214). In other examples, the engines (214) refer to a combination of hardware and program instructions to perform a designated function. Each of the engines (214) may include a processor and memory. The program instructions are stored in the memory and cause the processor to execute the designated function of the engine. As illustrated, the transferring system (210) includes a receiving engine (214-1), a size determining engine (214-2), a cache line determining engine (214-3), an assigning engine (214-4), a CRC engine (214- 5), and a transferring engine (214-6).

[0039] The receiving engine (214-1) receives a data payload command to transfer a variable data payload from the memory controller (202) to the memory device (206). The receiving engine (214-1) may receive data payload command A (216-1 ) to transfer variable data payload A (212-1 ) from the memory controller (202) to memory device A (206-1 ). The receiving engine (214-1) may further receive data payload command B (216-1) to transfer variable data payload B (212-2) from the memory controller (202) to memory device B (206-2). Still further, the receiving engine (214-1) may receive data payload command C (216-c) to transfer variable data payload C (212-2) from the memory controller (202) to memory device B (206-2).

[0040] The receiving engine (214-1) may receive the data payload commands (216) based on a ready bit. The ready bit may indicate if the memory devices (206) are ready to receive the next data payload command. If the ready bit is not set, the next data payload command is not received by the memory devices (206). However, if the ready bit is set, the next data payload command is received by the memory devices (206). The ready bit may be set if the ready bit's value is one. Alternatively, ready bit may not be set if the ready bit's value is zero. [0041] The size determining engine (214-2) determines a size of the variable data payioad. The size of each of the variable data payloads (212) may be sent on predefined address lanes of the memory controller (202) and encoded in hex. For example, a hex value of OxOOOF associated with variable data payioad A (212-1) indicates that variable data payioad A (212-1 ) is one- kilobyte. A hex value of 0x0000 associated with variable data payioad B (212- 2) indicates that variable data payioad B (212-2) may be sixty-four bytes. A hex value of 0x0002 associated with variable data payioad C (212-3) indicates that variable data payioad C (212-3) may be one-hundred twenty-eight bytes.

Further, bits two to zero of the data payioad commands (216) may be used for critical chunk addressing and used determine the sizes of the variable data payloads (212) in cache line increments. The interpretations of these bits may be a negotiate value that is determined at an initialization time between the memory controller (202) and the memory devices (206).

[0042] The cache line determining engine (214-3) determines, based on the size of the variable data payioad, a number of cache lines for the variable data payioad. As mentioned above, the hex value of OxOOOF associated with variable data payioad A (212-1 ) indicates that variable data payioad A (212-1 ) is one- kilobyte. Further, each cache line may be sixty-four bytes. As a result, the cache line determining engine (214-3) determines sixteen cache lines are needed to transfer variable data payioad A (212-1) from the memory controller (202) to memory device A (206-1 ). Similarly, the cache line determining engine (214-3) determines one cache line is needed for variable data payioad B (212-2) and two cache lines are needed for variable data payioad C (212-3).

[0043] The cache line determining engine (214-3) may determine, based on the size of the variable data payioad, the number of cache lines for the variable data payioad by determining a burst length. The burst length may be dependent on the type of memory device. For some memory devices, the burst length may be eight bits. For other memory devices, the burst length may be in terms of blocks. As a result, for memory devices with a larger burst length, less cache lines are needed for the variable data payioad. [0044] Further, the cache line determining engine (214-3) may determine, based on the size of the variable data payload, the number of cache lines for the variable data payload by determining a bit width of the memory devices. The bit width may affect the memory device's addressing. In an example, the bit width of the memory device A (206-1 ) may be four bits. The bit width of the memory device B (206-2) may be two bits.

[0045] The cache line determining engine (214-3) may further determine, based on the size of the variable data payload, the number of cache lines for the variable data payload by determining a value to modify a prefetch amount. The value may be a maximum or a minimum amount of the variable data payload to prefetch. The prefetch amount may aid the memory controller (202), the memory devices (206), or the transferring system (204) in reducing wait states.

[0046] Further, the size of the number of cache lines is based on increments of bytes. A cache line may be sixty-four bytes. As a result, half of a cache line may be thirty-two bytes.

[0047] As mentioned above, the transferring system (204) includes an assigning engine (214-4). The assigning engine (214-4) assigns the variable data payload to the number of cache lines. For example, the assigning engine (214-4) assigns variable data payload A (212-1 ) to sixteen cache lines. As will be described below, the sixteen cache lines for variable data payload A (212-1 ) are transferred to memory device A (206-1) as cache line one (218-1 ) to cache line sixteen (218-16). Further, variable data payload B's one cache line is transferred to memory device B (206-2) as cache line A (220-1). Variable data payload C's two cache lines are transferred to memory device B (206-2) as cache line B (220-2) and cache line C (220-3).

[0048] The CRC engine (214-5) determines a CRC character for each of the cache lines (218, 220). A CRC character may be a mechanism used to detect accidental changes made to a cache line while transferring the cache line from the memory controller (202) and the memory devices (206). The CRC character may be a short, fixed-length binary sequence that is concatenated to a cache line. The CRC engine (214-5) may determine the CRC characters based on various methods and techniques.

[0049] The transferring engine (214-6) transfers, based on the data payload command, each of the cache lines with a CRC character from the memory controller (202) to the memory devices (206). Variable data payload A (212-1) is transferred, via the transferring engine (214-6), to memory device A (206-1 ) as cache line one (218-1 ) to cache line sixteen (218-16). Further, cache line one (218-1 ) to cache line sixteen (218-16) may include a CRC character for each of the cache lines (218).

[0050] Further, variable data payload B (212-2) is transferred, via the transferring engine (214-6), to memory device B (206-2) as cache line A (220- 1). Cache line A (220-1 ) may include a CRC character.

[0051] Variable data payload C (212-3) is transferred, via the transferring engine (214-6), to memory device B (206-2) as cache line B (220-2) and cache line C (220-3). Further, cache line B (220-2) and cache line C (220- 3) may include CRC characters.

[0052] The transferring engine (214-6) may transfer each of the cache lines with a CRC character from the memory controller (202) to the memory devices (206) based on an acknowledge command, an activate command, a read command, a write command, or combinations thereof. The acknowledge command may allow the memory devices (206) to acknowledge that it is ready to receive the next command. If the acknowledge command indicates the memory devices (206) are ready to receive the next command, the next command is sent. If the acknowledge command indicates the memory devices (206) are not ready to receive the next command, the next command is not sent.

[0053] The activate command may activate the memory devices (206). The activate command may include rank addressing, bank addressing, bank group addressing, or row addressing of the memory devices (206).

[0054] The read command may read the variable data payload from the memory devices (206). The variable data payload may be read from the memory devices (206) by the memory controller (206) via the bus (208). Further, the write command may write the variable data payload to the memory devices (206). The variable data payload may be written to the memory devices (206) by the memory controller (202) via the bus (208). As a result, the variable payload data may be transferred based on the memory command cycle, via a bus (208). The read command and the write command may include rank addressing, bank addressing, bank group addressing, or column addressing of the memory devices (206).

[0055] As overall example of Fig. 2 will now be described. The receiving engine (214-1) receives data payload command A (216-1) to transfer variable data payload A (212-1) from the memory controller (202) to memory device A (206-1 ). The size determining engine (214-2) determines the size of variable data payload A (212-1 ) as one kilobyte. The cache line determining engine (214-3) determines that variable data payload A (212-1 ) is to be represented as sixteen cache lines. The assigning engine (214-4) assigns variable data payload A (212-1) to sixteen cache lines. The CRC engine (214- 5) determines eight bit CRC characters for each of the sixteen cache lines for variable data payload A (212-1). The transferring engine (214-6) transfers, the sixteen cache lines with the CRC characters from the memory controller (202) to memory device A (206-1 ) as cache line one (218-1) to cache line sixteen (218-16).

[0056] Fig. 3 is a flowchart of a method for transferring a variable data payload, according to one example of principles described herein. The method (300) may be executed by the system (100) of Fig. 1. The method (300) may be executed by other systems such as system 200, system 500, or system 600. In this example, the method (300) includes receiving (301 ) a data payload command to transfer a variable data payload from a memory controller to a memory device, determining (302), based on the size of the variable data payload, a number of cache lines for the variable data payload, assigning (303) the variable data payload to the number of cache lines, and transferring (304) each of the cache lines with a CRC character from the memory controller to the memory device. [0057] As mentioned above, the method (300) includes receiving

(301 ) a data pay!oad command to transfer a variable data payioad from a memory controller to a memory device. The data payioad command may include a start address in the memory device, a length of the variable data payioad, a termination character, or combinations thereof. Further, the data payioad command is sent on predefined address lanes and encoded.

[0058] The variable data payioad may be chosen by the memory controller based on the type of memory device. For a DRAM memory device, the variable data payioad may be equal to burst lengths. For a non-volatile memory device the variable data payioad may be equal to a block size.

[0059] The variable data payioad may be chosen by the memory controller based on a workload. For a random workload, the variable data payioad may be sent to random address locations of the memory device. Further, the variable data payioad that is associated with a random workload may be transferred in cache line increments.

[0060] Further, the workload may transfer large sizes of variable data payloads in contiguous memory space of the memory device. As a result, the method (300) may transfer the cache lines such that the cache lines are transferred to consecutive addresses of the memory devices.

[0061] As mentioned above, the method (300) includes determining

(302) , based on the size of the variable data payioad, a number of cache lines for the variable data payioad. The method (300) determines, based on the size of the variable data payioad, the number of cache lines for the variable data payioad by determining a burst length, determining a bit width of the memory device, and determining a prefetch amount as described above.

[0062] As mentioned above, the method (300) includes assigning

(303) the variable data payioad to the number of cache lines. If the method (300) determines four cache lines are needed for the variable data payioad, the variable data payioad is divided into four equal sizes. Each of the four equal sizes of the variable data payioad is assigned to a cache line.

[0063] As mentioned above, the method (300) includes transferring

(304) each of the cache lines with a CRC character from the memory controller to the memory device. If the variable data payload is divided into four cache lines, each of the four cache lines is sent to the memory device with a CRC character. The variable data payload may be sent to multiple memory devices. The variable data payload portion of the data payload command may be issued for each read command or write command if the variable data payload changes between transferring the variable data payload from the memory controller to the memory device. Further, the variable data payload portion of the data payload command may be omitted if multiple transfers of the variable data payload are made to the same memory device.

[0064] Fig. 4 is a flowchart of a method for transferring a variable data payload, according to one example of principles described herein. The method (400) may be executed by the system (100) of Fig. 1. The method (400) may be executed by other systems such as system 200, system 500, or system 600. In this example, the method (400) includes receiving (401 ) a data payload command to transfer a variable data payload from a memory controller to a memory device, determining (402) a size of the variable data payload, determining (403), based on the size of the variable data payload, a number of cache lines for the variable data payload, assigning (404) the variable data payload to the number of cache lines, determining (405) the CRC character for each of the cache lines, transferring (406) each of the cache lines with a CRC character from the memory controller to the memory device.

[0065] As mentioned above, the method (400) includes determining (402) a size of the variable data payload. The size of the variable data payload may be sent on predefined address lanes of the memory controller and encoded in hex. For example, a hex value of 0x000 F indicates that the variable data payload is one-kilobyte.

[0066] As mentioned above, the method (400) includes determining (405) the CRC character for each of the cache lines. Depending on the size, complexity, and operation of the memory controller and the memory devices, the CRC character may vary in length. For a simple memory controller and memory devices, the CRC character may be three bits. For a complex memory controller and memory devices, the CRC character may be eight bits. The CRC character for each of the cache lines may be distinct from one another. The CRC character for each of the cache lines may be the same value.

[0067] Fig. 5 is a diagram of a transferring system, according to one example of principles described herein. The system (500) includes a cache line determining engine (514-1 ), an assigning engine (514-2), a CRC engine (514-3) and a transferring engine (514-4). The engines (514) refer to a combination of hardware and program instructions to perform a designated function.

Alternatively, the engines (514) may be implemented in the form of electronic circuitry (e.g., hardware). Each of the engines (514) may include a processor and memory. Alternatively, one processor may execute the designated function of each of the engines (514). The program instructions are stored in the memory and cause the processor to execute the designated function of the engine.

[0068] The cache line determining engine (514-1) determines, based on the size of the variable data payload, a number of cache lines for the variable data payload. The cache line determining engine (514-1) determines the number of cache lines based on the size of the cache line. If a variable data payload is one kilobyte and a cache line is sixty four bytes, the cache line determining engine (514-1 ) determines sixteen cache lines are needed for the variable data payload.

[0069] The assigning engine (514-2) assigns the variable data payload to the number of cache lines. If sixteen cache lines are needed for the variable data payload, the assigning engine (514-4) assigns portions of the variable data payload to sixteen cache lines.

[0070] The CRC engine (514-2) determines the CRC character for each of the cache lines. The CRC character may be two bits, four bits, eight bits, or other lengths of bits depending on the size of the variable data payload.

[0071] The transferring engine (514-4) transfers each of the cache lines with a CRC character from the memory controller to the memory device. The transferring engine (514-4) may transfer each of the cache lines with a CRC character from the memory controller to the memory device in a sequential order. [0072] Fig. 6 is a diagram of a transferring system, according to one example of principles described herein. In this example, the transferring system (600) includes resource(s) (602) that are in communication with a machine- readable storage medium (604). Resource(s) (602) may include one processor. In another example, the resource(s) (602) may further include at least one processor and other resources used to process instructions. The machine- readable storage medium (604) represents generally any memory capable of storing data such as instructions or data structures used by the transferring system (600). The instructions shown stored in the machine-readable storage medium (604) include size determining instructions (606), cache line

determining instructions (608), assigning instructions (610), and transferring instructions (612).

[0073] The machine-readable storage medium (604) contains computer readable program code to cause tasks to be executed by the resource(s) (602). The machine-readable storage medium (604) may be tangible and/or physical storage medium. The machine-readable storage medium (604) may be any appropriate storage medium that is not a

transmission storage medium. A non-exhaustive list of machine-readable storage medium types includes non-volatile memory, volatile memory, random access memory, write only memory, flash memory, electrically erasable program read only memory, or types of memory, or combinations thereof.

[0074] The size determining instructions (606) represents instructions that, when executed, cause the resource(s) (602) to determine a size of the variable data payload. The cache line determining instructions (608) represents instructions that, when executed, cause the resource(s) (602) to determine, based on the size of the variable data payload, a number of cache lines for the variable data payload.

[0075] The assigning instructions (610) represents instructions that, when executed, cause the resource(s) (602) to assign the variable data payload to the number of cache lines. The transferring instructions (612) represents instructions that, when executed, cause the resource(s) (602) to transfer each of the cache lines with a CRC character from the memory controller to the memory device.

[0076] Further, the machine-readable storage medium (604) may be part of an installation package. In response to installing the installation package, the instructions of the machine-readable storage medium (604) may be downloaded from the installation package's source, such as a portable medium, a server, a remote network location, another location, or combinations thereof. Portable memory media that are compatible with the principles described herein include DVDs, CDs, flash memory, portable disks, magnetic disks, optical disks, other forms of portable memory, or combinations thereof. In other examples, the program instructions are already installed. Here, the memory resources can include integrated memory such as a hard drive, a solid state hard drive, or the like.

[0077] In some examples, the resource(s) (602) and the machine- readable storage medium (604) are located within the same physical component, such as a server, or a network component. The machine-readable storage medium (604) may be part of the physical component's main memory, caches, registers, non-volatile memory, or elsewhere in the physical component's memory hierarchy. Alternatively, the machine-readable storage medium (604) may be in communication with the resource(s) (602) over a network. Further, the data structures, such as the libraries, may be accessed from a remote location over a network connection while the programmed instructions are located locally. Thus, the transferring system (600) may be implemented on a user device, on a server, on a collection of servers, or combinations thereof.

[0078] The transferring system (600) of Fig. 6 may be part of a general purpose computer. However, in alternative examples, the transferring system (600) is part of an application specific integrated circuit.

[0079] The preceding description has been presented to illustrate and describe examples of the principles described. This description is not intended to be exhaustive or to limit these principles to any precise form disclosed. Many modifications and variations are possible in light of the above teaching.