BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for reducing noise in electronic devices, and more particularly, to a method and apparatus for reducing transient noise generated when electronic devices are switched to drive high ouput currents.

2. Description of the Prior Art

In many electronic devices and systems, the presence or generation of transient noise is an undesireable consequence of normal operation. Although low levels of transient noise may be tolerated under certain operating conditions, transient noise of high levels may result in inaccurate outputs for the electronic devices, or may cause the electronic devices to exceed their operating conditions for a period of time. This may lead to the ultimate failure of the electronic devices and the systems in which they are utilized.

Figure 1 illustrates an output driver 10 used in a conventional integrated circuit. The output driver 10 is activated by an input voltage V I _T .N_ received from the logic of the integrated circuit (not shown) and provides an output voltage _Q used to drive external electronic device. The output driver 10 illustrated includes a parasitic inductance 12 representative of the inductance of the integrated circuit, a first switch 14 and a second switch 16.

Prior to activation of the output driver 10, the first switch 14 is closed and the second switch 16 is

open. A power supply voltage V is applied to the load capacitance 18 through the first switch 14, allowing the load capacitance 18 to become fully charged, maintaining the output voltage V _ouτ equal to the power supply voltage V _DD . The parasitic inductance 12 of the integrated circuit is electrically isolated from the power supply voltage V _DD and the load capacitance 18 by the open second switch 16. As illustrated in Figure 2, the current level I _Q passing through the parasitic inductance 12 is therefore initially at a low level. Similarly, the voltage level across the parasitic inductance 12 is also minimal prior to the closing of the switch 16.

At a time which may be referred to as time zero

⁽ tg) , the input voltage V _IN changes state to activate the output driver 10. In response, the first switch 14 begins to open and the second switch 16 begins to close.

The fully charged load capacitance 18 therefore begins to discharge very quickly, supplying a current I, to the parasitic inductance 12. The level of current I passing through the parasitic inductance 12 therefore increases as a step function at time t _{r) r} as illustrated in Figure 2. Similarly, the output voltage V commences to decrease as the load capacitance 18 discharges over time, as illustrated' in Figure 3.

Figure 4 illustrates the rate of change of the current I passing through the parasitic inductance 12.

Due to the step increase in the current I G which occurs at time t _{Q r} a spike 19 is created in the rate of change of the current I Since noise is proportional to the rate of change of the current I passing through the parasitic inductance 12, the spike 19 results in the undesireable generation of a high level of noise.

In recent years, methods and devices have been sought to drive higher and higher values of load capacitance 18. When larger values of load capacitance

18 are made to discharge within the same time period as conventional values of capacitance, higher rates of change of current are experienced through the parasitic inductance 12 electronic device. As a result, even higher levels of transient noise are generated than exist in conventional output drivers.

In addition, faster circuit switching has recently been sought. However, when conventional values of load capacitance are driven within a shorter period of time, higher levels of transient noise are also produced.

Conventional electronic devices have therefore been limited to high speed, high noise applications or low speed, low noise applications.

Some conventional electronic devices have also required the consumption of DC, increasing the total power drain caused by the operation of the electronic devices.

SUMMARY OF THE INVENTION

The present invention provides an apparatus and technique for allowing high speed, low noise switching of electronic devices used to drive high transient current electronic devices. The present invention also allows current switching to occur without the application of DC power. The present invention accompishes these functions by providing means for maintaining a relatively constant level of current passing through the parasitic inductance of the electronic devices during the switching operations.

More specifically, a switch is provided between the power source and the parasitic inductance of the electronic device. At a predetermined point in time prior to activation of the electronic device, the switch begins to close, providing a current which passes through the parasitic inductance of the electrical device, presoaking it with current. When the electronic device is activated, the switch begins to open, decreasing the level of current passing through the parasitic inductance. Simultaneously, current begins to pass through the parasitic inductance of electronic device from the discharging load capacitance such that the total current passing through the parasitic inductance remains constant due to the offsetting slopes of the currents passing therethrough. Since the rate of change of the current passing through the parasitic inductance is minimized, so too is the level of transient noise generated. In the preferred embodiment of the present invention, the magnitudes of the current passing through the parasitic inductance during the current presoaking period and during switching of the electronic device are equal, resulting in at most a negligible level of transient noise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 illustrates a schematic diagram of a conventional output driver of an integrated circuit.

FIGURE 2 illustrates the current level over time passing through the parasitic inductance of a conventional integrated circuit having the output driver illustrated in FIGURE 1.

FIGURE 3 illustrates the output voltage level over time of the output driver illustrated in FIGURE 1.

FIGURE 4 illustrates the derivative over time of the current level passing through the parasitic inductance of a conventional integrated circuit having the output driver of FIGURE 1.

FIGURE 5 illustrates a schematic diagram of the output driver of the present invention.

FIGURE 6 illustrates the output voltage over time of the output driver illustrated in FIGURE 5.

FIGURE 7 illustrates the presoaking current level over time.

FIGURE 8 illustrates the voltage across the parasitic inductance of the electronic device of the present invention.

FIGURE 9 illustrates the current level over time discharged from the load capacitance of FIGURE 5.

FIGURE 10 illustrates the current level over time passing through the parasitic inductance of the electronic device in a first application of the present invention.

FIGURE 11 illustrates the current level over time passing through the parasitic inductance of the electronic device in a second application of the present invention.

FIGURE 12 illustrates a more detailed schematic diagram of the output driver illustrated in FIGURE 5.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The following description is of the best presently contemplated mode of carrying out the present invention. This description is made for the purposes of illustrating the general principles of the invention and is not to be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

The present invention provides a device and a method for reducing transient noise generated during activation of an electronic device. The present invention is unconventional in that the inductance of the electronic device is presoaked with current prior to the time at which the electronic device is activated, thereby minimizing the rate of change of the current passing through the parasitic inductance when the load capacitance is allowed to discharge.

The present apparatus and method are applicable to all electronic devices which drive high output current. For simplicity, however, the present invention will be described below with respect to output drivers used in integrated circuits.

Operation of the output driver 30 is described below with respect to three time frames. The first time frame elapses at ^• a preselected time t prior to the

P commencement the activation of the output driver 30.

The second time frame is a current presoaking period which commences at time t and ends at time zero (t _n ) when activation of the output driver 30 is commenced.

The final time frame begins when activation of the output driver 30 is commenced at time t and includes all time thereafter.

Referring to Figure 5, the electronic device of the present invention includes an output driver 30 having a power supply (not illustrated) which generates

a power supply voltage V _D . A first switch 34 is provided between the power supply and an load capacitance 38 representative of the capacitance of the electrical device (s) being driven. A second switch 36 is provided between the load capacitance 38 and the parasitic inductance 32 representative of any internal or external parasitic inductance connected to the output driver 30. In addition, a third switch 37, which in a preferred embodiment is matched with the second switch 36, is provided between the power supply and the parasitic inductance 32.

During the first time frame prior to time t , the first switch 34 is closed, allowing the power supply voltage V _DD to be applied to the load capacitance 38. The load capacitance 38 may therefore become fully charged, allowing the output voltage V to attain its maximum limit, as illustrated in Figure 6. The second switch 36 is open, electrically isolating the parasitic inductance 32 from the load capacitance 32. Similarly, the third switch 37 is open, electrically isolating the parasitic inductance 32 from the power supply voltage

The current presoaking period commences at time t when the activation input voltage V _IN received from the logic of the circuit (not shown) changes state. The input voltage V _IN is applied to two paths, with the first path 40 leading to a delay mechanism 44. The delay mechanism may be formed, for example, of a plurality of in series inverters. The second path 42 leads to the switch 37-. Application of the changed state input voltage V to the second path 42 results in switch 37 commencing to close, allowing the power supply voltage V _DD to be applied to the parasitic inductance 32. A current I ₂ therefore begins to flow through the switch 37 , presoaking the parasitic inductance 32, as illustrated in Figure 7. A resistance element 45 is

provided along the second path 42 in order to assure smooth closing of the switch 37, thereby providing a linear transition in the level of current I passing through the parasitic inductance 32, minimizing its rate of change and the noise which is thereby generated. The voltage level V _G across the parasitic inductance 32, which is proportional to the rate of change of the current 1^ passing through the parasitic inductance 32, remains constant during this period of time due to the linear increase in the current I _Q as illustrated in Figure 8.

The third time period commences when the output driver 30 is activated at time ^' t _Q . This occurs when the changed state input voltage V _IN i _s no longer delayed by the delay mechanism 44 located along the first path 40. When this event occurs, which may be varied by selection of an appropriate delay time for the delay mechanism 44, an appropriate voltage signal is applied to the third path 43 to begin opening the switch 37, thereby commencing to electrically isolate the inductance 32 of the integrated circuit from the power supply voltage _DD . The flow of the current I2 passing through the parasitic inductance 32 begins to quickly decrease, as illustrated by numeral 33 in Figure 7. The delayed input voltage signal is also applied to the first switch 34 which commences to open and allow the load capacitance 38 to become electrically isolated from the power supply voltage V ^' The second switch 36 also commences to close to create an electrical connection between the load capacitance 38 and the parasitic inductance 32 of the integrated circuit. The load capacitance 38 thus commences to discharge through the second switch 36, generating an initially increasing value of current I ₃ which passes through the parasitic inductance 32 of the integrated circuit, as illustrated by numeral 35 in Figure 9.

The total value of the current I passing through the parasitic capacitance 32 at any time is thus equal to the total of the current ∑ ₂ from the power supply and the current I., from the load capacitance. As illustrated in Figure 10, if the switches 36 and 37 are chosen as a matched pair with the same switching speed, and the second switch 36 commences to close simultaneously with the commencement of the opening of the switch 37 at time t~ , the current I _G should remain approximately constant during the switching operation. The rate of change of the current passing through the parasitic inductance 32, as well as the transient noise generated, will therefore be negligible or zero. This constitutes the preferred embodiment of the present invention.

Alternately, it is possible that switches 36 and 37 are not a matched pair and have different switching speeds, or that the second switch 36 does not commence to close simultaneously with the commencement of opening of switch 37. In such cases, it is possible that the total level of current I passing through the parasitic capacitance 32 may not be exactly constant, and some level of switching noise may be generated. This level of switching noise, however, may still be less than that experienced by conventional switching mechanisms under the same operating conditions. Figure 11 illustrates the case in which the second switch 36 commences to close a short time Δ t after matched switch 37 commences to open.

It is also preferred that the maximum values of the current I_ and I are equal, as illustrated in Figure 10. If they are not of the same magnitude, however, this does not preclude the establishment of transient noise levels which are still lower than those achievable with conventional electronic devices.

Figure 5 also illustrates an optional current source 48 located on ^" the ungrounded end of the inductance 48 of the integrated circuit. The current source 48 improves the operation of the output driver 30 of the present invention by more accurately maintaining a preselected maximum level of current passing through the parasitic inductance 32 during switching. During the first time period, the current source 48 is inactive and passes no current through the parasitic inductance 32. During the current presoaking time period, however, the switch 37 begins to close and the power supply voltage V _D is applied to the current source 48, activating it. A fixed current is therefore generated by the current source 48 which is delivered to the parasitic inductance 32. During the third time period during switching, the power supply voltage V commences becoming electrically isolated from the fixed current source 48 by the open switch 37. The fixed current source 48 therefore decreases its output current, and the current flowing through the parasitic inductance 32 due the switch 37 begins to rapidly decrease. Si ultaneoustly, however, the delayed changed state input voltage signal V _IN begins to close the switch 36, allowing the output voltage V _QUT to be applied to the current source 48, biasing the current source 48 to output more current at the same time that the current source 48 is outputting less current due to the opening of switch 37. The total current I _G passing through the parasitic inductance from the current source 48 thus remains approximately constant. The current source 48 thus assures that a relatively constant maximum level of current will pass through the integrated circuit during the activation of the output driver 30, thereby reducing the noise generated during activation of the output driver.

The circuit illustrated in Figure 5 thus decreases the level of transient noise generated during activation of the output driver 30 by presoaking the parasitic inductance 32 with a current prior to activation of the output driver 30. When the output driver is activated, the presoaking current is reduced as the current discharged from the load capacitance 38 increases. The switching operation is also accomplished without the necessity of providing DC power.

Figure 12 illustrates the integrated circuit of Figure 5 in more detail, wherein the switches 34, 36 and 37 illustrated in Figure 5 have been replaced with MOSFET transistors M , M _N , r _j p and M _DN and the output driver is formed as an active high output driver. More specifically, during the first time frame prior to activation of the output driver 30, the input voltage V is low. Accordingly, N-channel transistor M _N is nonconductive, electrically isolating the parasitic inductance 32 from the power supply voltage The low input voltage signal is inverted by an inverter 50, maintaining the N-channel transistor M conductive, electically connecting the load capacitance 38 with the power supply voltage V _DD . The input voltage signal is further inverted by the inverter 52, maintaining P-channel transistor M _p conductive and the N-channel transistor M _DN nonconductive. The parasitic inductance 32 of the device is therefore electrically isolated from the power supply voltage V _DD as the power supply voltage V _DD is applied to the load capacitance 38. The entire circuit thus draws zero direct current.

During the current presoaking time period, the high input voltage signal V _χN is generated by the logic of the circuit and is applied to both the time delay path 40 and the second path 42. The N-channel transistor M _N commences to become conductive, electrically connecting the parasitic inductance 32 with

the power supply voltage V _n . The current source 48 commences to be activated, supplying a fixed current to the parasitic inductance 32, presoaking it. Transistors Mp, Mrp and Mr _jN remain unaffected by the activating input voltage V _N during the current presoaking time period.

After the presoaking period has elapsed, the high input voltage V _IN is no longer delayed by the delay mechanism 44. The twice inverted high input voltage V commences to make transistor M nonconductive, eliminating the electrical connection between the power supply voltage V _DD and the current source 48. The current source 48 therefore commences to deactivate. In addition, the inverted high input voltage V is applied to transistor g commencing to make it non-conductive. Moreover, the twice inverted input voltage V i _s also applied to transistor making it commences to be conductive. An electrical connection is thereby created between the current source 48 and the load capacitance 38. As the load capacitance 38 begins to discharge, the output voltage _QUT increasingly biases the current source 48 to be activated. Ideally, the initially increasing output voltage V _QUT biases the current source 48 to make up for its deactivation due to the increasingly nonconductive transistor such that the current source 48 outputs a constant level of current during the switching operation. Since the same total fixed level of current is applied to the parasitic inductance 32 throughout the switching operation, the rate of change of the current passing through the parasitic inductance 32 is zero or some minimum value. The transient noise generated by activation of the output driver 30 is therefore minimized.

The invention has been described and illustrated with respect to ground noise generated when the electronic device being driven is allowed to discharge

through the ground inductance during a switching operation. As can easily be envisioned, the invention is also applicable to the reduction or elimination of power supply switching noise created when the electrical device being driven is initially charged through the power supply inductance by a switching operation. Ideally, presoaking of both the power supply inductance and the ground inductance may occur to reduce or eliminate all switching noise in the electronic device.