The present invention relates to transmission gates, particularly transmission gates for use in analogue-to-digital converters.

Modern electronic circuits, including analogue-to-digital converters (ADCs), employ a particular circuit element known as a transmission gate. A transmission gate is effectively a switch that can either provide a bidirectional signal path or can (ideally) block signals from passing through it. The transmission gate can be switched between these two modes through use of a control signal. Such transmission gates therefore pass a signal from an input terminal to an output terminal or block it, depending on the value of the control signal, e.g. if the control signal is logic high, the transmission gate will pass the signal or, if the control signal is logic low, the transmission gate will block the signal, or vice versa.

Typical transmission gates are constructed using complementary metal-oxide- semiconductor (CMOS) technology, wherein a complementary, matched pair of transistors - a p-channel metal-oxide-semiconductor field-effect-transistor

(pMOSFET) and an n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) - are connected in parallel with one another. The input terminal is typically connected to one terminal of each transistor (e.g. the source terminals of each) and the output terminal is connected to the other terminal of each transistor (e.g. the drain terminal of each). The control signal is applied to the gate terminal of one of the transistors and a logical negation of the control signal is applied to the gate terminal of the other transistor. This ensures that both transistors are on, or both transistors are off, at the same time. Such a conventional transmission gate structure can be found on page 123 of the textbook "CMOS Analog Circuit Design, Second Edition" by Douglas R. Holberg and Phillip E. Allen.

CMOS-based transmission gates are particularly suited for digital circuits due to their ability to pass both "strong" digital 'O's and strong digital '1 's from the input to the output when compared to a single nMOSFET (which can typically only pass a strong '0' but a poor Ί') or a single pMOSFET (which can typically only pass a strong Ί' but a poor 'Ο') used as a switch. One exemplary application of the use of a transmission gate of the kind described is an ADC for use in battery voltage measurement - i.e. for checking the voltage produced by a battery. Such a battery measurement ADC may, for example, require a 5 V transmission gate. When analysing the performance of a transmission gate, two important measures are the "on-resistance" R _on and the "off-resistance" R ₀ ff of the transmission gate. The on-resistance R _on is the resistance of the transmission gate while it is switched on (i.e. when signals may pass through it). Similarly, the off-resistance R ₀ ff is the resistance of the transmission gate while it is switched off (i.e. when signals are supposed to be blocked). However, the Applicant has appreciated that the on and off-resistances R _on , R ₀ ff typically vary depending on the input voltage presented at the input terminal.

The Applicant has appreciated that it would be advantageous for a transmission gate to exhibit a greater degree of linearity with respect to the on and off- resistances Ron, Roff across a range of different input voltages.

When viewed from a first aspect, the present invention provides a transmission gate circuit portion arranged selectively to pass an input signal from an input node to an output node, said transmission gate comprising:

a control circuit portion arranged to provide first and second control voltages;

a first field-effect-transistor having a drain terminal connected to the input node, a source terminal connected to the output node, and a gate terminal connected to the first control voltage, said first field-effect-transistor having a first drain-source breakdown voltage, a first gate-source breakdown voltage, a first gate- drain breakdown voltage, and a first gate-body breakdown voltage; and

a second field-effect-transistor having a drain terminal connected to the output node, a source terminal connected to the input node, and a gate terminal connected to the second control voltage, said second field-effect-transistor having a second drain-source breakdown voltage, a second gate-source breakdown voltage, a second gate-drain breakdown voltage, and a second gate-body breakdown voltage;

wherein the first drain-source breakdown voltage is substantially equal to the second drain-source breakdown voltage; and wherein at least one of the first and second field-effect transistors has its respective drain-source breakdown voltage greater than its respective gate-source, gate-drain, and gate-body breakdown voltages of the respective field-effect- transistor.

Thus it will be appreciated by those skilled in the art that the present invention provides a transmission gate that exhibits less variation in the on-resistance and off-resistance presented by the transmission gate across a range of input voltages compared to conventional transmission gate arrangements, thus leading to improvements in the linearity of the transmission gate. The improved linearity arises due to at least one of FETs being arranged such that its drain-source breakdown voltage is higher than its respective gate-source, gate-drain, and gate- body breakdown voltages. Those skilled in the art will appreciate that, in general, the drain-source breakdown voltage of a FET is the maximum rated voltage that can be applied between the drain and source terminals of the FET without it breaking down electrically.

Typically the drain-source breakdown voltage is different across different device categories. Similarly, the gate-source, gate-drain, and gate-body breakdown voltages are typically different across different device categories.

For example, typically, a '5 V PMOS-based FET might typically exhibit drain- source, gate-source, gate-drain, and gate-body breakdown voltages of

approximately between 5 V and 6 V, for example 5.5 V. Conversely, a '3 V NMOS- based FET might typically exhibit drain-source, gate-source, gate-drain, and gate- body breakdown voltages of approximately between 3 V and 4 V, for example 3.6 V.

The Applicant has appreciated that a FET (or FETs) having a greater drain-source breakdown voltage than the other breakdown voltages is effectively a device of a 'lower device category' but that exhibits an atypically high drain-source breakdown voltage. Thus, in accordance with embodiments of the present invention, a special FET is used where the gate-source, gate-drain, and gate-body breakdown voltages are typical of a different device category to that associated with the drain-source breakdown voltage. The off-resistance exhibited by the transmission gate is effectively the parallel combination of the off-resistance of the first FET and the off-resistance of the second FET. Due to at least one of these FETs being from a 'lower' device category but with a higher drain-source breakdown voltage, this FET (or FETs) exhibit a smaller off-resistance than a conventional FET having that drain-source breakdown voltage. As such, the off-resistance of the transmission gate is dominated by the off-resistance of the FET (or FETs) with the increased drain- source breakdown voltage.

Similarly, the on-resistance exhibited by the transmission gate is effectively the parallel combination of the on-resistance of the first FET and the on-resistance of the second FET. As, the FET with the increased drain-source breakdown voltage has a smaller on-resistance than a conventional FET, the on-resistance of the transmission gate is also dominated by the on-resistance of the FET (or FETs) with the increased drain-source breakdown voltage.

A transmission gate in accordance with some embodiments of the present invention may be constructed from two different, unmatched field-effect-transistors (FETs), i.e. the two FETs may have different gate-source, gate-drain, and gate-body breakdown voltages to one another but have the same drain-source breakdown voltage. This unconventional arrangement provides a transmission gate that uses FETs that effectively belong in different device categories. In particularly preferred set of such embodiments, the first drain-source breakdown voltage is greater than the first gate-source, gate-drain, and gate-body breakdown voltages.

However, both the first and second FETs may exhibit this property. Thus, in some alternative embodiments, the first drain-source breakdown voltages is greater than the first gate-source, gate-drain, and gate-body breakdown voltages; and the second drain-source breakdown voltages is greater than the second gate-source, gate-drain, and gate-body breakdown voltages.

The two FETs are each arranged such that the drain terminal of each is connected to the source terminal of the other. In some embodiments, at least one of the first and second field-effect-transistors is an n-channel metal-oxide-semiconductor field- effect-transistor and the other of said first and second field-effect-transistors is a p- channel metal-oxide-semiconductor field-effect-transistor. It will be appreciated that these could be either way around depending on which of the input and output nodes is generally at the greater voltage. However, typically the input node is at a greater voltage than the output node and thus, in at least some preferred embodiments, the first field-effect-transistor comprises an n-channel metal-oxide- semiconductor field-effect-transistor and the second field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor. While the field-effect-transistors could be depletion-type FETs, it is preferred that these are enhancement type. Thus in a set of embodiments, the first field-effect- transistor is enhancement type. In a potentially overlapping set of embodiments, the second field-effect-transistor is enhancement type. Thus in a preferred set of embodiments, the first field-effect-transistor comprises an enhancement type n-channel metal-oxide-semiconductor field-effect-transistor and the second field- effect-transistor comprises an enhancement type p-channel metal-oxide- semiconductor field-effect-transistor. In some embodiments, the first drain-source breakdown voltage is greater than 5 V, e.g. between 5 V and 6 V, e.g. 5.5 V. In some embodiments, the first gate-source breakdown voltage is between 2 V and 5 V, e.g. between 3 V and 4 V, e.g. 3.6 V.

In some embodiments, the first gate-drain breakdown voltage is between 2 V and 5 V, e.g. between 3 V and 4 V, e.g. 3.6 V.

In some embodiments, the first gate-body breakdown voltage is between 2 V and 5 V, e.g. between 3 V and 4 V, e.g. 3.6 V.

In some embodiments, the second drain-source breakdown voltage is greater than 5 V, e.g. between 5 V and 6 V, e.g. 5.5 V.

In some embodiments, the second gate-source breakdown voltage is greater than 5 V, preferably between 5 V and 6 V, and is preferably 5.5 V. ln some embodiments, the second gate-drain breakdown voltage is greater than 5 V, preferably between 5 V and 6 V, and is preferably 5.5 V.

In some embodiments, the second gate-body breakdown voltage is greater than 5 V, preferably between 5 V and 6 V, and is preferably 5.5 V.

In some embodiments, the transmission gate circuit portion is arranged such that: in a first mode of operation, the first control voltage is set to a non-zero value different to the input voltage and the second control voltage is set to zero; and in a second mode of operation, the first control voltage is set to zero and the second control voltage is set to the input voltage. Those skilled in the art will appreciate that by setting the first control voltage to a non-zero value different to the input voltage and choosing this voltage appropriately, the off-resistance presented by the transmission gate can be made more consistent across a range of different input voltages than would be typical of a conventional transmission gate.

This is novel and inventive in its own right and thus, when viewed from a second aspect, the present invention provides a method of operating a transmission gate circuit portion arranged selectively to pass an input signal from an input node to an output node said transmission gate comprising:

a control circuit portion arranged to provide first and second control voltages;

a first field-effect-transistor having a drain terminal connected to the input node, a source terminal connected to the output node, and a gate terminal connected to the first control voltage; and

a second field-effect-transistor having a drain terminal connected to the output node, a source terminal connected to the input node, and a gate terminal connected to the second control voltage;

wherein the method comprises:

in a first mode of operation, setting the first control voltage to a non-zero value different to the input voltage and setting the second control voltage to zero; and

in a second mode of operation, setting the first control voltage to zero and setting the second control voltage to the input voltage. Those skilled in the art will appreciate that the features described in relation to various embodiments of the first aspect of the invention apply equally, where appropriate, to the second aspect of the invention. While it will be appreciated by those skilled in the art that there are many applications to which transmission gate circuit portions in accordance with the present invention may be readily applied, in a preferred set of embodiments, the input node is connected to a battery. Thus, in accordance with such embodiments, the transmission gate circuit portion is arranged to pass a voltage from a battery from the input node to the output node, e.g. for digitisation by an ADC.

This is novel and inventive in its own right and thus, when viewed from a third aspect, the present invention provides an electronic circuit portion comprising: a battery having first and second terminals and providing a battery voltage; and

a transmission gate circuit portion arranged selectively to pass the battery voltage from an input node to an output node, said transmission gate comprising: a first field-effect-transistor having a drain terminal connected to the input node, a source terminal connected to the output node, and a gate terminal connected to a first control voltage; and

a second field-effect-transistor having a drain terminal connected to the output node, a source terminal connected to the input node, and a gate terminal connected to a second control voltage;

wherein the transmission gate circuit portion is arranged such that:

in a first mode of operation, the first control voltage is set to a non-zero value different to the battery voltage and the second control voltage is set to zero; and

in a second mode of operation, the first control voltage is set to zero and the second control voltage is set to the battery voltage.

Those skilled in the art will appreciate that the features described in relation to various embodiments of the first and second aspects of the invention apply equally, where appropriate, to the third aspect of the invention. An embodiment of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Fig. 1 is a circuit diagram of a conventional transmission gate circuit portion;

Fig. 2 is a circuit diagram of a transmission gate circuit portion in

accordance with an embodiment of the present invention;

Fig. 3 is a graph comparing a simulation of the on-resistance of the transmission gate circuit portion of Fig. 2 of the conventional transmission gate circuit portion of Fig. 1 ; and

Fig. 4 is a graph comparing a simulation of the off-resistance of the transmission gate circuit portion of Fig. 2 to the conventional transmission gate circuit portion of Fig. 1.

Fig. 1 is a circuit diagram of a conventional transmission gate circuit portion 2. The transmission gate 2 comprises an n-channel metal-oxide-semiconductor field-effect- transistor (nMOSFET) 4 and a p-channel metal-oxide-semiconductor field-effect- transistor (pMOSFET) 6 arranged in parallel such that the drain terminal of the nMOSFET 4 and the source terminal of the pMOSFET 6 are connected to one another and to an input voltage V _in and such that the source terminal of the nMOSFET 4 and the drain terminal of the pMOSFET 6 are connected to one another and produce an output voltage V _ou t- As is typical of such complementary metal-oxide-semiconductor (CMOS) based transmission gates, the nMOSFET 4 and the pMOSFET 6 are "matched" to one another, i.e. they have certain electrical characteristics including their respective drain-source and gate-source breakdown voltages in common with one another.

Complementary control signals are applied to the gate terminals of the nMOSFET 4 and the pMOSFET 6, i.e. the signal applied to the gate terminal of the pMOSFET 6 is at all times the logical negation of the signal applied to the gate terminal of the nMOSFET 4. This is typically achieved by having a control circuit portion 3 that produces a single control signal (in this example, the one applied to the gate terminal of the nMOSFET 4) and a Boolean inverter 5, connected between the gate terminals of the nMOSFET 4 and the pMOSFET 6, which provides the gate terminal of the pMOSFET 6 with the logical negation of the signal produced by the control circuit portion 3. When the transmission gate 2 is driven at "logic high", the gate terminal of the nMOSFET 4 is set to the input voltage V _in and the gate terminal of the pMOSFET 6 is set to 0 V. Conversely, when the transmission gate 2 is driven at "logic low", the gate terminal of the nMOSFET 4 is set to 0 V and the gate terminal of the pMOSFET 6 is set to V _in .

In the logic high state, the gate-source voltage of the nMOSFET 4 is V _in - V _out and the gate-source voltage of the pMOSFET 6 is 0 - V _in = -V _in . Thus, in the logic high state, both the nMOSFET 4 and the pMOSFET 6 conduct, assuming that their respective gate-source voltages exceed their respective threshold voltages.

Conversely, in the logic low state, the gate-source voltage of the nMOSFET 4 is 0 ^{_ v} out = ~ ^v out ^an d ^tne gate-source voltage of the pMOSFET 6 is V _in - V _in = 0. Thus, in the logic low state, neither the nMOSFET 4 nor the pMOSFET 6 conducts, assuming that their respective gate-source voltages are below their respective threshold voltages.

The on-resistance R _on and off-resistance R ₀ ff values (i.e. the effective resistance of the transmission gate circuit portion 2 when it is switched on and switched off respectively) typically presented for two different values of the input voltage V _in are given below in Table 1 :

Table 1: Comparison of on-resistance R _on and off-resistance R ₀ n presented by the transmission gate circuit portion 2 for different input voltage V _in values.

It can be seen from Table 1 that the variation in on-resistance R _on between the cases where the input voltage V _in is 2.5 V and when it is 4.35 V is ±27%. The variation in off-resistance R ₀ ff between the cases where the input voltage V _in is 2.5 V and when it is 4.35 V is ±14%. The Applicant has appreciated that these variations in the on-resistance R _on and off-resistance R ₀ ff values across a typical range of input voltage V _in values are higher than is desirable as these negatively impact the linearity of the transmission gate.

Fig. 2 is a circuit diagram of a transmission gate circuit portion 8 in accordance with an embodiment of the present invention. In common with the conventional arrangement, the transmission gate 8 comprises an n-channel metal-oxide- semiconductor field-effect-transistor (nMOSFET) 10 and a p-channel metal-oxide- semiconductor field-effect-transistor (pMOSFET) 12 arranged in parallel such that the drain terminal of the nMOSFET 10 and the source terminal of the pMOSFET 6 are connected to one another and to an input voltage V _in and such that the source terminal of the nMOSFET 10 and the drain terminal of the pMOSFET 12 are connected to one another and are arranged to produce an output voltage V _ou t-

However, unlike the transmission gate circuit portion 2 of Fig. 1 , the nMOSFET 10 and the pMOSFET 12 are not "matched" to one another. While the pMOSFET 12 is a standard '5 V PMOS device having its respective drain-source, gate-source, gate-drain, and gate-body breakdown voltages all approximately equal to 5.5 V; the nMOSFET 10 is an unconventional NMOS device, where its respective gate- source, gate-drain, and gate-body breakdown voltages are typical of a '3 V NMOS device, i.e. they are around 3.6 V, but the drain-source voltage of the nMOSFET 10 is 5.5 V, i.e. typical of the higher, '5 V, device category.

Furthermore, unlike the transmission gate circuit portion 2 of Fig. 1 , the control signals applied to the gate terminals of the nMOSFET 10 and the pMOSFET 12 are not direct complements of each other. Instead, these control signals (labelled V _S uppi _y / 0 V and 0V / V _in ) are both produced by a control circuit portion 11 independently of one another. Similarly to the transmission gate circuit portion 2 of Fig. 1 , when the transmission gate 8 is driven at logic low, the gate terminal of the nMOSFET 10 is set to 0 V and the gate terminal of the pMOSFET 12 is set to V _in . However, when the transmission gate circuit portion 8 is in the logic high state, the gate terminal of the nMOSFET 10 is set to a supply voltage V _S uppi _y and the gate terminal of the pMOSFET 12 is set to 0 V, wherein the supply voltage V _S uppi _y is different to the input voltage V _in . The supply voltage V _S uppi _y is lower than the input voltage V _in and may be produced from the input voltage V _in , for example using a low-dropout (LDO) voltage regulator, known in the art per se. A lower voltage (i.e. V _S uppi _y ) can be applied to the gate terminal of the nMOSFET 10 than the voltage applied to the gate terminal of pMOSFET 12 (i.e. V _in ) because the gate-source, gate-drain, and gate-body breakdown voltages of the nMOSFET 10 are lower than the corresponding breakdown voltages of the pMOSFET 12.

These lower breakdown voltages provide the nMOSFET 10 with more linear on- and off-resistance behaviours across a range of input voltages V _in as discussed below with reference to Figs. 3 and 4, while the higher drain-source breakdown voltage of the nMOSFET 10 (i.e. substantially equal to the higher drain-source breakdown voltage of the pMOSFET 12) allows the transmission gate circuit portion 8 to handle the same magnitude of input voltages V _in as the conventional transmission gate circuit portion 2 of Fig. 1.

In one exemplary application, the transmission gate circuit portion 8 may be used to monitor a battery voltage. In that example, the battery voltage would serve as the input voltage V _in , while V _S uppi _y would be derived from the battery voltage, for example using a low-dropout (LDO) voltage regulator, known in the art per se.

In the logic high state, the gate-source voltage of the nMOSFET 10 is V _supply - V _out and the gate-source voltage of the pMOSFET 12 is 0 - V _in = -V _in . Thus, in the logic high state, both the nMOSFET 10 and the pMOSFET 12 conduct, assuming that their respective gate-source voltages exceed their respective threshold voltages.

Conversely, in the logic low state, the gate-source voltage of the nMOSFET 10 is 0 ^{_ v} out = ^~v out ^an d ^tne gate-source voltage of the pMOSFET 12 is V _in - V _in = 0. Thus, in the logic low state, neither the nMOSFET 10 nor the pMOSFET 12 conducts, assuming that their respective gate-source voltages are below their respective threshold voltages.

Fig. 3 is a graph comparing a simulation of the on-resistance R _on of the

transmission gate circuit portion 8 of Fig. 2 to the on-resistance R _on exhibited by the conventional transmission gate circuit portion 2 of Fig 1 across different input voltage V _in values.

The graph of Fig. 3 shows a number of curves 14, 16, 18, 20 corresponding to the on-resistance R _on of the transmission gate circuit portions 2, 8 under different operating conditions across a range of input voltage V _in values.

A first curve 14, corresponds to the on-resistance R _on of the conventional transmission gate circuit portion 2 described previously with reference to Fig. 1. The other three curves 16, 18, 20 correspond to the on-resistance R _on of the transmission gate circuit portion 8 in accordance with the embodiment of the invention described previously with reference to Fig. 2 with different supply voltage suppiy values: the uppermost curve 16 of these corresponds to the on-resistance Ron of the transmission gate circuit portion 8 operated with a supply voltage V _S uppi _y of 1.62 V; the middle curve 18 corresponds to the on-resistance R _on of the

transmission gate circuit portion 8 operated with a supply voltage of 3 V; and finally the lowermost curve 20 corresponds to the on-resistance R _on of the transmission gate circuit portion 8 operated with a supply voltage of 3.6 V. As can be seen from the graph, the curves 16, 18, 20 corresponding to the on- resistance Ron of the transmission gate circuit portion 8 have a much shallower gradient than the curve 14 corresponding to the on-resistance R _on of the

conventional transmission gate circuit portion 2. This shows that the on-resistance Ron of the transmission gate circuit portion 8 of the present invention is significantly more consistent across different input voltage V _in values. It can also be seen from the graph that increasing the supply voltage V _S uppi _y provided to the gate terminal of the nMOSFET 10 in the logic high state reduces the on-resistance R _on of the transmission gate circuit portion 8 and also reduces the rate at which the on- resistance Ron increases for increasing input voltage V _in .

The on-resistance R _on of the transmission gate circuit portion 8 is more linear than the conventional transmission gate circuit portion 2 due to the on-resistance of the nMOSFET 10 being lower than the on-resistance of the pMOSFET 12, on account of the gate-source, gate-drain, and gate-body breakdown voltages of the nMOSFET 10 being lower than the respective breakdown voltages of the pMOSFET 12. As the on-resistance exhibited by the transmission gate circuit portion 8 is effectively the parallel combination of the on-resistance of the nMOSFET 10 and the on- resistance of the pMOSFET 12, the on-resistance R _on of the transmission gate is dominated by the on-resistance of the nMOSFET 10. The on-resistance of a regular transmission gate constructed from a conventional nMOSFET-pMOSFET pair typically decreases as the input voltage V _in increases because the on-resistances of both the conventional nMOSFET and pMOSFET decrease as V _in increases. However, the on-resistance behaviour of nMOSFET 10 is different to the on-resistance behaviour exhibited by a conventional nMOSFET as V _in increases.

It is clear from the lowermost curve 20 (i.e. V _S uppi _y = 3.6 V) that the on-resistance R _on of the transmission gate circuit portion 8 is mainly dominated by the on-resistance of the nMOSFET 10 as the on-resistance of the nMOSFET 10 is much smaller than on-resistance of the pMOSFET 12. Therefore, the on-resistance R _on of the transmission gate circuit portion 8 is increases as V _in increases.

With a lower supply voltage (V _S uppi _y = 1.62 V, uppermost curve 16), the on- resistance of the nMOSFET 10 is larger than in the V _S uppi _y = 3.6 V case. However, the on-resistance of the nMOSFET 10 is still much smaller than the on-resistance of the pMOSFET 12. As such, the on-resistance R _on of the transmission gate circuit portion 8 increases as V _in increases.

Fig. 4 is a graph comparing a simulation of the off-resistance of the transmission gate circuit portion 8 of Fig. 2 to the off-resistance R ₀ ff exhibited by the conventional transmission gate circuit portion 2 of Fig 1 across different input voltage V _in values. The graph shows a pair of curves 22, 24, wherein the uppermost curve 22 corresponds to the off-resistance R ₀ ff of the conventional transmission gate circuit portion 2 of Fig. 1 and the lowermost curve 24 corresponds to the off-resistance R ₀ ff of the transmission gate circuit portion 8 of Fig. 2 in accordance with an

embodiment of the present invention.

Some examples of the on-resistance R _on and off-resistance R ₀ ff values (i.e. the effective resistance of the transmission gate circuit portion 8 when it is switched on and switched off respectively) typically presented for different values of the input voltage V _in and supply voltage V _S uppi _y are given below in Table 2:

Table 2: Comparison of on-resistance R _on and off-resistance R _off presented by the transmission gate circuit portion 8 for different supply voltage V _sup pi _y

and input voltage V _in values.

Where the supply voltage V _S uppi _y is 1.62 V, the variation in on-resistance R _on between the cases where the input voltage V _in is 2.5 V and when the input voltage V _in is 4.35 V is ±12%. For the case where the supply voltage V _S uppi _y is 3.6 V, the variation in the on-resistance R _on between the cases where the input voltage V _in is 2.5 V and when the input voltage V _in is 4.35 V is ±12%. Those skilled in the art will appreciate that, compared to the variation of ±27% exhibited by the transmission gate circuit portion 2 of Fig. 1 , the transmission gate circuit portion 8 of Fig.

provides an improved, more consistent on-resistance Ron across different input voltages V _in for a given supply voltage V _SU ppiy.

Furthermore, the variation in off-resistance R ₀ ff between the cases where the input voltage V _in is 2.5 V and when the input voltage V _in is 4.35 V, when the supply voltage V _S uppi _y is 1.62 V or 3.6 V is ±1 %, a substantial improvement over the variation of ±14% in the off-resistance R ₀ ff presented by the transmission gate circuit portion 2 of Fig. 1.

It can clearly be seen from the graph that the off-resistance R ₀ ff of the transmission gate circuit portion 8 is significantly more consistent across the range of input voltage V _in values than the off-resistance R ₀ ff of the conventional transmission gate circuit portion 2, i.e. the gradient of the lower curve 24 is greatly reduced compared to the gradient of the upper curve 22. This is because the off-resistance exhibited by the transmission gate circuit portion 8 is effectively the parallel combination of the off-resistance of the nMOSFET 10 and the off-resistance of the pMOSFET 12. As the nMOSFET 10 is effectively from a 'lower' device category but with a higher drain-source breakdown voltage, the nMOSFET 10 exhibit a smaller off-resistance than the conventional nMOSFET 4 used in the transmission gate circuit portion 2 of Fig. 1 (and, in this case, a smaller off-resistance than the pMOSFET 12). As such, the off-resistance of the transmission gate circuit portion 8 is dominated by the off- resistance of the nMOSFET 10.

Thus it will be appreciated by those skilled in the art that embodiments of the present invention provide an improved transmission gate circuit portion that presents more consistent on-resistance and off-resistance values across a range of input voltage values compared to conventional transmission gate circuit portions, therefore providing a transmission gate circuit portion with improved linearity performance. It will be appreciated by those skilled in the art that the embodiment described above is merely exemplary and is not limiting on the scope of the invention.