CROSS-REFERENCE TO RELATED APPLICATION

[0001] This Application claims priority to and the benefit of United States Patent Application Serial No. 17/949,935 filed in the United States Patent and Trademark Office on September 21, 2022, the entire content of which is incorporated herein as if fully set forth below in its entirety and for all applicable purposes.

FIELD

[0002] Aspects of the present disclosure relate generally to transmitters and/or transceivers, and in particular, to a transmitter or transceiver including a phase lock loop (PLL) including at least two outputs for generating a digital-to-analog (DAC) sampling signal and a radio frequency (RF) local oscillator (LO) signal.

BACKGROUND

[0003] A transmitter may be configured to transmit a set of pulses (e.g., ultra- wideband (UWB) pulses) based on a set of data. The signal including the set of pulses may be frequency upconverted to generate a transmit radio frequency (RF) signal. The transmit RF signal may then be amplified by a power amplifier (PA), and provided to an antenna for wireless transmission. Such transmitter may include phase lock loops (PLLs) to generate clocks or periodic oscillating signals used to generate the transmit RF signal. Reducing the number of components in such transmitter is of interest to reduce transmitter size and costs, and conserve power.

SUMMARY

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005] An aspect of the disclosure relates to a transmitter. The transmitter including a phase lock loop (PLL) configured to generate a digital-to-analog (DAC) sampling signal and a local oscillator (LO) signal; a digital-to-analog (DAC) converter configured to convert a transmit digital signal into a transmit analog signal based on the DAC sampling signal; and a mixer configured to frequency upconvert the transmit analog signal based on the LO signal.

[0006] Another aspect of the disclosure relates to a method of generating a transmit radio frequency (RF) signal. The method includes phase-frequency locking a feedback signal to a reference signal to generate a digital-to-analog (DAC) sampling signal and a local oscillator (LO) signal; converting a transmit digital signal into a transmit analog signal based on the DAC sampling signal; and frequency upconverting the transmit analog signal to generate the transmit RF signal.

[0007] Another aspect of the disclosure relates to an apparatus for generating a transmit analog signal. The apparatus includes a digital pulse shaper configured to generate a transmit digital signal including sets of sample coefficients corresponding to a set of consecutive pulses, respectively, wherein the sets of sample coefficients are generated in accordance with a fractional oversampling ratio (OSR); and a digital-to-analog converter (DAC) configured to generate the transmit analog signal based on the transmit digital signal.

[0008] Another aspect of the disclosure relates to a method of generating a transmit analog signal. The method includes generating a transmit digital signal including sets of sample coefficients corresponding to a set of consecutive pulses, respectively, wherein the sets of sample coefficients are generated in accordance with a fractional oversampling ratio (OSR); and converting the transmit digital signal into the transmit analog signal.

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 illustrates a block diagram of an example transmitter in accordance with an aspect of the disclosure.

[0011] FIG. 2 illustrates a graph of an example transmit analog pulse in accordance with another aspect of the disclosure. [0012] FIG. 3 illustrates a graph of an example transmit digital pulse in accordance with another aspect of the disclosure.

[0013] FIG. 4 illustrates a graph of a frequency spectrum of an example transmit analog pulse in accordance with another aspect of the disclosure.

[0014] FIG. 5A illustrates a graph of an example set of consecutive transmit digital pulses in accordance with another aspect of the disclosure.

[0015] FIG. 5B illustrates a table depicting digital sample coefficients of at least some of the first set of consecutive transmit digital pulses and transmit digital signal associated with FIG. 5A in accordance with another aspect of the disclosure.

[0016] FIG. 6A illustrates a graph of another example set of consecutive transmit digital pulses in accordance with another aspect of the disclosure.

[0017] FIG. 6B illustrates a table depicting digital sample coefficients of at least some of the set of consecutive transmit digital pulses and transmit digital signal associated with FIG. 6A in accordance with another aspect of the disclosure.

[0018] FIG. 7 illustrates a block diagram of another example transmitter in accordance with another aspect of the disclosure.

[0019] FIG. 8 illustrates a block diagram of an example phase lock loop (PLL) in accordance with another aspect of the disclosure.

[0020] FIG. 9 illustrates a table comparing a fixed oversampling ratio (OSR) with variable OSRs for generating a transmit digital signal in a transmitter in accordance with another aspect of the disclosure.

[0021] FIG. 10A illustrates a graph of another example set of consecutive transmit digital pulses in accordance with another aspect of the disclosure.

[0022] FIG. 10B illustrates a table depicting digital sample coefficients of at least some of the set of consecutive transmit digital pulses and transmit digital signal associated with FIG. 10A in accordance with another aspect of the disclosure.

[0023] FIG. 11A illustrates a table depicting digital sample coefficients for a set of consecutive transmit digital pulses sampled in accordance with a fractional oversampling ratio (OSR) of 5.5 in accordance with another aspect of the disclosure.

[0024] FIG. 11B illustrates a table depicting digital sample coefficients for a set of consecutive transmit digital pulses sampled in accordance with a fractional oversampling ratio (OSR) of 4.25 in accordance with another aspect of the disclosure.

[0025] FIG. 12 illustrates a block diagram of at least a portion of an example transmitter in accordance with another aspect of the disclosure. [0026] FIG. 13 illustrates a flow diagram of an example method of generating a transmit radio frequency (RF) signal in accordance with another aspect of the disclosure.

[0027] FIG. 14 illustrates a flow diagram of an example method of generating a transmit analog signal in accordance with another aspect of the disclosure.

DETAILED DESCRIPTION

[0028] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0029] FIG. 1 illustrates a block diagram of an example transmitter 100 in accordance with an aspect of the disclosure. The transmitter 100 includes a digital pulse shaper 105, a digital- to-analog converter (DAC) 110, a DAC sampling phase lock loop (PLL) 115, a frequency-upcon verting mixer 120, a radio frequency (RF) local oscillator (LO) PLL 125, and a power amplifier (PA) 130. It shall be understood that the transmitter 100 is an example, and the transmitter 100 may be configured differently including more or less components as exemplified in FIG. 1. Further, it shall be understood that the transmitter 100 may be part of a transceiver including an associated receiver.

[0030] The digital pulse shaper 105 is configured to receive transmit (Tx) data (which in some applications could be a repeated pre-defined data set), and generate a transmit digital signal DTX based on the Tx data. For example, the transmit digital signal DTX may be samples of a pulse, such as an ultra- wideband (UWB) pulse, indicative of logic information of the current Tx data. For instance, if the current Tx data is a logic one (1), the digital pulse shaper 105 may generate the transmit digital signal DTX to include a positive pulse (e.g., the main pulse lobe initially rises and then falls). If the current Tx data is a logic zero (0), the digital pulse shaper 105 may generate transmit digital signal DTX to include a negative pulse (e.g., the main pulse lobe initially falls and then rises). [0031] Alternatively, the digital pulse shaper 105 may generate the transmit digital signal DTX to represent a ternary logic signal. For example, the Tx input data could be 2 bits of parallel inputs at 500 mega bits per second (Mbps), with bit<l> as a logic one (1) and bit<0> as another logic one (1) , then the digital pulse shaper 105 may generate the transmit digital signal DTX to include a positive pulse. Similarly, if the 2 bits of parallel inputs send a logic one (1) at bit<l> and a logic zero (0) at bit<0> , then the digital pulse shaper 105 may generate the transmit digital signal DTX to include a negative pulse. And if bit<l> of the 2 bits Tx data input is a logic zero (0), regardless of the status of bit<0>, which could be considered as a “don’t care”, then the digital pulse shaper 105 may generate the transmit digital signal DTX to include no pulse (or an absence of a pulse).

[0032] With regard to UWB pulses, UWB connectivity is a short-range, wireless communication protocol that operates with a very high frequency as compared to other short-range wireless communication technologies (e.g., Bluetooth, wide local area network (WLAN), Zigbee, or the like), and uses a relatively wide frequency band (e.g., 500 MHz or greater) as compared to other short-range wireless communication technologies, which makes UWB useable for high-resolution positioning and localization purposes. In some cases, UWB technology may be used for location discovery, device ranging, or the like. In some cases, a UWB transmitter (e.g., the transceiver 100 or 700 implemented as a UWB transmitter) may transmit numerous pulses across the wide spectrum frequency, and a corresponding UWB receiver (e.g., located at another UWB-enabled device) may translate the pulses into data.

[0033] The digital pulse shaper 105 may generate the transmit digital signal DTX based on a DAC sampling signal fs generated by the DAC sampling PLL 115. For simplicity’s sake, the term “fs” may refer to the DAC sampling signal or the frequency of the DAC sampling signal depending how the term is used. As discussed in more detail further herein, a pulse may have a main lobe width represented as a unit interval (UI). For example, in the pulses exemplified herein, each pulse has a UI of two (2) nanoseconds (ns), but it shall be understood that the UI may be different depending on the requirements and application for the transmitter. The DAC sampling signal fs sets the number of samples of the transmit digital signal DTX to generate a UI of a pulse. If the number of samples to generate a UI of a pulse is two (2), it may be said that the DAC sampling signal fs has an oversampling ratio (OSR) of 2x. If the number of samples to generate a UI of a pulse is four (4), the DAC sampling signal fs has an OSR of 4x. And, if the number of samples to generate a UI of a pulse is eight (8), the DAC sampling signal fs has an OSR of 8x. [0034] The pulses (including no pulse intervals) of the transmit digital signal DTX are generated every UI. As discussed above, in the examples provided herein, the UI is 2ns. Accordingly, the pulses (including no pulse intervals) are generated at a rate fp of 500 mega Hertz (MHz) (e.g., update every 2ns). If the OSR is 2x, then the frequency of the DAC sampling signal fs is one (1) giga Hertz (GHz) (e.g., 2x500MHz). If the OSR is 4x, then the frequency of the DAC sampling signal fs is 2GHz (e.g., 4x500MHz). And, if the OSR is 8x, then the frequency of the DAC sampling signal fs is 4GHz (e.g., 8x500MHz).

[0035] The transmit digital signal DTX is provided to the DAC 110, which is configured to convert the transmit digital signal DTX into a transmit analog signal VTX. Although in example implementations described herein, the DAC sampling signal f s generated by the DAC sampling PLL 115 is provided to the digital pulse shaper 105, the DAC sampling signal fs controls the rate at which the DAC 110 converts the transmit digital signal DTX into a transmit analog signal VTX, as discussed further herein.

[0036] The frequency-upcon verting mixer 120 is configured to mix the transmit analog signal VTX with an LO signal fpo generated by the RF LO PLL 125 to generate a transmit RF signal RFTX- For simplicity’s sake, the term “/LO” may refer to the LO signal or the frequency of the LO signal depending how the term is used. It shall be understood that the transmitters described herein may include more than one frequency-upconverting mixer stage. For example, the transmitter 100 may include a first mixer stage configured to frequency upconvert the transmit analog signal VTX into an intermediate frequency (IF) transmit signal, and then a second mixer stage configured to frequency upconvert the IF transmit signal into the transmit RF signal RFTX- In this example, the LO signal fpo may serve as the carrier component of the transmit RF signal RFTX-

[0037] The PA 130 is configured to amplify the transmit RF signal RFTX to a particular power level for transmission to one or more wireless devices (e.g., in the case of communication applications) and/or one or more objects (e.g., in the case of radar applications). The output of the PA 130 may be coupled to an antenna to radiate the amplified transmit RF signal RFATX to effectuate the remote transmission to the one or more wireless devices and/or objects. As alluded to above, the transmitter 100 may include additional components between the PA 130 and the antenna, such as a directional coupler, power detector, diplexer, duplexer, filter, etc.

[0038] FIG. 2 illustrates a graph of an example transmit analog pulse VTX in accordance with another aspect of the disclosure. The x- or horizontal-axis of the graph represents time in nanoseconds (ns) extending from zero (0) to 8ns. The y- or vertical-axis of the graph represents normalized amplitude with respect to a peak of the transmit analog pulse VTX, extending from -0.2 to 1.0.

[0039] As illustrated, the example transmit analog pulse VTX may be in the form of a raised- cosine pulse. It may not be desirable for such pulse to take on a square or rectangular shape as such pulse has a relatively wide spectrum. If the transmission of the amplified transmit RF signal RFATX is within an assigned frequency channel among a set of defined frequency-staggered channels, there may be a specification as to the width of the spectrum of the transmit RF signal RFATX SO as not to interfere with the transmission of an adjacent frequency channel. Such specification is often referred to as a spectrum emission mask (SEM). On the other hand, the raised-cosine pulse has a relatively narrow spectrum, and may be preferred over a square or rectangular pulse based on the governing SEM.

[0040] In this example, the raised-cosine pulse VTX has a main lobe centered within a UI of 2ns; for example, within UI extending from 3ns to 5ns. Further, the raised-cosine pulse VTX has a sinewave-looking leader extending from 0ns to 3ns, and a sinewave-looking trailer extending from 5ns to 8ns. Because raised-cosine pulse VTX has relatively smooth curves, compared to the step changes of a square or rectangular pulse, the spectrum of the raised- cosine pulse VTX is narrow compared to a square or rectangular pulse with the same UI.

[0041] FIG. 3 illustrates a graph of an example transmit digital pulse DTX in accordance with another aspect of the disclosure. The x- or horizontal-axis of the graph represents time in nanoseconds (ns) extending from zero (0) to 6ns. The y- or vertical-axis of the graph represents amplitude of the transmit digital pulse DTX, extending from -5 to 35.

[0042] The transmit digital pulse DTX may be an example of a transmit digital signal generated by the digital pulse shaper 105 that results in the DAC 110 generating the raised-cosine pulse VTX, as discussed with reference to FIG. 2. In this example, the transmit digital pulse DTX may extend three (3) UIs, with a leader portion of the pulse extending from 0 to 2ns, a main lobe of the pulse extending from 2ns to 4ns, and a trailer portion of the pulse extending from 4ns to 6ns. With the pulse shaper’s coefficients being quantized and the pulse transmit length limited in this example, this may be a more practical implementation.

[0043] Further, in accordance with this example, the transmit digital pulse DTX has an oversampling ratio (OSR) of 8x. That is, for each UI (e.g., 2ns), there are eight (8) samples. For example, within the UI corresponding to the main lobe of the pulse, the eight (8) samples correspond to: (1) time interval 2ns to 2.25ns where DTX has a sample coefficient of 16; (2) time interval 2.25ns to 2.5ns where DTX has a sample coefficient of 22; (3) time interval 2.5ns to 2.75ns where DTX has a sample coefficient of 27; (4) time interval 2.75ns to 3ns where DTX has a sample coefficient of 30; (5) time interval 3ns to 3.25ns where DTX has a sample coefficient of 31; (6) time interval 3.25ns to 3.5ns where DTX has a sample coefficient of 30; (7) time interval 3.5ns to 3.75ns where DTX has a sample coefficient of 27; and (8) time interval 3.75ns to 4ns where DTX has a sample coefficient of 22. The leader portion UI (e.g., between 0ns to 2ns) and the trailer portion UI (e.g., 4ns to 6ns) each also have eight (8) samples. Although, in this example, the OSR is eight (8), it shall be understood that the transmit digital signal DTX may be generated with different OSRs, as discussed further herein.

[0044] In this example, the transmit digital pulse DTX may be quantized to a signed five (5) bit, ranging from -31 to +31. The example transmit digital pulse DTX, which is a positive pulse, extends from a sample coefficient of -5 to a sample coefficient of +31. An example of a negative transmit digital pulse DTX may extend from +5 to -31 , as discussed further herein. An extra bit may also be added to extend the range to -47 to +47 for cases where data pulses could overlap with each other so that a higher peak is expected. It shall be understood that the quantization of the transmit digital pulse DTX may be different to include more or less bits depending on various design factors.

[0045] FIG. 4 illustrates a graph of a frequency spectrum of an example transmit analog pulse VTX in accordance with another aspect of the disclosure. The x- or horizontal- axis of the graph represents normalized frequency in terms of the pulse rate fp, extending from zero (0) where the center of the main peak lies in frequency to beyond 2fp. The y- or verticalaxis represents magnitude of the frequency constituents of the transmit analog pulse VTX- As the transmit signal pulses are transmitted at 500Mbps (fp), null happen at every 500MHz.

[0046] Accompanying the graph is a table illustrating the effects of different OSRs on the spectrum of the transmit analog pulse VTX- The table includes a left column representing the different OSRs (e.g., OSR=2x in row 1; OSR=4x in row 2; and OSR=8x in row 3). The middle column of the table represents the frequency of the closest sideband associated with DAC image (e.g., 0.75GHz in row 1; 1.75GHz in row 2; and 3.75GHz in row 3; where UI is 2ns or the pulse rate fp is at 500MHz). The right column of the table represents the sideband (SB) rejection or the amount of decibels relative to a reference (dBr) below the main peak (reference) where the magnitude of the closest sideband or first image lies (e.g., -15.5dBr in row 1; -18.5dBr in row 2; and -24.5dBr in row 3). [0047] As FIG. 4 illustrates, the higher the OSR, the farther away in frequency is the closest sideband or first image, and the lower in magnitude is the peak of the closest sideband or first image relative to the main peak. As an example, a SEM may specify a sideband rejection of -18 dBr. In such case, the C)SR=2x would be insufficient to meet the -18dBr SEM requirement as it can only achieve a sideband rejection of -15.5dBr. The C)SR=4x would marginally meet the -18dBr SEM requirement with a sideband rejection of - 18.5dBr, which may not provide sufficient margin to take into account tolerances in the design. However, the OSR 8x with a sideband rejection of -24.5dBr may provide sufficient margin beyond the -18dBr SEM requirement that it may be suitable for such application. Higher OSRs (e.g., 16x or more) may provide improved sideband rejection, but would result in significantly higher DAC sampling frequency fs (e.g., I 6X500MHZ=8GHZ) that would adversely impact power consumption and design complexity.

[0048] FIG. 5A illustrates a graph of an example set of consecutive transmit digital pulses DTX in accordance with another aspect of the disclosure. The x- or horizontal-axis of the graph represents time in nanoseconds (ns) extending from zero (0) to 10ns. The y- or verticalaxis of the graph represents amplitude of the transmit digital pulse DTX, extending from - 5 to 31. A table, accompanying the graph, is provided as a legend to identify each of the pulses and the bit each of the pulses represents.

[0049] In this example, the set of consecutive transmit digital pulses DTX are a set of positive pulses, which may represent a digital stream of four consecutive ones (Is) (e.g., l/l/l/l). As previously discussed, each pulse may extend three (3) UIs with a leader portion spanning the first UI, the main lobe portion spanning the second UI, and the trailer portion spanning the third UI. In accordance with the ongoing example, a UI may span a 2ns interval.

[0050] For example, the first pulse (“pulse 1”), represented as a small, dashed line, extends from 0ns to 6ns, with its leader between 0 to 2ns, its main lobe between 2ns to 4ns, and its trailer between 4ns to 6ns. The second pulse (“pulse 2”), represented as a large, dashed line, extends from 2ns to 8ns, with its leader between 2ns to 4ns, its main lobe between 4ns to 6ns, and its trailer between 6ns to 8ns. The third pulse (“pulse 3”), represented as a solid line, extends from 4ns to 10ns, with its leader between 4ns to 6ns, its main lobe between 6ns to 8ns, and its trailer between 8ns to 10ns. The fourth pulse (“pulse 4”), represented as a dotted line, extends from 6ns to 12ns, with its leader between 6ns to 8ns, its main lobe between 8ns to 10ns, and its trailer between 10ns to 12ns (not shown because it extends beyond the graph’s time dimension).

[0051] Note that the pulses overlap with each other. For example, the first and second pulses overlap during time interval 2ns to 6ns; the first, second, and third pulses overlap during time interval 4ns to 6ns; the second, third, and fourth pulses overlap during time interval 6ns to 8ns; and the third and fourth pulses overlap during time interval 8ns to 10ns. Thus, as discussed, since each pulse spans three (3) UIs and adjacent pulses are spaced apart by one (1) UI, then each pulse overlaps with an adjacent pulse by two (2) UIs. The sample coefficient of the transmit digital signal DTX at a particular sample or tap (sample index) is the cumulative sum of the sample coefficients of the overlapping pulses. For example, the sample coefficient of the transmit digital signal DTX at tap 16 is 29 (e.g., 16 from pulse 1, 16 from pulse 2, and -3 from pulse 3; or 16+ 16-3=29).

[0052] FIG. 5B illustrates a table depicting sample coefficients of the first, second, and third consecutive pulses of FIG. 5A and transmit digital signal DTX at various taps in accordance with another aspect of the disclosure. The left column represents the pulses and transmit digital signal DTX (e.g., pulse 1 in row 1, pulse 2 in row 2, pulse 3 in row 3, pulse 4 in row 4, and DTX in row 5). The remaining columns, from left-to-right, represents the sets of sample coefficients of the pulses and the transmit digital signal DTX corresponding to taps zero (0) to 17, respectively.

[0053] For example, at tap 0, the first pulse has a sample coefficient of -3. Per this example, there are no other pulses overlapping with the first pulse at tap 0. Accordingly, the transmit digital signal DTX also has a sample coefficient of -3 at tap 0. For the first UI (e.g., taps 0 to 7), there are no pulses overlapping with the first pulse; and thus, the sample coefficients for the first pulse, as well as the transmit digital signal DTX, for taps 1-7 are - 4, -5, -4, 3, 0, 5, and 10, respectively.

[0054] At tap 8 (or the beginning of the second UI), the first pulse begins to overlap with the second pulse. Accordingly, the sample coefficient of the first pulse at tap 8 is 16, and the sample coefficient of the second pulse at tap 8 is -3. Thus, the transmit digital signal DTX at tap 8 has a sample coefficient of 13 (e.g., 16-3= 13). Similarly, for the second UI (e.g., taps 8 to 15), only the first and second pulses overlap; and thus, the sample coefficients for the first and second pulses, and the transmit digital signal DTX for taps 9-15 are [22, - 4, 18], [27, -5, 22], [30, -4, 26], [31, -3, 28], [30, 0, 30], [27, 5, 32], and [22, 10, 32], respectively. [0055] At tap 16 (or the beginning of the third UI), the first and second pulses begin to overlap with the third pulse. Accordingly, the sample coefficient of the first pulse at tap 16 is 16, the sample coefficient of the second pulse at tap 16 is 16, and the sample coefficient of the third pulse at tap 16 is -3. Thus, the transmit digital signal DTX at tap 16 has a sample coefficient of 29 (e.g., 16+ 16-3=29). Similarly, for the third UI (e.g., taps 16 to 23), only the first, second, and third pulses overlap; and thus, the sample coefficients for the first, second, and third pulses, and the transmit digital signal DTX for tap 17 is [10, 22, -4, 28]. The sample coefficients for the pulses and the transmit digital signal DTX may be determined for the remaining taps in the third UI, the fourth UI, and so on.

[0056] The digital pulse shaper 105 may include a memory (e.g., a firmware register) with the set of sample coefficients for each positive pulse (as well as a negative pulse, as discussed further herein), a counter driven by the DAC sampling signal fs to keep track of the taps, and a summer to sum the sample coefficients of the overlapping pulses to generate the transmit digital signal DTX based on the received Tx data.

[0057] FIG. 6A illustrates a graph of another example set of consecutive transmit digital pulses DTX in accordance with another aspect of the disclosure. The x- or horizontal- axis of the graph represents time in nanoseconds (ns) extending from zero (0) to 12ns. The y- or vertical- axis of the graph represents amplitude of the transmit digital signal DTX, extending from -40 to +40. A table, accompanying the graph, is provided as a legend to identify each of the pulses and the bit each of the pulses represents.

[0058] In this example, the set of consecutive transmit digital pulses DTX are a set of pulses representing a bit stream of 1/- 1/1/1. As previously discussed, each pulse may extend three (3) UIs with a leader portion spanning the first UI, the main lobe portion spanning the second UI, and a trailer portion spanning the third UI. In accordance with the ongoing example, a UI may span a 2ns interval.

[0059] For example, the first pulse (“pulse 1”), represented as a small, dashed line, extends from 0ns to 6ns, with its leader between 0 to 2ns, its main lobe between 2ns to 4ns, and its trailer between 4ns to 6ns. The second pulse (“pulse 2”), represented as a large, dashed line, extends from 2ns to 8ns, with its leader between 2ns to 4ns, its main lobe between 4ns to 6ns, and its trailer between 6ns to 8ns. The third pulse (“pulse 3”), represented as a solid line, extends from 4ns to 10ns, with its leader between 4ns to 6ns, its main lobe between 6ns to 8ns, and its trailer between 8ns to 10ns. The fourth pulse (“pulse 4”), represented as a dotted line, extends 6ns to 12ns, with its leader between 6ns to 8ns, its main lobe between 8ns to 10ns, and its trailer between 10ns to 12ns. [0060] As previously discussed, the pulses overlap with each other. For example, the first and second pulses overlap during time interval 2ns to 4ns; the first, second, and third pulses overlap during time interval 4ns to 6ns; the second, third, and fourth pulses overlap during time interval 6ns to 8ns; and the third and fourth pulses overlap during time interval 8ns to 10ns. Thus, as discussed, since each pulse spans three (3) UIs and adjacent pulses are spaced apart by one (1) UI, then each pulse overlaps with an adjacent pulse by two (2) UIs. Also, as previously discussed, the sample coefficient of the transmit digital signal DTX at a particular sample or tap is the cumulative sum of the sample coefficients of the overlapping pulses.

[0061] FIG. 6B illustrates a table depicting sets of sample coefficients of the first, second, and third pulses of FIG. 6A and the transmit digital signal DTX at various taps in accordance with another aspect of the disclosure. The left column represents the pulses and the transmit digital signal DTX (e.g., pulse 1 in row 1, pulse 2 in row 2, pulse 3 in row 3, pulse 4 in row 4, and DTX in row 5). The remaining columns, from left-to-right, represents the different sample coefficients of the pulses and the transmit digital signal DTX corresponding to taps zero (0) to 17, respectively.

[0062] Similar to the previous example, for the first UI (e.g., taps 0 to 7), there are no pulses overlapping with the first pulse; and thus, the sample coefficients for the first pulse, as well as the transmit digital signal DTX, for taps 0-7 are -3, -4, -5, -4, -3, 0, 5, and 10, respectively.

[0063] At tap 8 (or the beginning of the second UI), the first pulse begins to overlap with the second pulse. In contrast to the previous example, the second pulse is a negative pulse; and accordingly, has a different (e.g., opposite sign) set of sample coefficients than a positive pulse. Accordingly, the sample coefficient of the first pulse at tap 8 is 16, and the sample coefficient of the second pulse at tap 8 is 3. Thus, the transmit digital signal DTX at tap 8 has a sample coefficient of 19 (e.g., 16+3= 19). Similarly, for the second UI (e.g., taps 8 to 15), only the first and second pulses overlap; and thus, the sample v coefficients for the first and second pulses, and the transmit digital signal DTX for taps 9-15 are [22, 4, 26], [27, 5, 32], [30, 4, 34], [31, 3, 34], [30, 0, 30], [27, -5, 22], and [22, -10, 12], respectively.

[0064] At tap 16 (or the beginning of the third UI), the first and second pulses begin to overlap with the third pulse. Accordingly, the sample coefficient of the first pulse at tap 16 is 16, the sample coefficient of the second pulse at tap 16 is -16, and the sample coefficient of the third pulse at tap 16 is -3. Thus, the transmit digital signal DTX at tap 16 has a sample coefficient of -3 (e.g., 16- 16-3=-3). Similarly, for the third UI (e.g., taps 16 to 23), only the first, second, and third pulses overlap; and thus, the sample coefficients for the first, second, and third pulses, and the transmit digital signal DTX for tap 17 is [10, -22, -4, - 16]. The sample coefficients for the pulses and the transmit digital signal DTX may be determined for the remaining taps in the third UI, the fourth UI, and so on.

[0065] FIG. 7 illustrates a block diagram of another example transmitter 700 in accordance with another aspect of the disclosure. A drawback of the transmitter 100 previously discussed is that it requires two PLLs: the DAC sampling PLL 115 configured to generate the DAC sampling signal fs and the RF LO PLL 125 configured to generate the LO signal fro. Thus, for transmitter 100, significant circuit area or integrated circuit (IC) area or footprint is needed to accommodate the two PLLs 115 and 125. Further, both PLLs 115 and 125 are consuming power in generating the DAC sampling signal fs and the LO signal fro, respectively. As discussed further herein, the transmitter 700 includes a single PLL configured to generate both the DAC sampling signal fs and the LO signal fro.

[0066] In particular, the transmitter 700 includes a digital pulse shaper 705, a digital-to-analog converter (DAC) 710, a dual-output phase lock loop (PLL) 715 , a frequency-upcon verting mixer 720, and a power amplifier (PA) 730. It shall be understood that the transmitter 700 is an example, and the transmitter 700 may be configured differently including more or less components as exemplified in FIG. 7. Further, it shall be understood that the transmitter 700 may be part of a transceiver including an associated receiver.

[0067] The digital pulse shaper 705 is configured to receive transmit (Tx) data, and generate a transmit digital signal DTX based on the Tx data. For example, the transmit digital signal DTX may be samples of a pulse, such as an ultra-wideband (UWB) pulse, indicative of logic information of the current Tx data. For instance, if the current Tx data is a logic one (1), the digital pulse shaper 705 may generate the transmit digital signal DTX to include a positive pulse. If the current Tx data is a logic zero (0), the digital pulse shaper 705 may generate the transmit digital signal DTX to include a negative pulse.

[0068] Alternatively, the digital pulse shaper 705 may generate the transmit digital signal DTX to represent a ternary logic signal. For example, a previously discussed, the Tx input data could be 2 bits of parallel inputs at 500 mega bits per second (Mbps), with bit<l> as a logic one (1) and bit<0> as another logic one (1) , then the digital pulse shaper 105 may generate the transmit digital signal DTX to include a positive pulse. Similarly, if the 2 bits of parallel inputs send a logic one (1) at bit<l> and a logic zero (0) at bit<0> , then the digital pulse shaper 105 may generate the transmit digital signal DTX to include a negative pulse. And if bit<l> of the 2 bits Tx data input is a logic zero (0), regardless of the status of bit<0>, which could be considered as a “don’t care”, then the digital pulse shaper 105 may generate the transmit digital signal DTX to include no pulse (or an absence of a pulse). [0069] The digital pulse shaper 705 may generate the transmit digital signal DTX based on a DAC sampling signal fs generated by the dual-output PLL 715. As previously discussed, the DAC sampling signal f s sets the number of samples of the transmit digital signal DTX to generate a UI of a pulse. If the number of samples to generate a UI of a pulse is two (2), it may be said that the DAC sampling signal fs has an OSR of 2x. If the number of samples to generate a UI of a pulse is four (4), the DAC sampling signal fs has an OSR of 4x. And, if the number of samples to generate a UI of a pulse is eight (8), the DAC sampling signal f s has an OSR of 8x.

[0070] The pulses (including no pulse intervals) of the transmit digital signal DTX are generated every UI. Considering the ongoing example, a UI may be 2ns. Accordingly, the pulses (including no pulse intervals) are generated at a rate of 500 MHz (e.g., l/2ns). If the OSR is 2x, then the frequency of the DAC sampling signal fs is 1GHz (e.g., 2x500MHz). If the OSR is 4x, then the frequency of the DAC sampling signal fs is 2GHz (e.g., 4x500MHz). And, if the OSR is 8x, then the frequency of the DAC sampling signal fs is 4GHz (e.g., 8x500MHz).

[0071] The transmit digital signal DTX is provided to the DAC 710, which is configured to convert the transmit digital signal DTX into a transmit analog signal VTX- Although the DAC sampling signal fs generated by the dual-output PLL 715 is provided to the digital pulse shaper 705, the DAC sampling signal fs controls the rate at which the DAC 710 converts the transmit digital signal DTX into the transmit analog signal VTX-

[0072] The frequency-upcon verting mixer 720 is configured to mix the transmit analog signal VTX with an LO signal /LO also generated by the dual-output PLL 715 to generate a transmit RF signal RFTX. AS previously discussed, it shall be understood that the transmitter 700 may include more than one frequency-upconverting mixer stage. For example, the transmitter 700 may include a first mixer stage configured to frequency upconvert the transmit analog signal VTX into an intermediate frequency (IF) transmit signal, and then a second mixer stage configured to frequency upconvert the IF transmit signal into the transmit RF signal RFTX- In this example, the LO signal f LO may serve as the carrier component of the transmit RF signal RFTX.

[0073] The PA 730 is configured to amplify the transmit RF signal RFTX to a particular power level for transmission to one or more wireless devices (e.g., in the case of communication applications) and/or one or more objects (e.g., in the case of radar applications). The output of the PA 730 may be coupled to an antenna to radiate the amplified transmit RF signal RFATX to effectuate the remote transmission to the one or more wireless device and/or objects. As alluded to above, the transmitter 700 may include additional components between the PA 730 and the antenna, such as a directional coupler, power detector, diplexer, duplexer, filter, etc.

[0074] FIG. 8 illustrates a block diagram of an example dual-output phase lock loop (PLL) 800 in accordance with another aspect of the disclosure. The dual-output PLL 800 may be an example implementation of the dual-output PLL 715 of transmitter 700. Although the PLLs 715 and 800 are described as having dual outputs, it shall be understood that the PLLs 715 and 800 may each have more than two outputs for generating periodic oscillating signals or clocks.

[0075] In particular, the PLL 800 includes a phase-frequency detector (PFD) 805, a charge pump (CP) 810, a low pass filter (LPF) 815, a voltage controlled oscillator (VCO) 820, a buffer 830, a divide-by-M frequency divider 835, a divide-by-P frequency divider 840, and a divide-by-N frequency divider 845.

[0076] The PFD 805 is configured to compare the phase-frequency of an input reference signal REF (e.g., a clock) to the phase-frequency of a feedback signal fin to generate a control signal err+/err- for the charge pump 810. The charge pump 810 is configured to charge or discharge an internal capacitor based on the control signal err+/err-, respectively. For example, if the phase-frequency of the feedback signal I B is lagging the phase-frequency of the REF signal, then the err-i- component of the control signal is asserted and the err- component of the control signal is not asserted; thereby, causing the CP 810 to charge the internal capacitor to increase a voltage Vi. If the phase-frequency of the feedback signal fin is leading the phase-frequency of the REF signal, then the err-i- component of the control signal is not asserted and the err- component of the control signal is asserted; thereby, causing the CP 810 to discharge the internal capacitor to decrease the voltage Vi. Thus, the charge pump is configured to generate a first voltage Vi based on the control signal err_/err-.

[0077] The LPF 815 filters the voltage Vi to substantially eliminate high frequency components therein so as to generate a VCO frequency control voltage V2. The VCO 820 is configured to generate a VCO signal .fvco whose frequency is controlled by the voltage V2 to maintain the feedback signal in phase-frequency locked with the REF signal. The VCO signal fvco is provided to the divide-by-M frequency divider 835 via the buffer 830. The frequency divider 835 is configured to frequency divide the VCO signal .fvco by an integer M to generate the LO signal /LO- Similarly, the LO signal fix, is provided to the frequency divider 845, which is configured to frequency divide the LO signal fix, by an integer N to generate the DAC sampling signal fs. In a like manner, the LO signal fix, is also provided to the frequency divider 840, which is configured to frequency divide the LO signal fix, by an integer P to generate the feedback signal fin (e.g., through frequency dividers 835 and 840, the feedback signal fi n is based on the VCO signal fvco). The divider ratio P of the frequency divider 840 may be variable, and may depend on a select channel signal CH. It shall be understood that the PLL 800 is an example, and the PLL 800 may be configured differently including more or less components exemplified in FIG. 8.

[0078] FIG. 9 illustrates a table for comparing a fixed oversampling ratio (OSR) and variable OSR associated with generating transmit digital signal DTX in accordance with another aspect of the disclosure. The left column of the table represents different transmission (e.g., UWB) channels, such as channel 5 in row 1, channel 6 in row 2, channel 8 in row 3, and channel 9 in row 4. The next three (3) columns to the left of the UWB channel column pertain to a fixed OSR of eight (8), and they include the frequency of the LO signal /LO, the frequency of the DAC sampling signal fs, and the ratio of the frequencies fro/fs- The next three (3) columns, to the left of the three (3) columns pertaining to the fixed OSR of eight (8), pertain to a variable OSR, and they include the frequency of the LO signal fix,, the frequency of the DAC sampling signal fs, and the ratio of the frequencies fro/fs-

[0079] In both the fixed and variable OSR sections, the frequencies of the LO signal fix, for channels CH5, CH6, CH8, and CH9 are 6500MHz, 7000MHz, 7500MHz, and 8000MHz, respectively. These frequencies may be an integer multiple P of the pulse rate fp or 1/UI (e.g., l/(2ns) or 500 MHz). For example, the integer P is 13, 14, 15, and 16 for channels 5, 6, 8, and 9. With regard to the PLL 800, the integer P may correspond to the divider ratio P of frequency divider 840 and the REF signal may have a frequency of 500 MHz. In the case of the fixed OSR=8. the frequency of the DAC sampling fs is fixed at the OSR x 1/UI; or in this example, 8 x l/2ns = 8 x 500 MHz = 4000 MHz.

[0080] An issue with the fixed OSR is that the frequency divider 845 needs to be implemented as a fractional frequency divider. This is indicated in the table as the column pertaining to the ratio fw/f s- The ratio fixffs is the same as the divider ratio N of frequency divider 845 if the frequency divider 845 were to be configured as a fractional divider. For example, with regard to channel 5, the ratio fw/fs is 13/8; with regard to channel 6, the ratio fLo/ s is 7/8; with regard to channel 8, the ratio .fro/.fs is 15/8; and with regard to channel 9, the ratio .fro/.fs is 2. Accordingly for channels 1-3, the frequency divider 845 is configured to produce divider ratios 13/8, 7/4, and 15/8, respectively. Fractional frequency division is very complex (e.g., requiring significant number of components) and typically consumes significant power. It would be more desirable to implement the frequency divider 845 as an integer M divider for design simplicity and reduced power consumption.

[0081] With regard to the variable OSR, the frequency divider 845 may be implemented with an integer divider ratio M (e.g., M=2; or more generally, M=2 ^T , where T is a positive integer). Thus, as indicated in the column pertaining to the ratio f o/fs for the variable OSR, the ratio f o/fs or the divider ratio M of the frequency divider 845 is set to two (2) for all channels 1-4. However, in doing so, the OSR varies per the current channel. For example, for channel 5, the OSR is 6.5, which corresponds to a DAC sampling frequency fs of 3250 MHz ( LO/2); for channel 6, the OSR=7, which corresponds to a DAC sampling frequency fs of 3500 MHz ( LO/2); for channel 8, the OSR=7.5. which corresponds to a DAC sampling frequency fs of 3750 MHz ( LO/2); and for channel 9, the OSR=8. which corresponds to a DAC sampling frequency fs of 4000 MHz (/LO/2).

[0082] With regard to integer OSRs, such as 7 for channel 6, and 8 for channel 9, the digital pulse shaper 105 or 705 may generate the sample coefficients for the transmit digital signal DTX in a similar manner as the digital pulse shaper 105 or 705 generates the sample coefficients for the C)SR=8 examples discussed with reference to FIGs. 5A-5B and 6A- 6B. That is, sample coefficients are generated at the start and end boundaries of each UI because the OSR is an integer. However, for fractional OSRs, such as 6.5 for channel 5, and 7.5 for channel 8, a sample coefficient may be generated at one boundary (e.g., at the start) of a UI, but a sample coefficients cannot be generated at the other boundary (e.g., at the end) of the UI. The following further elaborates on fractional OSR and solutions as to how to handle the generation of the transmit digital signal DTX based on a fractional OSR.

[0083] FIG. 10A illustrates a graph of another example set of consecutive transmit digital pulses in accordance with another aspect of the disclosure. The x- or horizontal-axis of the graph represents time in nanoseconds (ns) extending from 0ns to 7ns. The y- or vertical-axis of the graph represents amplitude of the transmit digital pulse DTX, extending from -5 to +31. A table, accompanying the graph, is provided as a legend to identify each of the pulses and the bits each of the pulses represents.

[0084] In this example, the set of consecutive transmit digital pulses DTX are a set of pulses representing a bit stream of 1/1/1. Further, in accordance with this example, the OSR for the transmit digital signal DTX is 6.5. That is, there are 6.5 samples per UI (e.g., 2ns). As such, the last sample of every odd UI begins before and terminates after the boundary between the odd and even UIs. Whereas, the last sample of every even UI ends at the boundary between the even and odd UIs.

[0085] For example, with regard to the first pulse (“pulse 1”), represented as a solid line, there are 6.5 samples between 0ns to 2ns (the first UI), with the seventh sample (with a sample value of 4) beginning before the 2ns (e.g., at ~1.846ns) and ending after the 2ns (e.g., at ~2.154ns). However, the 13 ^th sample (with a sample value of 29) ends at 4ns (boundary between the first and second UIs). This is because with an OSR of 6.5, there are 13 (integer) samples for every two consecutive UIs. Thus, as discussed further herein, when the fractional part of an OSR is 0.5, there are an integer number of samples per every two consecutive UIs.

[0086] With regard to the second pulse (“pulse 2”), represented as a larger dashed line, there are 6 samples between 2ns to 4ns (the second UI), with its first sample (with a sample value of -2) not starting at the beginning of the second UI, but at ~2.154ns but ending at the end of the second UI at 4ns. However, the 13 ^th sample (with a sample value of 27) ends at slightly after the third UI at 6.154ns. Similarly, with a 2UI time interval (6.154ns- 2.154ns), there are 13 (integer) samples of the second pulse. Again, when the fractional part of an OSR is 0.5, there are an integer number of samples per every two consecutive UIs.

[0087] With regard to the third pulse (“pulse 1”), represented as a smaller dashed line, there are 6.5 samples between 4ns to 6ns (the third UI), with the seventh sample (with a sample value of 4) beginning before the 6ns (e.g., at ~5.846ns) and ending after the 6ns (e.g., at ~6.154ns). However, the 13 ^th sample of the third pulse (with a sample value of 29) ends at 8ns (not shown, but the boundary between the third and fourth UIs). Again, this is because with an OSR of 6.5, there are 13 (integer) samples for every two consecutive UIs. And, as mentioned, when the fractional part of an OSR is 0.5, there are an integer number of samples per every two consecutive UIs.

[0088] FIG. 10B illustrates a table depicting sets of sample coefficients of the first, second, and third pulses of FIG. 10A and the transmit digital signal DTX at various taps in accordance with another aspect of the disclosure. The left column represents the pulses and the transmit digital signal DTX (e.g., pulse 1 in row 1, pulse 2 in row 2, pulse 3 in row 3, and DTX in row 4). The remaining columns, from left-to-right, represents the different sample coefficients of the pulses and the transmit digital signal DTX corresponding to taps zero (0) to 17, respectively.

[0089] For taps 0 to 6, there are no pulses overlapping with the first pulse; and thus, the sample coefficients for the first pulse, as well as the transmit digital signal DTX, for taps 0-6, are -1, -3, -4, -5, -5, -2, and 4, respectively. At tap 7, the first pulse begins to overlap with the second pulse. The sample coefficient of the first pulse at tap 7 is 10, and the sample coefficient of the second pulse at tap 7 is -2. Thus, the transmit digital signal DTX at tap 7 has a sample coefficient of 8 (e.g., 10-2=8). Similarly, for taps 8 to 12, only the first and second pulses overlap; and thus, the sample coefficients for the first and second pulses, and the transmit digital signal DTX for taps 8 to 12 are [18, -3.5, 14.5], [25, -4.5, 20.5], [29, -5, 24], [31, -3.5, 27.5], and [29, 1, 30], respectively. At tap 13, the first and second pulses begin to overlap with the third pulse. Accordingly, the sample coefficients for the first, second, and third pulses, and the transmit digital signal DTX for taps 13 to 17 are [25, 7, -1, 31], [18, 14, -3, 29], [10, 21.5, -4, 27.5], [4, 27, -5, 26], and [-2, 30, -5, 23], respectively.

[0090] As explained in more detail further herein, when the OSR is an integer, each positive pulse may have the same set of sample coefficients. For example, with reference to the example OSR=8 depicted in the table of FIG. 5B, the first positive pulse (“pulse 1”) has a set of sample coefficients of [-3, -4, -5, -4, -3, 0, 5, 10, 16, 22, 27, 30, 31, 30, 27, 22, 16, 10, 5, 0, -3, -4, -5, -4, -3]. The second positive pulse (“pulse 2”) has the same set of sample coefficients [-3, -4, -5, -4, -3, 0, 5, 10, 16, 22, 27, 30, 31, 30, 27, 22, 16, 10, 5, 0, -3, -4, -5, -4, -3]. Similarly, with an integer OSR, negative pulses also have the same set of sample coefficients, which is the same as the positive pulse sequence but with the opposite sign, e.g., [3, 4, 5, 4, 3, 0, -5, -10, -16, -22, -27, -30, -31, -30, -27, -22, -16, -10, -5, 0, 3, 4, 5, 4, 3],

[0091] However, when the OSR is fractional, the set of sample coefficients of one pulse is based on (e.g., by interpolation) of the set of sample coefficients of an adjacent pulse. For example, with reference again to FIG. 10B, the first sample coefficient (e.g., -2) of the second pulse is a half-weighted interpolation of the first and second sample coefficients (-1 and -3) of the first pulse. Similarly, the second sample value (e.g., -3.5) of the second pulse is a half- weighted interpolation of the second and third sample coefficients (-3 and -4) of the first pulse. Accordingly, it follows that the 3 ^rd to the 11 ^th sample coefficients of the second pulse (-4.5, -5, -3.5, 1, 7, 14, 21.5, 27, and 30) are the half-weighted interpolations of the 2 ^nd and 3 ^rd to the 10 ^th and 11 ^th sample coefficients of the first pulse ([-4,-5], [-5,-5], [-5,-2], [-2, 4], [4, 10], [10, 18], [18, 25], [25, 29], and [29, 31]), respectively. The reason for the interpolation is that the first sample of the second pulse should start at tap 6.5 because of the fractional C)SR=6.5. But because it starts at tap 7, the sample coefficient is corrected to account for the time discrepancy between tap 6.5 and tap 7.

[0092] FIG. 11A illustrates a table depicting digital sample coefficients of a pair of consecutive transmit digital pulses associated with a fractional oversampling ratio (OSR) of X.5 (where X is an integer) in accordance with another aspect of the disclosure. Although an OSR of 5.5 is used herein as an example, the algorithm discussed with reference to FIG. 11A is applicable to all 0.5 fractional OSRs.

[0093] In a 0.5 OSR, there are two distinct sets of sample coefficients associated with two adjacent or consecutive pulses, respectively. For example, a first positive pulse (“pulse 1”) has a set of sample coefficients of ao to ais- Note that the length or the number of sample coefficients of the set for the first pulse may be set to “j” (e.g., j= 19). A second positive pulse (“pulse 2”) has a set of sample coefficients of bo to bis. Note that the length or the number of sample coefficients of the set for the second pulse may be set to “j” (e.g., j= 19). The sequence for the second pulse is skewed by X+l taps (e.g., it starts at tap 6). Further, the sample coefficients of the set for the second pulse are each a 0.5 weighted interpolation of the sample coefficients of the first pulse (e.g., bo=l/2*(ao+ai), bi=l/2*(ai+a2), b^lGAai+ad, and so on). Generally, the i ^th sample coefficient of the second pulse may be given by the following: bi=l/2*(ai+ai ₊ i). To assist the interpolation, it is assumed ai9=0. and bi8=l/2*(ai8+ai9).

[0094] As previously discussed, the set of sample coefficients of a negative pulse is the negative sign of the set of sample coefficients of a positive pulse. In other words, the set of sample coefficients of a negative pulse corresponding to the first pulse (“pulse 1”) would be -ao to -aj. Similarly, the set of sample coefficients of a negative pulse corresponding to the second pulse (“pulse 2”) would be -bo to -bj. If the transmit digital signal DTX is a ternary signal, then a no pulse would have a set of sample coefficients being all zeros. Thus, a no pulse corresponding to the first pulse would have a set of sample coefficients of {ao to aj}=0, whereas a no pulse corresponding to the second pulse would have a set of sample coefficients of {bo to bj }=0. Further, as previously discussed, the transmit digital signal DTX would include a sum of the sets of sample coefficients Zo to Zj of overlapping pulses.

Thus, for a 0.5 fractional OSR, the following relationships may be applicable: a positive first pulse = { ao to aj } for taps 0 to j, respectively a positive second pulse = {bo to bj } for taps X+l to X+j, respectively, wherein bi=l/2*(a;+ai ₊ i), assume aj+i=O for interpolation a negative first pulse = - {ao to aj} for taps 0 to j, respectively a negative second pulse = {bo to bj} for taps X+l to X+j, respectively, wherein b,= l/2*(a;+ai ₊ i), assume aj ₊ i=O for interpolation a no first pulse = {ao to aj } =0 for taps 0 to j, respectively a no second pulse = {bo to bj } =0 for taps X+l to X+j, respectively

[0095] FIG. 11B illustrates a table depicting digital sample coefficients of a pair of consecutive transmit digital pulses associated with a fractional oversampling ratio (OSR) of X.25 (where X is an integer) in accordance with another aspect of the disclosure. Although an OSR 4.25 is used herein as an example, the algorithm discussed with reference to FIG. 11B is applicable to all 0.25 fractional OSRs.

[0096] In a 0.25 OSR, there are four distinct sets of sample coefficients associated with four adjacent or consecutive pulses, respectively. For example, a first positive pulse (“pulse 1”) has a set of sample coefficients of ao to ai4. Note that the length or the number of sample values of the sequence for the first pulse may be set to “j” (e.g., j = 15) .

[0097] A second positive pulse (“pulse 2”) has a set of sample coefficients of bo to bn. Note that the length or the number of sample coefficients of the set for the second pulse may be “j” (e.g., j= 15). The set of sample coefficients for the second pulse is skewed by X+l taps (e.g., it starts at tap 5). Further, the set of sample coefficients for the second pulse is based on (e.g., by a 0.25/0.75 weighted interpolation of) the sample coefficients of the first pulse (e.g., bo=l/4*ao+3/4*ai , bi=l/4*ai+3/4*a2, b i= l/4*a2+3/4*a3, and so on). Generally, the i ^th sample value of the sample coefficient of the second pulse may be given by the following: bi=l/4*ai+3/4*ai ₊ i. The theory behind this is that the first coefficient bo of the second train of pulse should start at 4.25 tap while it actually starts at the 5 ^th tap, where more weighting should be put on ai than ao. [0098] A third positive pulse (“pulse 3”) has a set of sample coefficients of co to C13. Note that the length or the number of sample values of the sequence for the third pulse may be set to “j” (e.g., j= 15). The set of sample coefficients of the third pulse is skewed by 2*(X+1) taps with respect to the set of sample coefficients of the first pulse (e.g., it starts at tap 10). Further, the set of sample coefficients of the third pulse is based on (e.g., by a 0.5 weighted interpolation of) the set of sample coefficients of the first pulse (e.g., co=l/2*(ao+ai), Ci=l/2*(ai+a2), C3=l/2*(a2+a3), and so on). Generally, the i ¹¹¹ sample value of the sample coefficient of the third pulse may be given by the following: Ci=l/2*(ai+ai+i).

[0099] A fourth positive pulse (“pulse 4”) has a set of sample coefficients of do to di3. Note that the length or the number of sample values of the sequence for the fourth pulse may be set to “j” (e.g., j= 15). The set of sample coefficients of the fourth pulse is skewed by 3*(X+1) taps relative to the start of the set of sample coefficients of the first pulse (e.g., it starts at tap 15). Further, the set of sample coefficients of the second pulse is based on (e.g., a 0.75/0.25 weighted interpolation of) the set of sample coefficients of the first pulse (e.g., do=3/4*ao+l/4*ai, di=3/4*ai+l/4*a2, d3=3/4*a2+l/4*a3, and so on). Generally, the i ^th sample coefficient of the fourth pulse may be given by the following: di=3/4*ai+l/4*ai ₊ i.

[0100] As previously discussed, the set of sample coefficients of a negative pulse is the negative sign of a positive pulse. In other words, a negative pulse corresponding to the first pulse (“pulse 1”) would be -ao to -aj. A negative pulse corresponding to the second pulse (“pulse 2”) would be -bo to -bj. A negative pulse corresponding to the third pulse (“pulse 3”) would be -co to -Cj. A negative pulse corresponding to the fourth pulse (“pulse 2”) would be -do to -dj.

[0101] If the transmit digital signal DTX is a ternary signal, then a no pulse would have a set of sample coefficients being all zeros. Thus, a no pulse corresponding to the first pulse would be [ao to a, |=0; a no pulse corresponding to the second pulse would be [bo to bj |=0; a no pulse corresponding to the third pulse would be [co to c, |=0; and a no pulse corresponding to the fourth pulse would be [do to clj |=0. Further, as previously discussed, the transmit digital signal DTX would include a sum of the sets of sample coefficients Zo to Zj of overlapping pulses. Thus, for a 0.25 fractional OSR, the following relationship may be applicable: a positive first pulse = { ao to aj } for taps 0 to j, respectively a positive second pulse = {bo to bj } for taps X+l to tap X+j, respectively, wherein bi=l/4ai+3/4*ai+i a positive third pulse = {co to Cj } for taps 2*(X+1) to 2*(X+1) + j-1, respectively, wherein c _l = l/2 ^::: ('a _l +a _l+ i) a positive fourth pulse = {do to dj } for taps 3* (X+l) to 3* (X+l) + j-1, respectively, wherein di=3/4ai+l/4*ai _+i a negative first pulse = -{ao to aj } for taps 0 to j, respectively a negative second pulse = - {bo to bj} for taps X+l to tap X+j, respectively, wherein bi=l/4ai+3/4*ai _+i a negative third pulse = -{co to Cj } for taps 2*(X+1) to 2*(X+1) + j-1, respectively, wherein c _l = l/2 ^::: ('a _l +a _l+ i) a negative fourth pulse = -{do to dj-i } for taps 3*(X+1) to 3*(X+1) + j-1, respectively, wherein di=3/4ai+l/4*ai+i a no first pulse = {ao to a, } =0 for taps 0 to j, respectively a no second pulse = {bo to bj } =0 for taps X+l to X+j-1, respectively a no third pulse = {co to c, }=0 for taps 2*(X+1) to 2*(X+1) + j-1, respectively a no fourth pulse = {do to dj )=0 for taps 3*(X+1) to 3*(X+1) + j-1, respectively

[0102] It shall be understood that the OSR may have a higher fractional order, such as 1/8, 1/16, or generally, 1/2 ^T , where T is a positive integer. The number of distinct sets of sample coefficients for adjacent pulses would be 2 ^T . The set of sample coefficients for the k ^th positive pulse following the first pulse may be given by the following: ki=(2 ^T -k)/2 ^T *a; + k/2 ^T *ai+i. The set of sample coefficients for the k ¹¹¹ negative pulse following the first pulse may be given by the following: k _l =-|k/2 ^{l :::} a _l + (2 ^T -k)/2 ^T *ai ₊ i]. The set of sample coefficients for the k ^th no pulse following the first pulse may be given by the following: k;=0. The k ^th pulse following the first pulse may be skewed with respect to the first pulse by k*(X+l) taps. And the k ^th pulse following the first pulse may have a length of j.

[0103] FIG. 12 illustrates a block diagram of at least a portion of an example transmitter 1200 in accordance with another aspect of the disclosure. The transmitter 1200 includes a digital pulse shaper 1205, a data serializer (e.g., 16-to-l or 16-1) 1210 including an input register 1212 and a multiplexer 1214, a frequency divider 1215, a counter 1220, a set of integrated DAC-mixer slices 1230-1 to 1230-46, and an output balun 1235. Each of the set of integrated DAC-mixer slices 1230-1 to 1230-46 includes a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs) M1-M6 and a current source 1232.

[0104] The digital pulse shaper 1205 is configured to receive the transmit data (Tx Data) (e.g., a bit stream). The digital pulse shaper 1205 is configured to output in parallel pulse sample coefficients for two consecutive UIs at half the pulse or bit rate 1/(2*UI) (e.g., l/(2*2ns)=l/4ns=250 MHz). The digital pulse shaper 1205 may be driven by a clock with frequency at the pulse rate, which is also equal to the DAC sampling frequency fs divided by the current OSR (fs/OSR); which in this example, the current OSR may be one of 6.5, 7, 7.5 or 8. The DAC sampling signal fs may have been generated by the dual-output PLL 715 or 800 previously discussed.

[0105] Accordingly, the input register 1212 of the 16-1 serializer 1210 is configured to receive the pulse sample coefficients DO to D12, or DO to D13, or DO to D14, or DO to D15 in parallel from the digital pulse shaper 1205. For example, if the current C)SR=6.5. the input register 1212 receives pulse sample coefficients DO to D12, as there are 13 pulse sample coefficients for two consecutive UIs. If the current C)SR=7, the input register 1212 receives pulse sample coefficients DO to D13, as there are 14 pulse sample coefficients for two consecutive UIs. If the current C)SR=7.5. the input register 1212 receives pulse sample coefficients DO to D14, as there are 15 pulse sample coefficients for two consecutive UIs. If the current C)SR=8. the input register 1212 receives pulse sample coefficients DO to D15, as there are 16 pulse sample coefficients for two consecutive UIs. Accordingly, the input register 1212 receives the pulse sample coefficients at a rate of 1/(2*UI), which is controlled by a clock generated by the frequency divider 1215 dividing by two (2) the pulse rate frequency fs/OSR.

[0106] The counter 1220 is driven by the DAC sampling signal fs generated by the dual-output PLL 715 or 800. The counter 1220 is further configured to receive the reset signal for the count limit, which is 2*OSR. As previously discussed, if the current OSR is 6.5, then there are 13 pulse sample coefficients to be outputted by the multiplexer 1214 for each cycle of the counter 1220. If the current OSR is 7, then there are 14 pulse sample coefficients to be outputted by the multiplexer 1214 for each cycle of the counter 1220. If the current OSR is 7.5, then there are 15 pulse sample coefficients to be outputted by the multiplexer 1214 for each cycle of the counter 1220. And, if the current OSR is 8, then there are 16 pulse sample coefficients to be outputted by the multiplexer 1214 for each cycle of the counter 1220. The counter 1220 outputs the index (e.g., 4 bits) of the current pulse sample coefficient to be outputted by the multiplexer 1214. [0107] As mentioned, the multiplexer 1214 is configured to output the current pulse sample coefficient as indicated by the pulse sample index generated by the counter 1220 from the set of pulse sample coefficients stored in the input register 1212. The multiplexer 1214 includes differential outputs D<5:0> and D<5:0> for generating a differential binary code based on the current pulse sample coefficient received from the input register 1212. The differential outputs D<5:0> and D<5:0> control set of integrated DAC-mixer slices 1230- 1 to 1230-46, respectively.

[0108] With reference to the table provided in FIG. 12, D/D, in this example, are six (6) bits. Bit <5> controls 16 integrated DAC-mixer slices; bit<4> controls 16 integrated DAC-mixer slices; bit<3> controls eight (8) integrated DAC-mixer slices; bit<2> controls four (4) integrated DAC-mixer slices; bit<l> controls two (2) integrated DAC-mixer slices; and bit<0> controls one (1) integrated DAC-mixer slices. When the pulse coefficient is positive, weight data is sent on D (e.g., gates of FET Ml) and zero (0) on D (e.g., gates of FET M4). When the pulse coefficient is negative, weight data is sent on D (e.g., gates of FET M4) and zero (0) on D (e.g., gates of FET Ml).

[0109] The LO signal fi , generated by the dual-output PLL 715 or 800 may be a differential signal fLo+/ ,f i.o-. wherein the positive LO signal f LO+ is provided to the corresponding gates of the NMOS FETs M5 of the integrated DAC-mixer slices 1230-1 to 1230-46, respectively; and the negative LO signal fro- is provided to the corresponding gates of the NMOS FETs M6 of the integrated DAC-mixer slices 1230-1 to 1230-46, respectively.

[0110] For each of the integrated DAC-mixer slices 1230-1 to 1230-46: the NMOS FETs Ml and M5, and the current source 1232 are coupled in series between a positive input (+) of the output balun 1235 and a lower voltage rail (e.g., ground); the NMOS FETs M4 and M6, and the current source 1232 are coupled in series between a negative input (-) of the output balun 1235 and the lower voltage rail; the NMOS FET M2 includes a drain coupled to the drain of NMOS FET M4, and a source coupled to a source of NMOS FET ; the NMOS FET M3 includes a drain coupled to a drain of NMOS FET Ml, and a source coupled to a source of NMOS FET M4; and the gates of NMOS FETs M2 and M3 are coupled together. The set of integrated DAC-mixer slices 1230-1 to 1230-46 are configured to generate a differential transmit RF signal at the differential inputs of the output balun 1235. Accordingly, the output balun 1235 is configured to generate a single- ended transmit RF signal RFTX, which may be provided to the PA 730 for amplification and subsequent transmission into free space by a corresponding antenna. [0111] As mentioned above, the transmitter 1200 may be an example implementation to effectuate a 0.5 fractional OSRs. If, for example, 0.25 fractional OSR is required: the digital pulse shaper 1205 may be configured to output in parallel pulse sample coefficients for four (4) UIs; the frequency divider 1215 may have a divider ratio of four (4); the size of the input register 1212 of the serializer 1210 may be set to accommodate pulse sample coefficients of length 4UIs; and the reset input of the counter 1220 may be configured to receive a count limit of 4 times the current OSR.

[0112] In general, the transmitter 1200 may be implemented to effectuate a 1/2 ^T fractional OSR. In such case: the digital pulse shaper 1205 may be configured to output in parallel pulse sample coefficients for 2 ^T UIs; the frequency divider 1215 may have a divider ratio of 2 ^T ; the size of the input register 1212 of the serializer 1210 may be set to accommodate pulse sample coefficients of length 2 ^T UIs; and the reset input of the counter 1220 may be configured to receive a count limit of 2 ^T times the current OSR.

[0113] FIG. 13 illustrates a flow diagram of an example method 1300 of generating a transmit radio frequency (RF) signal in accordance with another aspect of the disclosure. The method 1300 includes phase-frequency locking a feedback signal to a reference signal to generate a digital- to- analog (DAC) sampling signal and a local oscillator (LO) signal (block 1310). Examples of means for phase-frequency locking a feedback signal to a reference signal to generate a digital-to-analog (DAC) sampling signal and a local oscillator (LO) signal include PLL 715 and 800.

[0114] The method 1300 further includes converting a transmit digital signal into a transmit analog signal based on the DAC sampling signal (block 1320). Examples of means for converting a transmit digital signal into a transmit analog signal based on the DAC sampling signal the digital pulse shaper 705 and the DAC 710, and the digital pulse shaper 1205, frequency divider 1215, serializer 1210 including input register 1212 and multiplexer 1214, counter 1220, the set of DAC -mixer slices 1230-1 to 1230-46, and the output balun 1235.

[0115] Additionally, the method 1300 includes frequency upcon verting the transmit analog signal to generate the transmit RF signal (block 1330). Examples of means for frequency upconverting the transmit analog signal to generate the transmit RF signal include the mixer 720, and the set of DAC-mixer slices 1230-1 to 1230-46 including the output balun 1235.

[0116] FIG. 14 illustrates a flow diagram of an example method 1400 of generating a transmit analog signal in accordance with another aspect of the disclosure. The method 1400 includes generating a transmit digital signal including sets of sample coefficients corresponding to a set of consecutive pulses, respectively, wherein the sets of sample coefficients are generated in accordance with a fractional oversampling ratio (OSR) (block 1410). Examples of means for generating a transmit digital signal including sets of sample coefficients corresponding to a set of consecutive pulses, respectively, wherein the sets of sample coefficients are generated in accordance with a fractional oversampling ratio (OSR) include the digital pulse shapers 705 and 1205.

[0117] The method 1400 further includes converting the transmit digital signal into the transmit analog signal (block 1420). Examples of means for converting the transmit digital signal into the transmit analog signal include the DAC 710 and the set of DAC-mixer slices 1230-1 to 1230-46 including the output balun 1235.

[0118] The following provides an overview of aspects of the present disclosure:

[0119] Aspect 1: A transmitter, comprising a phase lock loop (PLL) configured to generate a digital-to-analog (DAC) sampling signal and a local oscillator (LO) signal; a digital-to- analog (DAC) converter configured to convert a transmit digital signal into a transmit analog signal based on the DAC sampling signal; and a mixer configured to frequency upconvert the transmit analog signal based on the LO signal.

[0120] Aspect 2: The transmitter of aspect 1, wherein the PLL is configured to maintain a ratio of a first frequency of the LO signal to a second frequency of the DAC sampling signal substantially constant for a set of different channels.

[0121] Aspect 3: The transmitter of aspect 2, wherein the ratio of the first frequency to the second frequency is substantially two (2).

[0122] Aspect 4: The transmitter of aspect 3, wherein the first frequency of the LO signal is substantially 6500 mega Hertz (MHz) and the second frequency of the DAC sampling signal is 3250 MHz for one of the set of different transmit channels.

[0123] Aspect 5: The transmitter of aspect 3 or 4, wherein the first frequency of the LO signal is substantially 7000 mega Hertz (MHz) and the second frequency of the DAC sampling signal is substantially 3500 MHz for one of the set of different transmit channels.

[0124] Aspect 6: The transmitter of any one of aspects 3-5, wherein the first frequency of the LO signal is substantially 7500 mega Hertz (MHz) and the second frequency of the DAC sampling signal is 3750 MHz for one of the set of different transmit channels.

[0125] Aspect 7: The transmitter of any one of aspects 3-6, wherein the first frequency of the LO signal is substantially 8000 mega Hertz (MHz) and the second frequency of the DAC sampling signal is substantially 4000 MHz for one of the set of different transmit channels.

[0126] Aspect 8: The transmitter of any one of aspects 1-7, wherein the PLL comprises a first frequency divider configured to frequency divide the LO signal by an integer to generate the DAC sampling signal.

[0127] Aspect 9: The transmitter of aspect 8, wherein the PLL further comprises: a phasefrequency detector (PFD) configured to: receive a reference signal and a feedback signal, and generate a control signal based on a phase-frequency difference between the reference signal and the feedback signal; a charge pump configured to generate a first voltage based on the control signal; a low pass filter (LPF) configured to generate a second voltage based on the first voltage; and a voltage controlled oscillator (VCO) configured to generate a VCO signal based on the second voltage, wherein the LO signal is based on the VCO signal.

[0128] Aspect 10: The transmitter of aspect 9, wherein the PLL further comprises a second frequency divider configured to generate the feedback signal based on the VCO signal.

[0129] Aspect 11: The transmitter of aspect 10, wherein the second frequency divider is configured to frequency divide based on a channel signal.

[0130] Aspect 12: The transmitter of aspect 10 or 11, wherein the PLL further comprises a second divider configured to frequency divide the VCO signal to generate the LO signal.

[0131] Aspect 13: The transmitter of any one of aspects 1-12, further comprising a digital pulse shaper configured to generate the transmit digital signal as a set of consecutive pulses, wherein adjacent pulses are spaced apart by a unit interval (UI).

[0132] Aspect 14: The transmitter of aspect 13, wherein the digital pulse shaper is configured to generate the set of consecutive pulses based on an oversampling ratio (OSR) indicating a number of samples per UI.

[0133] Aspect 15: The transmitter of aspect 14, wherein the OSR is a fractional OSR.

[0134] Aspect 16: The transmitter of aspect 15, wherein the fractional OSR has a fraction of 0.5. [0135] Aspect 17: The transmitter of aspect 16, wherein the digital pulse shaper is configured to: generate a first set of sample coefficients for a first pulse of the set of consecutive pulses; and generate a second set of sample coefficients for a second pulse of the set of consecutive pulses, wherein the first pulse is adjacent to the second pulse, and wherein the second set of sample coefficients is based on the first set of sample coefficients.

[0136] Aspect 18: The transmitter of aspect 17, wherein each sample coefficient of the second set is an interpolation of two sample coefficients of the first set. [0137] Aspect 19: The transmitter of any one of aspects 15-18, wherein the fractional OSR has a fraction of 0.25.

[0138] Aspect 20: The transmitter of aspect 19, wherein the digital pulse shaper is configured to: generate a first set of sample coefficients for a first pulse of the set of consecutive pulses; generate a second set of sample coefficients for a second pulse of the set of consecutive pulses, wherein the first pulse is adjacent to the second pulse, and wherein the second set of sample coefficients is based on the first set of sample coefficients; generate a third set of sample coefficients for a third pulse of the set of consecutive pulses, wherein the second pulse is adjacent to the third pulse, and wherein the third set of sample coefficients is based on the first set of sample coefficients; and generate a fourth set of sample coefficients for a fourth pulse of the set of consecutive pulses, wherein the third pulse is adjacent to the fourth pulse, and wherein the fourth set of sample coefficients is based on the first set of sample coefficients.

[0139] Aspect 21: The transmitter of aspect 20, wherein: each sample coefficient of the second set is a first weighted interpolation of two sample coefficients of the first set; each sample coefficient of the third set is a second weighted interpolation of two sample coefficients of the first set, wherein the second weighted interpolation is different than the first weighted interpolation; and each sample coefficient of the fourth set is a third weighted interpolation of two sample coefficients of the first set, wherein the third weighted interpolation is different than the first weighted interpolation.

[0140] Aspect 22: The transmitter of any one of aspects 1-21, wherein the DAC and mixer are integrated.

[0141] Aspect 23: The transmitter of aspect 22, wherein the integrated DAC-mixer comprises a set of parallel DAC-mixer slices configured to generate a transmit radio frequency (RF) signal based on digital information received from a digital pulse shaper and the LO signal.

[0142] Aspect 24: A method of generating a transmit radio frequency (RF) signal, comprising: phase-frequency locking a feedback signal to a reference signal to generate a digital-to- analog (DAC) sampling signal and a local oscillator (LO) signal; converting a transmit digital signal into a transmit analog signal based on the DAC sampling signal; and frequency upconverting the transmit analog signal to generate the transmit RF signal.

[0143] Aspect 25: The method of aspect 24, wherein the transmit digital signal comprises a set of consecutive pulses including samples generated in accordance with a fractional oversampling ratio (OSR). [0144] Aspect 26: An apparatus for generating a transmit analog signal, comprising: a digital pulse shaper configured to generate a transmit digital signal including sets of sample coefficients corresponding to a set of consecutive pulses, respectively, wherein the sets of sample coefficients are generated in accordance with a fractional oversampling ratio (OSR); and a digital-to-analog converter (DAC) configured to generate the transmit analog signal based on the transmit digital signal.

[0145] Aspect 27: The apparatus of aspect 26, wherein the fractional OSR includes a fraction of 1/2 ^T , wherein T is a positive integer, and wherein the sample coefficients of one or more of the sets of sample coefficients are based on another one of the sets of sample coefficients.

[0146] Aspect 28: The apparatus of aspect 27, wherein the sample coefficients of the one or more of the sets of sample coefficients are based on different interpolations of adjacent pairs of sample coefficients of the another one of the sets of sample coefficients, respectively.

[0147] Aspect 29: A method of generating a transmit analog signal, comprising: generating a transmit digital signal including sets of sample coefficients corresponding to a set of consecutive pulses, respectively, wherein the sets of sample coefficients are generated in accordance with a fractional oversampling ratio (OSR); and converting the transmit digital signal into the transmit analog signal.

[0148] Aspect 30: The method of aspect 29, wherein the fractional OSR includes a fraction of 1/2 ^T , wherein T is a positive integer, and wherein the sample coefficients of one or more of the sets of sample coefficients are based on another one of the sets of sample coefficients.

[0149] Aspect 31: An apparatus for generating a transmit radio frequency (RF) signal, comprising: means for phase-frequency locking a feedback signal to a reference signal to generate a digital-to-analog (DAC) sampling signal and a local oscillator (LO) signal; means for converting a transmit digital signal into a transmit analog signal based on the DAC sampling signal; and means for frequency upconverting the transmit analog signal to generate the transmit RF signal.

[0150] Aspect 32: An apparatus for generating a transmit analog signal, comprising: means for generating a transmit digital signal including sets of sample coefficients corresponding to a set of consecutive pulses, respectively, wherein the sets of sample coefficients are generated in accordance with a fractional oversampling ratio (OSR); and means for converting the transmit digital signal into the transmit analog signal. [0151] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.