Title:
TRANSMITTER AND METHOD OF CONTROLLING TRANSMITTER
Document Type and Number:
WIPO Patent Application WO/2018/061899
Kind Code:
A1
Abstract:
[Problem] In a transmitter having a plurality of transmission blocks, the wiring lengths of each transmission block vary, resulting in a deterioration in signal quality.
[Solution] This transmitter is provided with: a digital delay circuit which delays a 1-bit digital RF signal on the basis of another 1-bit digital RF signal; an amplifier which amplifies a signal output by the digital delay circuit; and a band-pass filter which allows signals in a prescribed frequency band, from among signals output by the amplifier, to pass. A signal output by the band-pass filter is input into a corresponding one antenna element from among a plurality of antenna elements, and controls the directionality of a beam formed by the plurality of antenna elements.
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Inventors:
TANIO MASAAKI (JP)
HORI SHINICHI (JP)
YAMASE TOMOYUKI (JP)
HORI SHINICHI (JP)
YAMASE TOMOYUKI (JP)
Application Number:
PCT/JP2017/033818
Publication Date:
April 05, 2018
Filing Date:
September 20, 2017
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H04B7/06; H01Q3/34; H01Q21/06; H04B7/10
Domestic Patent References:
WO2011078029A1 | 2011-06-30 |
Foreign References:
JP2015525494A | 2015-09-03 | |||
JP2001160716A | 2001-06-12 |
Other References:
MASAAKI TANIO ET AL.: "An FPGA-based All-Digital Transmitter with 28-GHz Time-Interleaved Delta-Sigma Modulation, Microwave Symposium(IMS", 2016 IEEE MTT-S INTERNATIONAL, 22 May 2016 (2016-05-22) - 27 May 2016 (2016-05-27), pages 1 - 4, XP032941166, DOI: 10.1109/MWSYM.2016.7540142
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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