TRANSMITTER AND TRANSMITTER/RECEIVER

WIPO Patent Application WO/2007/099719

A1

A clock control circuit (22) in a control circuit (21) provided in a transmitter (25) controls a gate circuit (12) according to an instruction of a microcomputer (32) and stops the output of a clock into a cable (115) for a first predetermined period. A read circuit in the microcomputer (32) accesses an EDID (31) held in an information holding circuit of a receiver (43) through the cable (115) and sets the first predetermined period according to the EDID (31). A resetting circuit (42) provided in the receiver (43) counts the stop state of the clock and resets at least either the receiver (43) or a television (114) when the clock continues the stop for a second predetermined period. By the reset operation, noise is prevented from being displayed on the television (114). As a result, even if signal switching causing a variation of the clock frequency is performed, noise occurring because of mislatch between the clock and the data can be reduced.

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YANAGISAWA RYOGO
TAKAHASHI SATOSHI
TABIRA YOSHIHIRO

PCT/JP2007/050092

September 07, 2007

January 09, 2007

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MATSUSHITA ELECTRIC IND CO LTD (JP)
YANAGISAWA RYOGO
TAKAHASHI SATOSHI
TABIRA YOSHIHIRO

H04L7/00; H04L7/04; H04N7/173; H04N21/436; H04N21/442

JP2002330120A	2002-11-15
JP2005191877A	2005-07-14
JP2006019809A	2006-01-19
JP2003527034A	2003-09-09
JPH08107406A	1996-04-23

MAEDA, Hiroshi et al. (5-7 Hommachi 2-chome, Chuo-k, Osaka-shi Osaka 53, JP)

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