Title:
TUNNELING FIELD EFFECT TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2019/107411
Kind Code:
A1
Abstract:
A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of a second conductive type, the second conductive layer forming, in a first region, a hetero-junction with the first semiconductor layer; a gate insulating layer covering the second semiconductor layer in the first region; a gate electrode layer that covers the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer which in a second region is sandwiched between the first semiconductor layer and the second semiconductor layer, the second region being adjacent to the second electrode layer side with respect to the first region.
Inventors:
KATO KIMIHIKO (JP)
TAKAGI SHINICHI (JP)
TAKENAKA MITSURU (JP)
TABATA HITOSHI (JP)
MATSUI HIROAKI (JP)
TAKAGI SHINICHI (JP)
TAKENAKA MITSURU (JP)
TABATA HITOSHI (JP)
MATSUI HIROAKI (JP)
Application Number:
PCT/JP2018/043787
Publication Date:
June 06, 2019
Filing Date:
November 28, 2018
Export Citation:
Assignee:
JAPAN SCIENCE & TECH AGENCY (JP)
International Classes:
H01L29/66; H01L21/336; H01L29/78
Foreign References:
| JPH0195554A | 1989-04-13 | |||
| JP2013046073A | 2013-03-04 |
Other References:
KATO, K. ET AL.: "Proposal and demonstration of oxide- semiconductor /(Si,SiGe,Ge) bilayer tunneling field effect transistor with type-II energy band alignment", IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2 December 2017 (2017-12-02), pages 377 - 380, XP033305980
KATO KIMIHIKO ET AL.: "Demonstration of n-Zno/p (Si, Ge) bilayer tunneling field effect transistor", THE JAPAN SOCIETY OF APPLIED PHYSICS- THE 65TH JSAP SPRING MEETING, 2018
KATO, K. ET AL.: "TiN/Al2O3/ZnO gate stackengineering for top-gate thin film transistorsby combination of post oxidation and annealing", APPLIED PHYSICS LETTERS, vol. 112, no. 16, 17 April 2018 (2018-04-17), pages 162105, XP012227785
TAKAGI, S. EL ET AL.: "Ultra-low power III-V-based MOSFETs and Tunneling FETs", ECS TRANSACTIONS, vol. 85, no. 8, 13 May 2018 (2018-05-13), pages 27 - 37, XP055615219
TAKAGI, S. ET AL.: "M0S Device Technology using Alternative Channel Materials for Low Power Logic LSI", SOLID-STATE DEVICE RESEARCH CONFERENCE- IEEE, 3 September 2018 (2018-09-03), pages 6 - 11, XP033417716
"Negative Capacitance FET and ReRAM are the way to large capacity in power efficiency", NIKKEI ELECTRONICS, March 2018 (2018-03-01), pages 75 - 81
"Newly Designed Tunneling Field Effect Transistors for Ultra Energy Efficient Computing, Drastic Extension of Battery Life of IoT Devices by Utilizing Quantum Tunneling Effect", SCHOOL OF ENGINEERING, THE UNIVERSITY OF TOKYO, 4 December 2017 (2017-12-04), Retrieved from the Internet
ANONYMOUS: "Designed Tunneling Field Effect Transistors for Ultra Energy Efficient Computing, drastic Extension of Battery Life of IoT Devices by Utilizing Quantum Tunneling Effect", JST, 4 December 2017 (2017-12-04), XP055615223, Retrieved from the Internet
ANONYMOUS: "Developpment of a new structure transistor that enables ultra-low power consumption LSI", NIKKEI, INC., 4 December 2017 (2017-12-04), Retrieved from the Internet
ANONYMOUS: "Development of Ultra-low Power Consumption Transistor", OPTRONICS, 4 December 2017 (2017-12-04), University of Tokyo, Retrieved from the Internet
ANONYMOUS: "To achieve quantum tunnel FET with oxide semiconductor and SI-based material", EE TIMES JAPAN, 5 December 2017 (2017-12-05), Retrieved from the Internet
"To achieve quantum tunnel FET with oxide semiconductor and SI-based material", EETIMES JAPAN, 5 December 2017 (2017-12-05), Retrieved from the Internet
ANONYMOUS: "Development of a new transistor to achieve ultra-low power LSI, significantly extending the battery life", MYNAVI NEWA, 6 December 2017 (2017-12-06), University of Tokyo, Retrieved from the Internet
ANONYMOUS: "Succeeded in the development of a new structure transistor operating with extremely small power consumption", FABCROSS FOR ENGINEER, 5 December 2017 (2017-12-05), Retrieved from the Internet [retrieved on 20190130]
"Succeeded in developing quantum tunneling transistor operating with extremely low power consumption", GLOBAL NET CO. LTD., 11 December 2017 (2017-12-11), Retrieved from the Internet
KATO KIMIHIKO ET AL.: "Demonstration of n-Zno/p (Si, Ge) bilayer tunneling field effect transistor", THE JAPAN SOCIETY OF APPLIED PHYSICS- THE 65TH JSAP SPRING MEETING, 2018
KATO, K. ET AL.: "TiN/Al2O3/ZnO gate stackengineering for top-gate thin film transistorsby combination of post oxidation and annealing", APPLIED PHYSICS LETTERS, vol. 112, no. 16, 17 April 2018 (2018-04-17), pages 162105, XP012227785
TAKAGI, S. EL ET AL.: "Ultra-low power III-V-based MOSFETs and Tunneling FETs", ECS TRANSACTIONS, vol. 85, no. 8, 13 May 2018 (2018-05-13), pages 27 - 37, XP055615219
TAKAGI, S. ET AL.: "M0S Device Technology using Alternative Channel Materials for Low Power Logic LSI", SOLID-STATE DEVICE RESEARCH CONFERENCE- IEEE, 3 September 2018 (2018-09-03), pages 6 - 11, XP033417716
"Negative Capacitance FET and ReRAM are the way to large capacity in power efficiency", NIKKEI ELECTRONICS, March 2018 (2018-03-01), pages 75 - 81
"Newly Designed Tunneling Field Effect Transistors for Ultra Energy Efficient Computing, Drastic Extension of Battery Life of IoT Devices by Utilizing Quantum Tunneling Effect", SCHOOL OF ENGINEERING, THE UNIVERSITY OF TOKYO, 4 December 2017 (2017-12-04), Retrieved from the Internet
ANONYMOUS: "Designed Tunneling Field Effect Transistors for Ultra Energy Efficient Computing, drastic Extension of Battery Life of IoT Devices by Utilizing Quantum Tunneling Effect", JST, 4 December 2017 (2017-12-04), XP055615223, Retrieved from the Internet
ANONYMOUS: "Developpment of a new structure transistor that enables ultra-low power consumption LSI", NIKKEI, INC., 4 December 2017 (2017-12-04), Retrieved from the Internet
ANONYMOUS: "Development of Ultra-low Power Consumption Transistor", OPTRONICS, 4 December 2017 (2017-12-04), University of Tokyo, Retrieved from the Internet
ANONYMOUS: "To achieve quantum tunnel FET with oxide semiconductor and SI-based material", EE TIMES JAPAN, 5 December 2017 (2017-12-05), Retrieved from the Internet
"To achieve quantum tunnel FET with oxide semiconductor and SI-based material", EETIMES JAPAN, 5 December 2017 (2017-12-05), Retrieved from the Internet
ANONYMOUS: "Development of a new transistor to achieve ultra-low power LSI, significantly extending the battery life", MYNAVI NEWA, 6 December 2017 (2017-12-06), University of Tokyo, Retrieved from the Internet
ANONYMOUS: "Succeeded in the development of a new structure transistor operating with extremely small power consumption", FABCROSS FOR ENGINEER, 5 December 2017 (2017-12-05), Retrieved from the Internet
"Succeeded in developing quantum tunneling transistor operating with extremely low power consumption", GLOBAL NET CO. LTD., 11 December 2017 (2017-12-11), Retrieved from the Internet
Attorney, Agent or Firm:
TAKAHASHI, HAYASHI AND PARTNER PATENT ATTORNEYS, INC. (JP)
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