BACKGROUND

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), and gallium arsenide (GaAS). A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device, and in instances where the charge carriers are holes, the FET is referred to as a p-channel device. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal -oxide-semiconductor FETs (MOSFETs) include a gate dielectric layer between the gate and the channel. MOSFETs may also be known, more generally, as metal-insulator-semiconductor FETs (MISFETs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFET (p-MOS) and n-channel MOSFET (n-MOS) to implement logic gates and other digital circuits.

A FinFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). A nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a method of forming an integrated circuit (IC) including at least one tunneling transistor including source/drain (S/D) regions employing a contact resistance reducing layer, in accordance with some embodiments of the present disclosure.

Figures 2A-H illustrate example integrated circuit structures that are formed when carrying out method of Figure 1, in accordance with various embodiments.

Figure 2D' illustrates the example structure of Figure 2D, including vertical isolation structures, in accordance with an embodiment.

Figure 2Ff illustrates the example structure of Figure 2H, including the vertical isolation structures of Figure 2D', in accordance with an embodiment.

Figure 3 illustrates an example cross-sectional view taken along one fin of the IC structure of Figure 2H, specifically taken along the A-A plane, in accordance with some embodiments of the present disclosure.

Figure 3' illustrates the IC structure of Figure 3, including shading and patterning to assist with visualizing the material and doping scheme of the S/D regions, in accordance with some embodiments of the present disclosure.

Figures 4 and 5 illustrate example p-type and n-type Fermi filter field-effect transistor (FFFET) energy band diagrams, respectively, for FFFET devices including S/D regions employing different semiconductor material, in accordance with some embodiments.

Figure 6 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Further still, some of the features in the drawings may include a patterned and/or shaded fill, which is primarily provided to assist in visually differentiating the different features, In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Different transistor types employ different source/drain (S/D) doping schemes, as is known in the semiconductor technology field. For example, metal-oxide-semiconductor field-effect transistors (MOSFETs) may employ source-channel-drain region doping schemes of p-n-p or n- p-n, where 'p' represents suitable p-type doping for a given semiconductor material and 'n' represents suitable n-type doping for a given semiconductor material. Thus, such MOSFETs employ similar-type doping in both of the S/D regions of one such device. However, other transistor types employ doping schemes that include a source region with dissimilar-type doping relative to the drain region of that transistor. For instance, tunnel field-effect-transistors (TFETs) generally include a similar structure as MOSFETs (as TFETs also include source, channel, and drain regions), except that TFETs may employ source-channel-drain doping schemes of p-i-n or n-i-p, where i represents intrinsic or nominally undoped semiconductor material (e.g., where nominally undoped includes impurity dopant concentrations of less than 1E16, 1E17, or 1E18 atoms per cubic cm). Thus, such TFETs employ dissimilar-type doping in the S/D regions of one such device. In addition, Fermi filter FETs (FFFETs), which are also referred to as tunnel- source MOSFETs, generally include a similar structure as MOSFETs (as FFFETs also include source, channel, and drain regions), except that FFFETs include a bilayer source region of opposite type doping, such that FFFETs may employ source-channel-drain doping schemes of np-i-p (or np-n-p) or pn-i-n (or pn-p-n). For TFETs, FFFETs, and other transistor types that include source and drain regions employing different dopant types (e.g., in contrast with S/D regions of MOSFETs that generally include only the same dopant types) and/or utilize tunneling mechanisms, it may be desired to alter the S/D material configuration from single semiconductor material designs to improve transistor performance. In addition, contact resistance is an issue at the source-contact and drain-contact locations, whereby such locations can include parasitic external resistance choke points that degrade transistor device performance.

Thus, and in accordance with one or more embodiments of the present disclosure, techniques are provided for forming tunneling transistors including S/D regions employing a contact resistance reducing layer. In some embodiments, the contact resistance reducing layer may be formed between the source region and its corresponding contact and/or the drain region and its corresponding contact, such that the contact resistance reducing layer is an intervening layer between at least one of the S/D regions and its corresponding contact. In some embodiments, the contact resistance reducing layer may include semiconductor material and also include higher dopant levels relative to its corresponding S/D region (e.g., relative to the dopant concentration of the underlying or otherwise proximate S/D semiconductor material). In some embodiments, the contact resistance reducing layer may include a doping concentration (e.g., of any suitable n-type or p-type dopant) that is at least 1E17 to 1E21 atoms per cubic cm (e.g., at least 1E20 atoms per cubic cm) greater than the dopant concentration of the underlying S/D region for which it is providing contact resistance reduction, or some other suitable relative amount as will be apparent in light of this disclosure.

As can be understood based on this disclosure, TFETs and FFFETs are two types of tunneling transistor devices that have steeper current turn-on (e.g., versus gate voltage) than p-n- p and n-p-n MOSFET devices, due to the fundamental switching mechanisms being relatively different. For example, such MOSFET devices generally switch by modulating thermionic emission over a barrier, whereas TFET and FFFET devices switch by modulating quantum tunneling through a barrier. Therefore, in some embodiments, via material bandgap engineering, the techniques described herein enhance the ability of such relatively steeper on-current devices (e.g., TFETs and FFFETs) to resist off-state leakage currents from source to drain (through the channel) and from source to ground/substrate. The material bandgap engineering may incorporate a material-based band offset component to control off-state leakage. Such a band offset can expand upon the limited band offset achievable using single-composition material configurations, because with such single-composition material configurations, above a threshold doping concentration, there is no additional decrease in leakage current for a given source to drain voltage at fixed dimensions. For instance, in the case of a silicon (Si) material configuration (e.g., where both S/D regions include only Si and suitable dopant), by substituting silicon germanium (SiGe) or germanium (Ge) for the Si material in one of the S/D regions, the energy of the conduction band can be decreased, thereby increasing the barrier height that charge carriers (e.g., electrons) must overcome to cross over to the channel region (e.g., in TFET and FFFET devices).

As will be apparent in light of this disclosure, the techniques can be implemented for S/D regions including group IV semiconductor material, group III-V semiconductor material, and/or any other suitable semiconductor material. The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as Si, Ge, SiGe, and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium antimonide (GaSb), and indium phosphide (InP), and so forth. In some embodiments, the S/D regions may employ different material to achieve desired bandgap engineering. In some such embodiments, the bandgap material engineering may be performed for only the source side of the devices. Regardless, in some embodiments, the S/D regions may include dissimilar material relative to each other, where the source region would include material that is different than material from material included in the drain region. Note that the differences in material described herein for the S/D regions of a transistor are with reference to the bulk semiconductor material included in the S/D regions and not with respect to the impurity dopant(s) added to the bulk semiconductor material. For instance, a TFET device including a p-i-n or n-i-p doping scheme includes different impurity dopant types between the source and drain regions (e.g., one is n-type doped and the other is p- type doped); however, the bulk semiconductor material of the S/D regions in such a TFET device is the same. For instance, TFET devices can be formed using a bulk semiconductor material of Si in both of the S/D regions, where one of the S/D regions is doped with a suitable n-type dopant (e.g., phosphorus) and the other S/D region is doped with a suitable p-type dopant (e.g., boron).

To assist with illustrating the benefits of the techniques described herein, in an example FFFET device, the source to drain material and doping scheme may include n-type doped Si then p-type doped SiGe in the source region, intrinsic Si in the channel region, and p-type doped Si in the drain region, in accordance with an embodiment employing a p-type FFFET device. In such an example embodiment, it can be understood based on this disclosure that by employing p-type doped SiGe in such a heteroj unction source stack as opposed to p-type doped Si (in what would be a homojunction source stack), the valence band edge (Ev) for that p-type doped source layer is relatively higher, thereby increasing the band offset to help reduce off-state leakage. In another example FFFET device, specifically for an embodiment employing an n-type FFFET device, the source to drain material and doping scheme may include p-type doped GaAs then n- type doped InGaAs in the source region, intrinsic GaAs in the channel region, and n-type doped GaAs in the drain region, for instance. In such an example embodiment, it can be understood based on this disclosure that by employing n-type doped InGaAs in such a heteroj unction source stack as opposed to n-type doped GaAs (in what would be a homojunction source stack), the conduction band edge (Ec) for that n-type doped source layer is relatively lower, thereby increasing the band offset to help reduce the off-state leakage. Numerous material and doping scheme configurations will be apparent in light of this disclosure. Thus, in some embodiments, a contact resistance reducing layer (also referred to as a cap layer and intervening layer herein) may be used to benefit tunneling transistor devices that include S/D regions employing different/dissimilar semiconductor material. However, in some embodiments, the tunneling transistors formed using the techniques described herein need not include dissimilar semiconductor material between the S/D regions (i.e., the S/D regions include similar or the same semiconductor material). For instance, in the case of a TFET device, the contact resistance reducing layer may be used to benefit at least one of the S/D regions, where both S/D regions include the same semiconductor material but are doped in an opposite manner (e.g., one of the S/D regions is n-type doped and the other is p-type doped), in accordance with some embodiments. Further, in the case of an FFFET devices, the contact resistance reducing layer may be used to benefit at least one of the S/D regions, where both S/D regions include the same semiconductor material but the doping scheme includes one of pn-i-n (or pn-p-n) or np-i-p (or np-n-p) due to the bilayer structure of the source region in those devices, in accordance with some embodiments. In such embodiments, it can be understood based on this disclosure that the source region would include a homojunction configuration as opposed to a heteroj unction configuration. Therefore, S/D contact resistance reducing layers as described herein can benefit a multitude of transistor devices, as will be apparent in light of this disclosure.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction ( BD or BED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SFMS); time-of-flight SFMS (ToF-SFMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate an integrated circuit (IC) including a tunneling transistor including at least one S/D region employing a contact resistance reducing layer as variously described herein. For instance, in some such embodiments, the contact resistance reducing layer may include semiconductor material having a higher dopant concentration relative to its underlying S/D region semiconductor material. Further, in some embodiments, the S/D regions may employ different semiconductor material. For instance, in the case of a TFET device, the p/n-type doped source region may include a first semiconductor material (e.g., Si or GaAs) and the n/p-type doped drain region may include a second semiconductor material different than the first (e.g., SiGe or InGaAs). Further, in some embodiments, the source region may include a bilayer structure including a first layer and a second layer, where one of the layers is p-type doped and the other is n-type doped. In some such embodiments, the first and second layers may include different semiconductor material. In any such embodiments, material engineering as described herein, including using dissimilar semiconductor material between the source and drain regions, can make use of the different bandgaps and band offsets achievable to decrease leakage current for the off-state of transistor devices that utilize quantum tunneling and/or band- to-band tunneling (BTBT), such as TFETs and FFFETs, for example. Therefore, the techniques can be detected through cross-sections and material/chemical analysis. In some embodiments, the techniques and structures described herein may be detected based on the benefits derived therefrom, such as the ohmic contact resistance reduction that can be achieved at the S/D-contact locations and/or the relatively reduced off-state leakage that can be achieved using relatively different semiconductor material in the S/D regions. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

Figure 1 illustrates a method 100 of forming an integrated circuit (IC) including at least one tunneling transistor including source/drain (S/D) regions employing a contact resistance reducing layer, in accordance with some embodiments of the present disclosure. In some embodiments, method 100 may also be used to form the tunneling transistor device to include S/D regions employing relatively different semiconductor material, such that the source region includes a first semiconductor material and the drain region includes a second semiconductor material different than the first semiconductor material, for example. The inclusion of different material in the S/D regions of a single transistor provides benefits as can be understood based on this disclosure, such as reducing off-state leakage in the form of source to drain leakage through the channel and source to ground/substrate leakage; however, the present disclosure is not intended to be so limited. Figures 2A-I illustrate example integrated circuit structures that are formed when carrying out method 100 of Figure 1, in accordance with some embodiments of the present disclosure. Method 100 of Figure 1 includes a primary vertical flow that illustrates a gate last transistor fabrication process flow, in accordance with some embodiments. However, in other embodiments, a gate first process flow may be used, as will be described herein (and which is illustrated with the alternative gate first flow 100' indicator in Figure 1). The structures of Figures 2A-H are primarily depicted and described herein in the context of forming Fermi filter field-effect transistors (FFFETs) having finned configurations (e.g., FinFET or tri-gate), for ease of illustration and description. However, the techniques can be used to form transistors of any suitable type and any suitable geometry or configuration, as can be understood based on this disclosure. For example, Figure 2G illustrates an example integrated circuit structure including transistors having nanowire configurations, as will be described in more detail below. In addition, variations to the techniques used to form tunnel FET (TFET) devices are described herein and primarily relate to the S/D processing (box 114 of method 100).

Thus, the techniques described herein can benefit various different transistor types, such as a multitude of field-effect transistors (FETs) (e.g., TFETs, FFFETs), and any other transistor that operates by modulating quantum tunneling through a barrier, for example. Other suitable transistor types may benefit of the techniques described herein, where different material is formed in the source and drain regions. Further, various example transistor configurations that can benefit from the techniques described herein include, but are not limited to, planar, finned (e.g., FinFET, tri-gate, double-gate), and nanowire (or nanoribbon or gate-all-around). Further still, the techniques can be used to benefit p-type devices (e.g., p-type FFFET and p-type TFET) and/or n-type devices (e.g., n-type FFFET and n-type TFET). Further yet, the techniques may be used to form complementary MOS (CMOS) devices/circuits, where either or both of the included p-type and n-type transistors are formed using the techniques described herein, such that either or both of the included p-type and n-type transistors include S/D regions having dissimilar material. Other example transistor devices can include few to single electron quantum transistor devices and devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example. In some embodiments, the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).

Method 100 of Figure 1 includes patterning 102 hardmask 210 on a substrate 200 to form the example resulting structure shown in Figure 2A, in accordance with an embodiment. Hardmask 210 may be formed or deposited on substrate 200 using any suitable technique, as will be apparent in light of this disclosure. For example, hardmask 210 may be blanket deposited or otherwise grown on substrate 200 using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin-on processing, and/or any other suitable process to form hardmask 210 on substrate 200. In some instances, the top surface of substrate 200 on which hardmask 210 is to be deposited may be treated (e.g., chemical treatment, thermal treatment, etc.) prior to deposition of the hardmask 210 material. Hardmask 210 can be patterned 102 using any suitable techniques, such as one or more lithography and etch processes, for example. Hardmask 210 may include of any suitable material, such as various oxide or nitride materials, for example. Specific oxide and nitride materials may include silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, or titanium nitride, just to name a few. In some cases, the hardmask 210 material may be selected based on the material of substrate 200, for example.

Substrate 200, in some embodiments, may include: a bulk substrate including group IV semiconductor material, such as silicon (Si), germanium (Ge), or silicon germanium (SiGe), and/or at least one group III-V semiconductor material and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned materials (e.g., group IV and/or group III-V material). Recall that the use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as Si, Ge, SiGe, and so forth. Also recall that the use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium antimonide (GaSb), and indium phosphide (InP), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example.

In some embodiments, substrate 200 substrate 110 may include a surface crystalline orientation described by a Miller Index plane of {001 }, {011 }, or { 111 }, as will be apparent in light of this disclosure. Although substrate 200, in this example embodiment, is shown as having a thickness (dimension in the Z-axis direction) similar to other layers for ease of illustration, in some instances, substrate 200 may be much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example, or any other suitable thickness as will be apparent in light of this disclosure. In some embodiments, substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.

Method 100 of Figure 1 continues with performing 104 shallow trench recess (STR) etch to form fins 202 from substrate 200, thereby forming the resulting example structure shown in Figure 2B, in accordance with an embodiment. The STR etch 104 used to form trenches 215 and fins 202 may include any suitable techniques, such as various masking processes and wet and/or dry etching processes, for example. In some cases, STR etch 104 may be performed in- situ/without air break, while in other cases, STR etch 104 may be performed ex-situ, for example. Trenches 215 may be formed with varying widths (dimension in the X-axis direction) and depths (dimension in the Z-axis direction) as can be understood based on this disclosure. For example, multiple hardmask patterning 102 and STR etching 104 processes may be performed to achieve varying depths in the trenches 215 between fins 202. Fins 202 may be formed to have varying widths Fw (dimension in the X-axis direction) and heights Fh (dimension in the Z-axis direction). For example, in an aspect ratio trapping (ART) integration scheme, the fins may be formed to have particular height to width ratios such that when they are later removed or recessed, the resulting trenches formed allow for defects in the replacement material deposited to terminate on a side surface as the material grows vertically, such as non- crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects, if such an ART scheme is used.

In some embodiments, the fin widths Fw may be in the range of 5-400 nm, for example, or any other suitable value, as will be apparent in light of this disclosure. In some embodiments, the fin heights Fh may be in the range of 10-800 nm, for example, or any other suitable value, as will be apparent in light of this disclosure. In embodiments employing an aspect ratio trapping (ART) scheme, the fins may be formed to have particular height to width ratios such that when they are later recessed and/or removed, the resulting fin trenches formed allow for defects in the replacement material deposited to terminate on a side surface as the material grows vertically, such as non-crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects. In such an example case, the height to width ratio of the fins (Fh:Fw) may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or any other suitable threshold ratio, as will be apparent in light of this disclosure. Note that the trenches 215 and fins 202 are each shown as having the same widths and depths/heights in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited. For example, in some embodiments, the fins 202 may be formed to have varying heights Fh and/or varying widths Fw. Further note that although four fins 202 are shown in the example structure of Figure 2B, any number of fins may be formed, such as one, two, ten, hundreds, thousands, millions, and so forth, as can be understood based on this disclosure.

Method 100 of Figure 1 continues with depositing 106 shallow trench isolation (STI) layer 220 and planarizing to form the resulting example structure shown in Figure 2C, in accordance with an embodiment. In some embodiments, deposition 106 of STI layer 220 may include any deposition process described herein (e.g., CVD, ALD, PVD), or any other suitable deposition process. The material of STI layer 220 may include any suitable insulating material, such as one or more dielectric, oxide (e.g., silicon dioxide), or nitride (e.g., silicon nitride) materials. In some embodiments, the material of STI layer 220 may selected based on the material of substrate 200. For instance, in the case of a Si substrate, STI material may be silicon dioxide or silicon nitride, to provide an example.

Method 100 of Figure 1 continues with recessing 108 the STI material 220 to cause at least a portion 204 of fins 202 to exude from the STI plane, thereby forming the resulting example structure shown in Figure 2D, in accordance with an embodiment. As shown in Figure 2D, the portion 204 of fin 202 exuding above the top plane of STI layer 220 (indicated as 204) has an active fin height indicated as Fah, which may be in the range of 10-750 nm, for example, or any other suitable value, as will be apparent in light of this disclosure. As is also shown, the portion 203 of fin 202 that is below the top plane of STI layer 220 is the sub-fin portion (indicated as 203). Note that in this example embodiment, fins 202 (including portions 203 and 204) are native to substrate 200. In other words, fins 202 were formed from substrate 200 in this example embodiment and include the same material in the structure of Figure 2D, such that fins 202 (including portions 203 and 204) and substrate 200 are one homogenous structure. However, in other embodiments, some or all of fins 202 may be removed and replaced with replacement fins, for example. In some such embodiments, the processing may continue from the structure of Figure 2C and include etching the fins 202 (e.g., using any suitable wet and/or dry etch processes) to form fin trenches between STI layer 220, where the etching either completely or partially removes fins 202 (e.g., either goes all the way to/past the bottom plane of STI layer 220 or does not, respectively). In such an embodiment, the fin trenches can be used for the deposition of a replacement material, and continuing with recess process 108 would result in the fins of Figure 2D being replacement fins (which may include different material than what is included in substrate 200). In some such embodiments, the replacement material may include group IV semiconductor material and/or group III-V semiconductor material, and/or any other suitable material as will be apparent in light of this disclosure. For instance, replacement fins including SiGe may be formed by removing native Si fins during such processing and replacing them with the SiGe material, to provide an example. Note that in some such embodiments where the fins are removed and replaced (and thus, are not native fins), an ART processing scheme may be employed, where the fin trenches have a high aspect ratio (e.g., heigh width ratio of greater than 1, 1.5, 2, 3, 4, 5, or a higher value). Such an ART processing scheme may be employed, for example to trap dislocations, thereby preventing the dislocations from reaching the epitaxial film surface and greatly reducing the surface dislocation density within the trenches.

Regardless of whether active fin portions 204 are native to substrate 200 or not, method 100 of Figure 1 may optionally continue with forming 110 vertical isolation structures 230 as shown in Figure 2D', in accordance with an embodiment. As can be understood based on this disclosure, Figure 2D' illustrates the example structure of Figure 2D, including vertical isolation structures 230. Therefore, the previous relevant description with respect to the example structure of Figure 2D is equally applicable to the example structure of Figure 2D'. In some embodiments, vertical isolation structures 230 may be formed to, for example, further isolate (or electrically insulate) single fins or groups of fins. For instance, in the example structure of Figure 2D', such vertical isolation structures are present and may be included to prevent the eventual S/D regions of one transistor device from shorting the S/D of another (e.g., adjacent) transistor device by ensuring the respective S/D regions stay separate. Accordingly, such vertical isolation structures 230 may be formed using any suitable techniques and, when present the structures 230 may include any suitable electrical insulator material, such as a dielectric, oxide, nitride, and/or carbide material, for instance. Note that although the vertical isolation structures 230 are higher (dimension in the Z-axis direction) than fins 204, the present disclosure is not intended to be so limited. Also, because vertical isolation structure 230 need not be present in some disclosure, as they are optional, method 100 will continue to be described using IC structures without the vertical isolation structures 230, for ease of description.

Recall that method 100 is primarily described herein in the context of a gate last transistor fabrication process flow, where the processing includes forming a dummy gate stack, performing the S/D processing, and then forming the final gate stack after the S/D regions have been processed. However, in other embodiments, the techniques may be performed using a gate first process flow. In such an example case, process 112 - forming a dummy gate stack - would not be performed, and thus, process 112 is optional in some embodiments (such as those employing the gate first process flow). This is reflected on the right side of the process flow of Figure 1, where performing 116 the final gate stack processing 116 may be performed prior to performing 114 the S/D processing, for example. However, the description of method 100 will continue using a gate last process flow, to allow for such a flow (which may include additional processes) to be adequately described.

Method 100 of Figure 1 continues with forming 112 a dummy gate stack, including dummy gate dielectric 242 and dummy gate electrode 244, thereby forming the example resulting structure of Figure 2E, in accordance with an embodiment. As described above, process 112 is optional, because it need not be performed in all embodiments (such as those employing a gate first process flow). In this example embodiment, dummy gate dielectric 242 (e.g., dummy oxide material) and dummy gate or dummy gate electrode 244 (e.g., dummy poly- silicon material) may be used for a replacement gate process. Note that side-wall spacers 250, referred to generally as gate spacers (or simply, spacers), on either side of the dummy gate stack were also formed, and such spacers 250 can help determine the channel length and can help with replacement gate processes, for example. As can be understood based on this disclosure, the dummy gate stack (and spacers 250) can help define the channel region and source/drain (S/D) regions of each fin, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of the dummy gate stack. Note that because the IC structures are being described in the context of forming finned transistors, the final gate stack will also be adjacent to either side of the fin, as the gate stack will reside along three walls of the finned channel regions, in some embodiments. Formation of the dummy gate stack may include depositing the dummy gate dielectric material 242 and dummy gate electrode material 244, patterning the dummy gate stack, depositing gate spacer material 250, and performing a spacer etch to form the structure shown in Figure 2E, for example. Spacers 250 may include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that in some embodiments, the techniques described herein need not include forming a dummy gate stack, such that a final gate stack may be formed in the first instance. Regardless, the end structure will include the end gate stack, as will be apparent in light of this disclosure. Also note that in some embodiments, a hardmask (not shown) may be formed over the dummy gate stack (which may also be formed over spacers 250) to protect the dummy gate stack during subsequent processing, for example.

Method 100 of Figure 1 continues with performing 114 source/drain (S/D) processing to form the example resulting structure of Figure 2F, in accordance with an embodiment. As shown in Figure 2F, the structure includes source regions 261 that each include a bilayer stack structure including a first layer 262 and a second layer 264. Note that although source region second layer 264 may be formed prior to source region first layer 262, in some embodiments, the layers 264, 262 are referred to as such due to the flow of current through the source region 261 (e.g., the current can flow from the source contact to the first layer 262 of the source region and then to the second layer 264 of the source region). In this example embodiment, second layer 264 is below first layer 262, and thus, first layer 262 is above second layer 264; however, the present disclosure need not be so limited unless otherwise stated. For instance, in some embodiments, source regions 261 may be single layer structures, such as in the case of forming TFET devices, to provide an example. However, continuing with the example embodiment of Figure 2F, in some embodiments, the source region second layer 264 may be between the source region first layer 262 and at least one of the channel region and the substrate 200, as can be understood based on this disclosure. For instance, the presence of second layer 264 may help prevent leakage from the first layer 262 to the channel region and/or substrate 200, in accordance with some such embodiments. As is also shown in Figure 2F, the structure includes drain regions 265 on the opposing side of the gate stack (and thus on the opposing side of the channel region) from each corresponding source region 261. Therefore, when discussing the S/D regions of a transistor herein, for ease of description, it will be assumed that a single transistor will be formed using a single fin structure, such that one source region 261 and its corresponding drain region 265 (e.g., aligned in the Y-axis direction) will be considered the S/D regions for that single transistor. Note that the structure of the S/D regions is also shown in Figure 3, which illustrates an example cross-sectional view taken along one fin of the IC structure of Figure 2H, and specifically taken along the A-A plane, which will be described in more detail below. Thus, the cross-sectional view of Figure 3 may help in illustrating the S/D regions and the transistor structure in general, for instance.

The S/D regions, in some embodiments, may be formed using any suitable techniques, such as masking regions outside of the S/D regions to be processed, etching portions of the fins from the structure of Figure 2E (in this example case, active portions 204 were etched and removed, leaving only sub-fin portions 203, as shown), and forming/depositing/growing the S/D regions (e.g., using any suitable techniques, such as CVD, ALD, PVD), for example. In some embodiments, the source regions 261 may be processed separately from the drain regions 265, as they may include different material and different doping types, as can be understood based on this disclosure. In some such embodiments, one set of the S/D regions (either source regions 261 or drain regions 265) may be masked off while processing occurs in the other set of S/D regions, and then the masking and processing can be switched. However, processing may occur to both sets of the S/D regions 261 and 265 simultaneously, such as forming dopants in source layer 264 and drain 265 simultaneously, as such features may include the same dopant types, in accordance with some embodiments. In some embodiments, the native fin 204 material (i.e., native to substrate 200) may remain in one or both of the S/D regions, where such native material can be doped to form final S/D region material. Thus, the material of the S/D regions may include native and/or replacement material, such that there may or may not be a distinct interface between the sub-fin portions 203 and the S/D regions (e.g., layers 264 and 265). In this example embodiment, as the material of the S/D regions is replacement material, there is a distinct interface between features 264 and 203 and between features 265 and 203, as shown in Figures 2F and 3. Note that even in embodiments where material native to substrate 200 is used in an S/D region, there may still be a distinct interface between the S/D region and the sub-fin 203, because of impurity dopants introduced into the S/D region, for example. Numerous different techniques for processing the S/D regions will be apparent in light of this disclosure.

In some embodiments, the S/D regions may include any suitable material, such as group IV semiconductor material (e.g., Si, SiGe, Ge), group III-V semiconductor material (e.g., GaAs, InGaAs, InAs), and/or any other suitable semiconductor material, and may also include any suitable doping scheme, as will be apparent in light of this disclosure. When impurity dopants are included in semiconductor material of a 1 ay er/regi on/feature, the impurity dopants can convert the semiconductor material to extrinsic semiconductor material (as opposed to intrinsic semiconductor material), as can be understood based on this disclosure. Such doping intentionally introduces the impurities in semiconductor material to, for example, modulate the electrical properties of the semiconductor material. Therefore, such impurity doping may be used to change the electrical properties of included group IV and/or group III-V semiconductor material, for instance. In some embodiments, doping semiconductor material may be achieved using any suitable techniques, such as via diffusion, ion implantation, depositing/growing the dopants with the primary semiconductor material, and/or any other suitable techniques as will be apparent in light of this disclosure. In some embodiments, the dopants may be introduced into native semiconductor material (native to the substrate) and/or replacement semiconductor material (e.g., that is epitaxially formed), for instance. Further, in embodiments where implantation is used, the impurity dopants may be implanted with or without preamorphizing treatments, for example. Any number of doping processes may be performed as desired to introduce suitable n-type and/or p-type dopant into the semiconductor material of the source, drain, and/or channel regions, as will be apparent in light of this disclosure.

However, in some embodiments, semiconductor material included in at least one of the layers/regions/features (e.g., in the channel region) may not be intentionally doped, such that the semiconductor material is intrinsic or nominally undoped. Such nominal doping may occur as a result of undesired diffusion, for example, and thus, the use of "nominally undoped" with reference to semiconductor material or a layer/region/feature including semiconductor material includes having an impurity dopant concentration of less than 1E15, 1E16, 1E17, or 1E18 atoms per cubic centimeter (cm), or less than some other suitable threshold amount, as will be apparent in light of this disclosure. Note that when dopants are present in the semiconductor material of any layer/region feature of a transistor device, the dopants may be present in any suitable concentration, such as in a concentration in the range of 1E15 to 5E22 atoms per cubic centimeter (cm), or any other suitable concentration as will be apparent in light of this disclosure. Relatively high dopant concentrations (e.g., greater than 1E19, 1E20, or 1E21) may be considered degenerate doping, where the semiconductor material starts to act more like a conductor (or actually does exhibit electrical properties similar to a conductor), as is known in the art. Conventional dopants for group IV semiconductor material (e.g., Si, SiGe, Ge) includes phosphorous (P) and/or arsenic (As) for n-type dopant (donors) and boron (B) for p-type dopant (acceptors), to provide some examples. In addition, conventional dopants for group III-V semiconductor material (e.g., GaAs, InGaAs, InAs) includes Si for n-type dopant (donors) and beryllium (Be), zinc (Zn), and/or magnesium (Mg) for p-type dopant, to provide some examples.

In embodiments where corresponding S/D regions on either side of the channel region (e.g., on either side of the gate stack) are to be used for a FFFET device, the source region 261 may include a bilayer structure, such as is shown in Figures 2F and 3, where that bilayer source region includes first layer 262 and second layer 264. Therefore, in embodiments where the transistor being formed is an FFFET device, the doping scheme for features 262/262-206-265 (bilayer source-channel-drain) may be np-i-p (or np-n-p) or pn-i-n (or pn-p-n), where 'n' represents n-type doped semiconductor material, 'p' represents p-type doped semiconductor material, and 'i' represents intrinsic or nominally undoped semiconductor material, for example. In some such embodiments, it can be understood that the source region first layer 262 may include one of n-type and p-type dopant and the source region second layer 264 includes the other of n-type and p-type dopant relative to the first layer 262. In addition, in some such embodiments, the drain region 265 may include the same dopant type as the source region second layer 264, such that they both include n-type or p-type dopant, for example. Thus, in some such embodiments, the drain region 265 may include the other of n-type and p-type dopant relative to the source region first layer 262, for example. Also note that the channel region 206 for FFFET devices or any other transistors that can be formed using the techniques described herein may be intrinsic or nominally undoped (e.g., with impurity dopant concentrations of less than 1E16, 1E17, or 1E18 atoms per cubic cm) or the channel region 206 may be doped with suitable n-type or p-type dopant, as will be apparent in light of this disclosure.

In embodiments where corresponding S/D regions on either side of the channel region (e.g., on either side of the gate stack) are to be used for a TFET device, recall that the source need not have a bilayer structure, such that the source region 261 is only one layer, for example. In some such embodiments, the S/D regions may include opposite types of dopant in a source- channel-drain scheme of either p-i-n (e.g., for p-TFET) or n-i-p (e.g., for n-TFET), for example. In some embodiments, where corresponding S/D regions on either side of the channel region (e.g., on either side of the gate stack) are to be used for a MOSFET device, the S/D regions may each include the same type of dopant in a source-channel-drain doping scheme of either p-n-p (e.g., for p-MOS) or n-p-n (e.g.. for n-MOS), for example. For instance, in some such embodiments, n-p-n and/or p-n-pMOSFET devices may be included with tunnel transistor devices (e.g., FFFETs and/or TFETs) in the same circuit (e.g., for forming CMOS devices). In some embodiments, one or both of the S/D regions 261 and 265 may include a multilayer structure of two or more material layers, for example, such as is the case for source region 261 including a bilayer structure in the example embodiments of Figures 2F and 3. In some embodiments, one or both of the S/D regions 261 and 265 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the region(s), where the material graded may relate to the concentration of included semiconductor material (e.g., the concentration of Ge throughout the SiGe material) and/or included dopant, for example. Thus, in accordance with various embodiments, a multitude of transistor types, and thus, S/D configurations and doping schemes, may be employed, as can be understood based on this disclosure. Further, the configurations and/or properties (e.g., included semiconductor material, doping, bandgap properties, relative location, and so forth) of at least two layers/regions/features of the IC structures described herein may be defined in any suitable relative manner, as will be apparent in light of this disclosure.

Recall that in some embodiments, the source region 261 may include different semiconductor material relative to the drain region 265, such as Si in one of the regions and SiGe or Ge in the other. For example, in the case of the bilayer source region of Figures 2F and 3 (e.g., which may be formed for a FFFET device), one or both of the layers 262 and 264 may include different semiconductor material relative to the semiconductor material included in drain region 265, in accordance with some embodiments. Further, in some embodiments, layers 262 and 264 may include the same or different semiconductor material (e.g., both include Si or one includes Si and the other includes SiGe). The use of different semiconductor material in the S/D regions can allow for bandgap engineering to obtain a desired effect, such as increasing band offsets to decrease leakage current in the transistor off-state, as will be described in more detail with respect to Figures 4 and 5. For instance, in some embodiments, semiconductor material may be selected based on relative bandgaps, relative valence band edge (Ev) properties, and/or based on relative conduction band edge (Ec) properties. However, in some embodiments, the source region 261 and drain region 265 may include the same semiconductor material, and in some such embodiments, only the same semiconductor material, for example. For instance, in some such embodiments related to TFET devices, the S/D regions may include the same semiconductor material (e.g., Si), but would be oppositely type doped (e.g., where the source region is n-type doped and the drain region is p-type doped, or where the source region is p-type doped and the drain region is n-type doped). Further, in some such embodiments related to FFFET devices, the S/D regions may include the same semiconductor material (e.g., Si), such that the bilayer source region includes a homojunction configuration (and not a heterojunction configuration), for example.

In embodiments employing the bilayer source region 261 of Figures 2F and 3, the source region second layer 264 may be considered a filter element, such as in a FFFET device, where the filter element is relatively thin, having a thickness (e.g., dimension in the Z-axis direction and/or dimension between 262 and 206 in the Y-axis direction) in the range of 5-50 nm (e.g., 10- 25 nm), or some other suitable thickness as will be apparent in light of this disclosure. Generally, the entirety of the thickness/height (e.g., dimension in the Z-axis direction) of the S/D regions may be any suitable thickness/height, which may be based on the active channel region height, for example. Additional material and doping example configurations will be described herein with reference to Figures 3', 4, and 5. Numerous transistor S/D configurations and variations will be apparent in light of this disclosure.

In some embodiments, a contact resistance reducing layer 266 may be formed on one or both of the S/D regions, where the contact resistance reducing layer 266 may be referred to herein as a cap layer (as it is formed on the top or above the corresponding S/D region) or an intervening layer (as it is formed between at least one S/D region and its corresponding contact), for example. In some embodiments, the contact resistance reducing layer 266 may be formed to assist with ohmic contact by reducing parasitic external resistance by including a higher dopant level/concentration relative to the underlying (or otherwise proximate) S/D region, for example. In some embodiments, contact resistance reducing layer 266 may include a doping concentration (e.g., of any suitable n-type or p-type dopant) that is at least 1E17 to 1E21 atoms per cubic cm (e.g., at least 1E20 atoms per cubic cm) greater than the dopant concentration of the underlying S/D region for which it is providing contact resistance reduction, or some other suitable relative amount as will be apparent in light of this disclosure. In some embodiments, the contact resistance reducing layer 266 may include any suitable material, such as group IV semiconductor material and/or group III-V semiconductor material, or any other suitable semiconductor material as will be apparent in light of this disclosure. In some embodiments, the contact resistance reducing layer 266 may include a multilayer structure including at least two material layers, for example. In some embodiments, the concentration of one or more materials included in the contact resistance reducing layer 266 may be graded (e.g., increased and/or decreased) in any suitable manner, for example. In some embodiments, where contact resistance reducing layer 266 is present, it may include degenerately doped material, such as including n-type and/or p- type dopant concentrations of at least 1E19, 1E20, 5E20, 1E21, 5E21, or 1E22 atoms per cubic cm, or some other suitable minimum threshold dopant concentration to assist with ohmic contact at one or both of the S/D locations.

In some embodiments, contact resistance reducing layer 266 may include similar semiconductor material and/or dopant relative to the directly underlying (or otherwise proximate) S/D material/dopant, for example. For instance, in the example embodiment shown in Figure 2F, where source region 261 includes a bilayer configuration including first layer 262 and second layer 264, the contact resistance reducing layer 266 formed above first layer 262 may include similar or the same semiconductor material as first layer 262 and also may include the same type dopant (e.g., n-type or p-type) relative to what is included in first layer 262, except the dopant concentration in that respective cap layer 266 would be relatively higher. More specifically, in an example embodiment, if first layer 262 were to include n-type Si (e.g., for a p- type FFFET device), then the overlying contact resistance reducing layer 266 may also include n-type Si, with higher levels of n-type dopant relative to that n-type Si first layer (e.g., n-type dopant levels at least 1E20 atoms per cubic cm greater), for instance. As can be understood based on this disclosure, the S/D regions of a transistor device formed using the techniques described herein may include opposite type doping at least in the top portions of the S/D regions. For example, in some embodiments, the S/D regions of a TFET device are oppositely doped, such that one is n-type doped and the other is p-type doped. Therefore, in some such embodiments, if the contact resistance reducing layer 266 is formed over both of the S/D regions, the portion of layer 266 over the n-type doped S/D region may also be n-type doped, and the portion of layer 266 over the p-type doped S/D region may also be p-type doped to provide contact resistance reduction for both S/D regions. However, in some embodiments, contact resistance reducing layer 266 need not include the same semiconductor material as the underlying S/D semiconductor material, such that material engineering via different semiconductor material may be utilized in addition to or alternative to the dopant concentration increase in the contact resistance reducing layer 266 (relative to the underlying S/D semiconductor material). For instance, in an example embodiment, if underlying S/D semiconductor material would be SiGe, a Si cap layer may be used for that S/D region to improve the contact resistance at that location, where the Si cap/contact resistance reducing layer may or may not include relatively higher dopant concentrations.

In example method 100 of Figure 1, box 114 includes employing the contact resistance reducing layer 266 during the S/D processing at this point in the process flow, in accordance with some embodiments. However, in some embodiments, the contact resistance reducing layer 266 (whether formed for the source region, the drain region, or both S/D regions) may be formed later in the process flow, during the S/D contact processing 118, such as forming the contact resistance reducing layer 266 as described herein in one or both of the S/D contact trenches, prior to forming the S/D contacts 290 (shown in Figure 2H), as can be understood based on this disclosure. Recall that the contact resistance reducing layer 266 need not be present between both the source region 261 and its corresponding S/D contact 290 and also the drain region 265 and its corresponding S/D contact 290, in some embodiments. For example, Figure 3' illustrates a variation where the contact resistance reducing layer 266 is formed only between one of the S/D regions and its corresponding contact, specifically, between drain region 265' and its corresponding S/D contact 290, as shown. Also recall that a contact resistance reducing layer 266 may be used to benefit tunneling devices (e.g., TFETs, FFFETs) employing similar material between respective S/D regions or dissimilar/different material between respective S/D regions, as can be understood based on this disclosure. Further, recall that in the case of FFFET devices, the contact resistance reducing layer 266 may benefit such FFFET devices including a bilayer source region, whether the source region includes a heteroj unction configuration or a homojunction configuration, as can also be understood based on this disclosure.

Note that in some embodiments, contact resistance reducing layer 266, where present, may be a distinct layer (e.g., as shown in Figure 2F) or it may be a portion of an S/D region where one or more materials or material concentrations are graded (e.g., increased and/or decreased) relative to the remainder of the S/D region, for example. For instance, when performing S/D processing, the final portion of the S/D formation process may include increasing the doping concentration in a steady or sudden manner to form contact resistance reducing layer 266, to provide an example. In another example, additional dopant may be introduced into the top portion of an S/D region (or the portion formed to be closest to the corresponding S/D contact) relative to the remainder of the S/D region, where the additional dopants may appear to be present in a distinct or graded manner, for instance. Also note that where the contact resistance reducing layer 266 is present for both of the S/D regions, the different portions of the layer 266 (e.g., the portion above the source region and the portion above the drain region) may be formed at different times during the process flow, with different semiconductor material, with different type dopant (e.g., where one portion is n-type doped and the other is p-type doped), with different dopant concentrations, and/or with different configurations (e.g., different geometry, different relative heights in the transistor device, and so forth), in accordance with some embodiments. Numerous different configurations and variations for an S/D contact resistance reducing layer will be apparent in light of this disclosure.

Method 100 of Figure 1 continues with performing 116 gate stack processing to form the example resulting structure of Figure 2G. As shown in Figure 2G, the processing in this example embodiment included depositing interlayer dielectric (ILD) layer 270 on the structure of Figure 2F, followed by optional planarization and/or polishing to reveal the dummy gate stack. Note that ILD layer 270 is shown as transparent in the example structure of Figure 2G to allow for the underlying features to be seen; however, the present disclosure is not intended to be so limited. In some embodiments, the ILD layer 270 may include any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. The gate stack processing, in this example embodiment, continued with removing the dummy gate stack (including dummy gate 244 and dummy gate dielectric 242) to allow for the final gate stack to be formed. Recall that in some embodiments, the formation of the final gate stack, which includes gate dielectric layer 282 and gate (or gate electrode) 284, may be performed using a gate first flow (also called up-front hi-k gate). In such embodiments, the gate processing may have been performed after process 108 or after optional process 110 (in embodiments where process 110 is performed) and prior to the S/D processing 114. However, in this example embodiment, the gate stack is formed using a gate last flow (also called a replacement gate or replacement metal gate (RMG) process). In such gate last processing, the process may include dummy gate oxide deposition, dummy gate electrode (e.g., poly-Si) deposition, and, optionally, patterning hardmask deposition, as previously described. Regardless of whether gate first or gate last processing is employed, the final gate stack can include gate dielectric layer 282 and gate 284 as shown in Figure 2G.

Note that when the dummy gate is removed, the channel region of fins 204 (that were covered by the dummy gate) are exposed to allow for any desired processing of the channel regions of the fins. Such processing of the channel region may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region of the fin as desired, forming the fin into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure. For instance, finned channel region 206 is illustrated (which is the channel region of the right most finned structure), which may have been formed by doping the native fin 204 with a desired suitable n-type or p-type dopant, for example. To provide another example, nanowire channel region 208 (which is the channel region of the left most finned structure) may have been formed after the dummy gate was removed and the channel regions of the fins were exposed, by converting the finned structure at that location using any suitable techniques, for example. As shown, nanowire channel region 208 includes 2 nanowires (or nanoribbons). However, a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1-10 or more, depending on the desired configuration.

As can be understood based on this disclosure, the channel region is at least below the gate stack in this example embodiment. For instance, in the case of a finned transistor configuration, the channel region may be below and between the gate stack, as the stack is formed on three sides as is known in the art. However, if the transistor device were inverted and bonded to what will be the end substrate, then the channel region may be above the gate. Therefore, in general, the gate and channel relationship may include a proximate relationship (which may or may not include intervening gate dielectric layer and/or other suitable layers), where the gate is near the channel region such that it can exert control over the channel region in some manner (e.g., in an electrical manner), in accordance with some embodiments. Further, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may substantially (or completely) surround each nanowire/nanoribbon in the channel region. Further still, in the case of a planar transistor configuration, the gate stack may simply be above the channel region. In some embodiments, the channel region may include group IV semiconductor material (e.g., Si, SiGe, Ge), group III-V semiconductor material (e.g., GaAs, InGaAs, InAs), and/or any other suitable material as will be apparent in light of this disclosure. In some embodiments, semiconductor material included in the channel region may be native to substrate 200 and/or semiconductor material included in the channel region may not be native to substrate 200 (e.g., such that it is replacement material or material formed above substrate 200). Recall that in some embodiments, the channel region may be doped (e.g., with any suitable n-type and/or p-type dopant) or intrinsic/nominally undoped, depending on the particular configuration. Note that the S/D regions are adjacent to either side of the channel region, as can be seen in Figure 2G and 3, for example. More specifically, the S/D regions are directly adjacent the channel region, such that there are no intervening layers between either of the S/D regions and the channel region, in the example embodiments. However, the present disclosure is not intended to be so limited. Also note that the configuration/geometry of a transistor formed using the techniques described herein may primarily be described based on the shape/configuration of the respective channel region of that transistor, for example. For instance, a nanowire (or nanoribbon or GAA) transistor may be referred to as such because it includes one or more nanowires (or nanoribbons) in the channel region of that transistor. However, transistor type (e.g., MOSFET, FFFET, TFET or other suitable type) may be described based on the doping and/or operating scheme of the source, drain, and channel regions, and thus those respective regions may be used to determine the type or classification of a given transistor, for example. This is especially true for MOSFET versus TFET transistors, as they may structurally be very similar (or the same), but include different doping schemes (e.g., p-n-p or n-p-n for MOSFET versus p-i-n or n-i-p for TFET).

Continuing with performing 116 gate stack processing, after the dummy gate has been removed and any desired channel region processing has been performed, the final gate stack can be formed, in accordance with an embodiment. In this example embodiment, the final gate stack includes gate dielectric layer 282 and gate 284, as shown in Figure 2G. The gate dielectric layer 282 may include, for example, any suitable oxide (such as silicon dioxide), high-k gate dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, an annealing process may be carried out on the gate dielectric layer 282 to improve its quality when high-k material is used. The gate 284 (or gate electrode) may include a wide range of materials, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example. In some embodiments, gate dielectric layer 282 and/or gate 284 may include a multilayer structure of two or more material layers, for example. In some embodiments, gate dielectric layer 282 and/or gate 284 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s). Additional layers may be present in the final gate stack, in some embodiments, such as one or more work function layers or other suitable layers, for example. Note that although gate dielectric layer 282 is only shown below gate 284 in the example embodiment of Figure 2G, in other embodiments, the gate dielectric layer 282 may also be present on one or both sides of gate 284, such that the gate dielectric layer 282 is between gate 284 and spacers 250, for example.

Method 100 of Figure 1 continues with performing 118 S/D contact processing to form the example resulting structure of Figure 2H, in accordance with an embodiment. As shown in Figure 2H, S/D contacts 290 were formed to make contact to each of the S/D regions, in this example embodiment. In some embodiments, S/D contacts 290 may be formed using any suitable techniques, such as forming contact trenches in ILD layer 270 over the respective S/D regions and depositing metal or metal alloy (or other suitable electrically conductive material) in the trenches. In some embodiments, S/D contact 290 formation may include silicidation, germinidation, and/or annealing processes, for example. In some embodiments, S/D contacts 290 may include aluminum or tungsten, although any suitable conductive metal or alloy can be used, such as silver, nickel-platinum, or nickel-aluminum, for example. In some embodiments, one or more of the S/D contacts 290 may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance. Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used. In some embodiments, additional layers may be present in the S/D contact 290 regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired.

Figure 2H' illustrates the example structure of Figure 2H, including vertical isolation structures 230 of Figure 2D', in accordance with an embodiment. Recall that process 110 is optional, such that the vertical isolation structures 230 need not be included in the IC structure. However, in the example structure of Figure 2H', two such structures 230 are present. The vertical isolation structures 230 may be etch resistant to the etch processes used during the IC fabrication (e.g., by the inclusion of an etch-resistant material, such as carbon), and thus, they may further isolate single fins or groups of fins. For instance, as shown in Figure 2H', the vertical isolation structures 230 are isolating the three right-most S/D regions from other portions of the IC structure (such as the left-most S/D regions). Such a configuration may be desired where, for example, those three right-most S/D regions are all of the same polarity (e.g., all n- type or all p-type), thereby allowing those same polarity S/D regions to be isolated from other polarity S/D regions (such as if the left-most S/D regions were the other polarity of n-type and p- type). The vertical isolation structures 230 may also allow for the material of adjacent S/D regions and/or S/D contacts to merge together, thereby providing barriers where desired to prevent said S/D region and/or S/D contact material from merging or contacting undesired material (such as S/D regions or contacts of another polarity). Numerous benefits of the vertical isolation structures 230 will be apparent in light of this disclosure and such vertical isolation structures 230 (where present) may be formed and included in the IC structure where desired.

Method 100 of Figure 1 continues with completing 120 integrated circuit (IC) processing, as desired, in accordance with some embodiments. Such additional processing to complete the IC may include back-end or back-end-of-line (BEOL) processing to form one or more metallization layers and/or to interconnect the transistor devices formed, for example. Any other suitable processing may be performed, as will be apparent in light of this disclosure. Note that the processes 102-120 of method 100 are shown in a particular order in Figure 1 for ease of description. However, one or more of the processes 102-120 may be performed in a different order or may not be performed at all. For example, box 110 is an optional process that need not be performed if the etch resistant vertical structures are not desired. Further, box 112 is an optional process that need not be performed in embodiments employing a gate first process flow, for example. Moreover, such a gate first process flow changes when process 116 is performed, as shown using alternative and optional gate first flow 100', whereby the final gate stack processing is performed 116 prior to performing 114 the S/D processing. Numerous variations on method 100 and the techniques described herein will be apparent in light of this disclosure. Recall that the techniques may be used to form one or more transistor devices including any of the following: field-effect transistors (FETs), Fermi filter FETs (FFFETs), tunnel-FETs (TFETs), planar configurations, finned configurations (e.g., fin-FET, tri-gate, dual-gate), and/or nanowire (or nanoribbon or gate-all-around) configurations (having any number of nanowires). In addition, the devices formed may include p-type transistor devices (e.g., p-FFFET or p-TFET) and/or n-type transistor devices (e.g., n-FFFET or n-TFET). Further, the devices may include complementary MOS (CMOS) devices or quantum devices (few to single electron), to provide additional examples.

Figure 3 illustrates an example cross-sectional view taken along one fin of the IC structure of Figure 2H, specifically taken along the A-A plane, in accordance with some embodiments of the present disclosure. Figure 3 is provided to assist in illustrating different components of the structure of Figure 2H. Therefore, the previous relevant description with respect to each similarly numbered feature is equally applicable to Figure 3. However, note that the dimensions of the features shown in Figures 2H and 3 may differ, for ease of illustration. Also note that some variations occur between the structures, such as the shape of spacers 250 and the S/D contacts 290 extending all the way to the spacers 250, for example, as is shown in Figure 3. Figure 3' also illustrates the variation to the techniques where the contact resistance reducing layer 266 is only formed for one of the S/D regions, and specifically in this example embodiment, only for the drain region 265, such that the resistance reduction layer 266 is not present between the source region 26 Γ and its corresponding S/D contact 290 as shown. Figure 3' illustrates the IC structure of Figure 3, including shading and patterning to assist with visualizing the material and doping scheme of the S/D regions, in accordance with some embodiments of the present disclosure. The previous relevant description with respect to each similarly numbered feature is equally applicable to Figure 3'. However, note that in the example structure of Figure 3', bilayer source region 26 Γ, including first layer 262' and second layer 264', and drain region 265' each have shading and patterning to assist in visually representing relative included material and doping schemes, in accordance with some embodiments.

For instance, in Figure 3' source region first layer 262' includes diagonal line patterning with a positive slope (i.e., goes from a bottom-left to top-right direction) to visually indicate that it includes different type dopant relative to both source region second layer 264' and drain region 265', which both include diagonal line patterning with a negative slope (i.e., goes from a top-left to bottom-right direction), in accordance with some embodiments. In some such embodiments, first layer 262' includes one of p-type and n-type dopant, while second layer 264' and drain region 265' include the other of p-type and n-type dopant relative to the first layer 262', such that one of 262' and 2647265' includes p-type dopant and the other includes n-type dopant. Further, second layer 264' includes shading to indicate that it includes different semiconductor material relative to first layer 262' and drain region 265', in accordance with some embodiments. In some such embodiments, first layer 262' and drain region 265' may thus include the same semiconductor material; however, the present disclosure need not be so limited, such that they may include different semiconductor material, in other embodiments. Example material configurations and doping schemes will be described herein with reference to Figures 4 and 5. Recall that for a TFET device, source region 26 Γ may only include one primary portion similar to the configuration for drain region 265' (and not a bilayer structure as shown in Figure 3'), where the source region 26 Γ includes different semiconductor material relative to the drain region and includes different a dopant type. Also note that the techniques may be applied to other suitable transistor types. For instance, MOSFET devices (e.g., including an n-p-n or p-n-p doping scheme) may benefit from the inclusion of different semiconductor material in S/D regions, as will be apparent in light of this disclosure. Numerous variations and configurations will be apparent in light of the present disclosure.

Example FFFET Energy Band Diagrams

Figures 4 and 5 illustrate example p-type and n-type FFFET energy band diagrams, respectively, for FFFET devices including S/D regions employing different semiconductor material, in accordance with some embodiments. Note that features from the structures of Figures 2H and 3 are included below the energy band diagrams in a schematic structure to show the different portions of the band diagrams and illustrate how current can flow through FFFET devices. However, the first number of related numerals for each feature has been changed to match the number of the corresponding figure, as the features in Figures 4 and 5 are described with reference to specific material and doping configurations as shown. Therefore, the previous relevant description with respect to those similar features is equally applicable to the schematic structure shown at the bottoms of Figures 4 and 5. As can also be understood, Figures 4 and 5 include the shading and patterning of Figure 3' to assist with visually identifying the material and doping differences between the S/D regions.

To assist with description, example p-type FFFET schematic structure of Figure 4 includes, from left to right (along with included material), S/D contact 490 (metal or metal alloy), contact resistance reducing layer 466, source region first layer 462 (n-type Si), source region second layer 464 (p-type SiGe), channel region 406 (i-type Si), drain region 465 (p-type Si), contact resistance reducing layer 466, and S/D contact 490 (metal or metal alloy). As can be understood, the first S/D contact 490 is specifically the source region 261 contact and the second S/D contact 490 is specifically the drain region 265 contact, in this example embodiment. In addition, the contact resistance reducing layers 466 between both of the S/D regions and their corresponding contacts are identified using the same number (466) for ease of reference. However, recall, in some embodiments, those separate layers 466 may be formed at different times during the process flow, with different semiconductor material, with different type dopant (e.g., where one portion is n-type doped and the other is p-type doped), with different dopant concentrations, and/or with different configurations (e.g., different geometry, different relative heights in the transistor device, and so forth), in accordance with some embodiments. Further, the example n- type FFFET schematic structure of Figure 5 includes, from left to right (along with included material), S/D contact 590 (metal or metal alloy), contact resistance reducing layer 566, source region first layer 562 (p-type GaAs), source region second layer 564 (n-type InGaAs), channel region 506 (i-type GaAs), drain region 565 (n-type GaAs), contact resistance reducing layer 566, and S/D contact 590 (metal or metal alloy).

In the example embodiments of Figures 4 and 5, the source regions 461 and 561 include a heterojunction structure, as the source region first layer 462/562 includes different semiconductor material relative to source region second layer 464/564 (e.g., Si compared to SiGe and GaAs compared to InGaAs, respectively). Further, the source regions 461/561 include different semiconductor material relative to the drain regions 465/565, respectively, in the example embodiments. For instance, using the example p-type FFFET device of Figure 4, SiGe is included in the source region 461 (specifically, in second layer 464 of the source region), while Si is the only semiconductor material in the drain region, in the example embodiment. Thus, they include different semiconductor material. In addition, the source regions 461 and 561 include a bilayer structure that includes a p-n or n-p diode configuration, as can be understood based on this disclosure. Note that, as a result of the diode in the source region, FFFET devices are sometimes referred to as tunnel source MOSFETs. Further, as was explained with respect to Figure 3', in the example FFFET devices of Figures 4 and 5, the source region second layers 464/564 include the same type of doping as their respective drain regions 465/565 (e.g., both p- type and both n-type, respectively), which is the other of n-type and p-type relative to the respective source region first layer 462/562, such that the example p-type FFFET structure of Figure 4 includes a np-i-p doping scheme and the example n-type FFFET structure of Figure 5 includes a pn-i-n doping scheme. However, recall that the channel regions may be doped, such that the p-type FFFET device may include a np-n-p doping scheme and the n-type FFFET device may include a pn-p-n doping scheme, in accordance with some embodiments.

Continuing with the energy band diagrams for the schematic FFFET structures of Figures 4 and 5, as shown in those figures, they each include energy band diagrams for the off-states 400/500 and on-states 401/501 of the devices, respectively. In addition, the energy (E) increases in an upward direction for all diagrams, as shown by the arrow on the left side of each figure. Further, the conduction band edge (Ec) and valence band edge (Ev) are both illustrated, as is common to plot key electron energy levels. As can also be understood, the bandgap is the energy difference (in electron volts) between Ec and Ev, as is known in the art. The corresponding S/D and channel regions are aligned with the energy band diagrams as shown to illustrate the benefits derived from the techniques and structures described herein. Note that exact band diagrams and values are not provided; however, the benefits derived from the techniques and structures described herein can be understood using these example energy band diagrams, as will be apparent. With reference to the example p-type FFFET device of Figure 4, it can be understood that by including SiGe in source region second layer 464 in a heteroj unction configuration (i.e., dissimilar crystalline semiconductor material configuration), due to the first layer 462 including Si, an increase in Ev for that layer 464 can be obtained relative to a homojunction configuration (e.g., if 464 were to include Si instead of SiGe, such that the layers include the same or similar semiconductor material). The increase in Ev relative to such a hypothetical homojunction Ev (indicated in dashed lines) is represented as delta Ev and provides the benefit of increasing the barrier height for the charge carriers at that 462/464 layer interface, thereby reducing off-state leakage (particularly for these FFFET devices that include carriers tunneling through the bilayer source tunnel-diode at all conditions or other devices that operate via band-to-band tunneling). In some such embodiments, the Ge concentration in the SiGe material included in second layer 464 may be in the range of 10-50 percent to provide such bandgap engineering benefits, or any other suitable Ge concentration as will be apparent in light of this disclosure. In addition, for completion of description, during the off-state 400, the channel region potential can block the low energy carriers, as can be understood. Further, the p-FFFET device can still effectively operate in the on-state 401, as can also be understood.

The example n-FFFET device of Figure 5 includes a similar principle, except that by including InGaAs in source region second layer 564 in a heteroj unction configuration (as opposed to layer 564 including GaAs in a homojunction configuration), a decrease in Ec for that layer 564 can be obtained relative to a homojunction configuration, which is beneficial for the n- type device. The decrease in Ec relative to such a hypothetical homojunction Ec (indicated in dashed lines) is represented as delta Ec and provides the benefit of increasing the barrier height (albeit, in an inverted fashion relative to that in Figure 4) for the carriers at that 562/564 layer interface, thereby reducing off-state leakage (again, particularly for tunneling devices, such as FFFET devices, that include carriers tunneling at all conditions). In some such embodiments, the In concentration in the InGaAs material included in second layer 564 may be in the range of 5-70 percent to provide such bandgap engineering benefits, or any other suitable In concentration as will be apparent in light of this disclosure. In addition, again, during the off-state 500, the channel region potential can block the low energy carriers, as can be understood. Further, the n- FFFET device can still effectively operate in the on-state 501, as can also be understood. Note that in both of the situations of Figures 4 and 5, the different material that created the heterojunction source region structures have a smaller bandgap than the other semiconductor material included in the source region (e.g., SiGe has a smaller bandgap than Si and InGaAs has a smaller bandgap than GaAs). Therefore, in some embodiments, semiconductor material included in the source region of a transistor formed using the techniques described herein may have a smaller bandgap, a higher valence band edge (Ev), and/or a lower conduction band edge (Ec) relative to one or both of other semiconductor material included in the source region (e.g., the material of the other layer in a bilayer structure) and semiconductor material included in the drain region. Numerous variations and configurations will be apparent in light of the present disclosure.

Example System

Figure 6 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set -top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit (IC) including: a substrate; and a transistor at least one of above and in the substrate, the transistor including a gate, a channel region proximate the gate, source and drain (S/D) regions adjacent the channel region, wherein the source region includes a first semiconductor material including one of n-type and p-type dopant, and wherein the drain region includes a second semiconductor material different than the first semiconductor material, the second semiconductor material including one of n-type and p-type dopant, a contact electrically connected to one of the S/D regions, and an intervening layer between the contact and the S/D region, wherein the intervening layer includes a higher dopant concentration relative to the S/D region.

Example 2 includes the subject matter of Example 1, wherein the intervening layer includes a maximum dopant concentration of at least 1E20 atoms per cubic centimeter (cm) greater than the maximum dopant concentration of the S/D region.

Example 3 includes the subject matter of Example 1 or 2, wherein the first semiconductor material is silicon germanium (SiGe) and the second semiconductor material is silicon (Si).

Example 4 includes the subject matter of Example 1 or 2, wherein the first semiconductor material is indium gallium arsenide (InGaAs) and the second semiconductor material is gallium arsenide (GaAs).

Example 5 includes the subject matter of any of Examples 1-4, wherein the second semiconductor material includes the other of n-type and p-type dopant relative to the first semiconductor material.

Example 6 includes the subject matter of any of Examples 1-4, wherein the second semiconductor material includes the one of n-type and p-type dopant included in the first semiconductor material.

Example 7 includes the subject matter of any of Examples 1-6, wherein the source region includes a bilayer configuration, such that a third semiconductor material is included in a first layer in the source region and the first semiconductor material is included in a second layer in the source region, wherein the second layer is between the first layer and the channel region. Example 8 includes the subject matter of Example 7, wherein the first layer includes the other of n-type and p-type dopant relative to the first semiconductor material.

Example 9 includes the subject matter of Example 7 or 8, wherein the third semiconductor material is the same as the second semiconductor material.

Example 10 includes the subject matter of any of Examples 7-9, wherein the second layer is between the first layer and the substrate.

Example 11 includes the subject matter of any of Examples 1-10, wherein the first and second semiconductor materials each include group IV semiconductor material.

Example 12 includes the subject matter of any of Examples 1-10, wherein the first and second semiconductor materials each include group III-V semiconductor material.

Example 13 includes the subject matter of any of Examples 1-12, wherein the channel region includes a configuration that is at least one of planar, finned, double-gate, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA).

Example 14 includes the subject matter of any of Examples 1-13, wherein the transistor is a Fermi filter field-effect transistor (FFFET).

Example 15 includes the subject matter of any of Examples 1-13, wherein the transistor is a tunnel field-effect transistor (TFET).

Example 16 is a complementary metal-oxide-semiconductor (CMOS) device including the subject matter of any of Examples 1-15.

Example 17 is a computing system including the subject matter of any of Examples 1-16.

Example 18 is an integrated circuit (IC) including: a substrate; and a transistor at least one of above and in the substrate, the transistor including a gate, a channel region proximate the gate, a source region adjacent the channel region, the source region including a first layer and a second layer between the first layer and the channel region, the first layer including a first semiconductor material and one of n-type and p-type dopant, the second layer including a second semiconductor material and the other of n-type and p-type dopant relative to the first layer, a drain region adjacent the channel region, the drain region including a third semiconductor material and the other of n-type and p-type dopant relative to the first layer, a contact electrically connected to one of the source and drain (S/D) regions, and an intervening layer between the contact and the S/D region, wherein the intervening layer includes a higher dopant concentration relative to the S/D region. Example 19 includes the subject matter of Example 18, wherein the intervening layer includes a maximum dopant concentration of at least 1E20 atoms per cubic centimeter (cm) greater than the maximum dopant concentration of the S/D region.

Example 20 includes the subject matter of Example 18 or 19, wherein the intervening layer includes a maximum dopant concentration of at least 1E21 atoms per cubic centimeter (cm).

Example 21 includes the subject matter of any of Examples 18-20, wherein the first semiconductor material is the same as the second semiconductor material.

Example 22 includes the subject matter of any of Examples 18-20, wherein the first semiconductor material is different than the second semiconductor material.

Example 23 includes the subject matter of any of Examples 18-21, wherein the first, second, and third semiconductor materials all include silicon (Si).

Example 24 includes the subject matter of any of Examples 18-20 or 22, wherein the second semiconductor material has a higher valence band edge (Ev) relative to the first semiconductor material.

Example 25 includes the subject matter of any of Examples 18-20, 22, or 24, wherein the second semiconductor material has a lower conduction band edge (Ec) relative to the first semiconductor material.

Example 26 includes the subject matter of any of Examples 18-25, wherein the third semiconductor material is the same as the first semiconductor material.

Example 27 includes the subject matter of any of Examples 18-25, wherein the third semiconductor material is different than the first semiconductor material.

Example 28 includes the subject matter of any of Examples 18-26, wherein the first layer includes n-type dopant, the second layer includes p-type dopant, and the drain region includes p- type dopant.

Example 29 includes the subject matter of any of Examples 18-26, wherein the first layer includes p-type dopant, the second layer includes n-type dopant, and the drain region includes n- type dopant.

Example 30 includes the subject matter of any of Examples 18-29, wherein the channel region includes intrinsic or nominally undoped semiconductor material.

Example 31 includes the subject matter of any of Examples 18-29, wherein the channel region includes one of n-type and p-type dopant. Example 32 includes the subject matter of any of Examples 18-31, wherein the channel region includes a configuration that is at least one of planar, finned, double-gate, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA).

Example 33 includes the subject matter of any of Examples 18-32, wherein the transistor is a Fermi filter field-effect transistor (FFFET).

Example 34 is a complementary metal-oxide-semiconductor (CMOS) device including the subject matter of any of Examples 18-33.

Example 35 is a computing system including the subject matter of any of Examples 18-34.

Example 36 is a method of forming an integrated circuit (IC), the method including: forming a source region adjacent a channel region of a transistor, wherein the source region includes a first semiconductor material including one of n-type and p-type dopant; forming a drain region adjacent to the channel region of the transistor, wherein the drain region includes a second semiconductor material different than the first semiconductor material, the second semiconductor material including one of n-type and p-type dopant; forming a contact above one of the source and drain (S/D) regions; and forming an intervening layer between the contact and the S/D region, wherein the intervening layer includes a higher dopant concentration relative to the S/D region.

Example 37 includes the subject matter of Example 36, wherein the intervening layer includes a maximum dopant concentration of at least 1E20 atoms per cubic centimeter (cm) greater than the maximum dopant concentration of the S/D region.

Example 38 includes the subject matter of Example 36 or 37, wherein the first semiconductor material is silicon germanium (SiGe) and the second semiconductor material is silicon (Si).

Example 39 includes the subject matter of Example 36 or 37, wherein the first semiconductor material is indium gallium arsenide (InGaAs) and the second semiconductor material is gallium arsenide (GaAs).

Example 40 includes the subject matter of any of Examples 36-39, wherein the second semiconductor material includes the other of n-type and p-type dopant relative to the first semiconductor material.

Example 41 includes the subject matter of any of Examples 36-39, wherein the second semiconductor material includes the one of n-type and p-type dopant included in the first semiconductor material. Example 42 includes the subject matter of any of Examples 36-41, wherein the source region includes a bilayer configuration, such that a third semiconductor material is included in a first layer in the source region and the first semiconductor material is included in a second layer in the source region, wherein the second layer is between the first layer and the channel region.

Example 43 includes the subject matter of Example 42, wherein the first layer includes the other of n-type and p-type dopant relative to the first semiconductor material.

Example 44 includes the subject matter of Example 42 or 43, wherein the third semiconductor material is the same as the second semiconductor material.

Example 45 includes the subject matter of any of Examples 42-44, wherein the second layer is between the first layer and the substrate.

Example 46 includes the subject matter of any of Examples 36-45, wherein the first and second semiconductor materials each include group IV semiconductor material.

Example 47 includes the subject matter of any of Examples 36-45, wherein the first and second semiconductor materials each include group III-V semiconductor material.

Example 48 includes the subject matter of any of Examples 36-47, wherein the channel region includes a configuration that is at least one of planar, finned, double-gate, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA).

Example 49 includes the subject matter of any of Examples 36-48, wherein the transistor is a Fermi filter field-effect transistor (FFFET).

Example 50 includes the subject matter of any of Examples 36-48, wherein the transistor is a tunnel field-effect transistor (TFET).

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.