A turbo decoder for decoding an input signal

TECHNICAL FIELD

The invention relates to the field of turbo-decoding.

BACKGROUND OF THE INVENTION

Long-haul optical fiber communication systems can be used to achieve a high data throughput over a long distance without signal regeneration in the optical domain.

In optical fiber communication systems, polarization multiplexing, quadrature amplitude modulation and coherent detection appear as a promising combination for the next generation of high-capacity optical transmission systems since they allow information encoding in many available degrees of freedom.

In optical fiber communication systems, specifications for the output bit error rate (BER) are usually demanding. In some applications, a BER value lower than 10 ^"15 is desired. This can be a challenge for the design of error correction codes and error correction decoders. While efficient error correction decoders may suffer from low performance, high performance decoders may suffer from a high error floor and/or an insufficient bit error correction capability.

A promising decoding scheme is provided by turbo decoders using soft decision decoding as described in F. Yu, N. Stojanovic, F.N. Hauske, D. Chang, Z. Xiao, G. Bauch, D. Pflueger, C. Xie, Y. Zhao, L. Jin, Y. Li, L. Li, X. Xu, Q. Xiong, "Soft-Decision LDPC Turbo Decoding for DQPSK Modulation in Coherent Optical Receivers", ECOC201 1 , 201 1 .

Despite of the good decoding performance of turbo decoders, there may exist a need for improving the error correction performance even further. SUMMARY OF THE INVENTION

It is the object of the invention to provide an efficient turbo decoder with an improved error correction performance.

This object is achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

The invention is based on the finding that limiting information exchanged by decoders of a turbo decoder can allow for an improved error correction performance.

In order to describe the invention in detail, the following terms, abbreviations and notations will be used:

MAP: Maximum A Posteriori Probability

LDPL: Low Density Parity Check

FEC: Forward Error Correction

LLR: Log-Likelihood Ratio

APP: A Posteriori Probability BCJR: Bahl-Cocke-Jelinek-Raviv

SOVA: Soft Output Viterbi Algorithm

ADC: Analogue/Digital Converter

AGC: Automatic Gain Control

FIR: Finite Impulse Response CD: Chromatic Dispersion

VCO: Voltage Controlled Oscillator QPSK: Quaternary Phase Shift Keying

DP-QPSK: Dual Polarization Quaternary Phase Shift Keying

FFT: Fast Fourier Transform

IFFT: Inverse Fast Fourier Transform DSP: Digital Signal Processing

OFE: Optical Front End

BER: Bit Error Rate

DE: Differential Encoder

DD: Differential Decoder MOD: Modulator

NCG: Net Coding Gain

CPE: Continuous Phase Encoder

CPR: Compact Position Report

SDE: Standard Deviation Estimation TD: Time Domain

FD: Frequency Domain

According to a first aspect, the invention relates to a turbo decoder for decoding an input signal, comprising a first decoder, a second decoder, a first limiter arranged between the first decoder and the second decoder, and a second limiter arranged between the second decoder and the first decoder. Thus, an efficient turbo decoder can be realized.

The turbo decoder can be configured to decode an input signal encoded with a forward error correction (FEC) code. The input signal can be a sampled and quantized communication signal. The input signal can be derived from an optical fiber communication signal. The first decoder can be configured to output information in the form of a log-likelihood ratio (LLR) for each bit or symbol of the sampled and quantized communication signal. The first decoder can further be configured to output information representing a posteriori probabilities (APP) in logarithmic domain. The second decoder can be configured to generate extrinsic information for the first decoder from the output information of the first decoder. The second decoder can further be configured to output information representing APP in logarithmic domain.

The first limiter can be configured to limit the APP values determined by the first decoder.

The second limiter can be configured to limit the extrinsic information determined by the second decoder.

In a first possible implementation form according to the first aspect as such, the first decoder is a maximum a posteriori probability (MAP) decoder. Thus, an efficient decoder can be used.

The MAP decoder can be based on maximum a posteriori probability estimation. The BCJR scheme, the max-star scheme, or the SOVA scheme can be used in the MAP decoder.

In a second possible implementation form according to the first aspect as such or the first implementation form of the first aspect, the second decoder is an LDPC decoder. Thus, an efficient error correction scheme can be used. The LDPC decoder can be configured to decode a signal encoded with a low-density parity check (LDPC) code.

In a third possible implementation form according to the first aspect as such or the first or the second implementation form of the first aspect, the turbo decoder further comprises summation means arranged between the second limiter and the first decoder, the summation means being configured to sum up the output information of the second limiter. Thus, a signal comprising extrinsic information for the first decoder can be provided. - -

The summation means can be configured to provide a signal comprising extrinsic information for the first decoder by summing up the output information signals of the second limiter.

In a fourth possible implementation form according to the third implementation form of the first aspect, the turbo decoder further comprises an adder for adding output signals from the first limiter and from the summation means. Thus, a signal for a decoding decision can be provided.

The decoding decision can be a hard decision.

In a fifth possible implementation form according to the fourth implementation form of the first aspect, the turbo decoder further comprises a decider being configured for performing a hard decision upon the basis of the addition signal. Thus, a decoded signal can be provided.

In a sixth possible implementation form according to the first aspect as such or any of the preceding implementation forms of the first aspect, the turbo decoder further comprises a subtracting means arranged between the first decoder and the first limiter, the subtracting means being configured to subtract the limited information of the second decoder from the output of the first decoder. Thus, an input signal for the second decoder can be provided.

In a seventh possible implementation form according to the first aspect as such or any of the preceding implementation forms of the first aspect, the second limiter is configured to transmit an output to the second decoder. Thus, a feedback loop can be provided for the second decoder.

In an eighth possible implementation form according to the first aspect as such or any of the preceding implementation forms of the first aspect, the turbo decoder further comprises a deviation estimator, the deviation estimator being configured to determine a standard deviation of the input signal and to provide the standard deviation to the first decoder for MAP decoding. Thus, a standard deviation of the input signal can be provided to the first decoder. In a ninth possible implementation form according to the eighth implementation form of the first aspect, the turbo decoder further comprises a multiplier arranged between the second decoder and the second limiter, the multiplier being configured to multiply an output of the second decoder by an output of the deviation estimator. Thus, a signal comprising weighted extrinsic information can be provided.

In a tenth possible implementation form according to the eighth or the ninth implementation form of the first aspect, the turbo decoder further comprises a determiner for determining a first limitation parameter for the first limiter upon the basis of an output of the deviation estimator and a first predetermined parameter, and for determining a second limitation parameter for the second limiter upon the basis of the first limitation parameter and a second predetermined parameter. Thus, a first limitation parameter for configuring the first limiter and a second limitation parameter for configuring the second limiter can be provided.

The first limitation parameter can be given by

L -—

f ^~ s ² '

where L _f denotes the first limitation parameter, n denotes the first predetermined parameter, and s denotes the standard deviation of the input signal determined by the deviation estimator.

The first predetermined parameter n can be one of the following parameters: 1 .4, 2.3, 2.5, 4.2, 12, 17.1 , 21 .

The first limiter can be configured to determine its absolute limiting values based on the first limitation parameter.

The second limitation parameter can be given by

where L _s denotes the second limitation parameter, L _f denotes the first limitation parameter, and m denotes the second predetermined parameter.

The second predetermined parameter m can be one of the following parameters: 0.04, 0.6, 0.91 , 1 , 2.1 , 2.4, 13.

The second limiter can be configured to determine its absolute limiting values based on the second limitation parameter. - -

In an eleventh possible implementation form according to the tenth implementation form of the first aspect, the determiner is arranged between the deviation estimator and the first limiter, the determiner being configured to transmit the first limitation parameter to the first limiter. Thus, the first limitation parameter can be provided to the first limiter.

In an twelfth possible implementation form according to the tenth or the eleventh

implementation form of the first aspect, the determiner is arranged between the deviation estimator and the second limiter, the determiner being configured to transmit the second limitation parameter to the second limiter. Thus, the second limitation parameter can be provided to the second limiter.

According to a second aspect, the invention relates to a method for turbo-decoding an input signal, the method comprises decoding the input signal using a first decoder generating a first decoded signal, subtracting a limited extrinsic information signal from the first decoded signal to obtain a subtracted signal, decoding the subtracted signal using a second decoder generating a second decoded signal, weighting the second decoded signal by a standard deviation of the input signal to obtain a weighted signal, and limiting the weighted signal or a processed version thereof to obtain the limited extrinsic information signal. Thus, an efficient method for decoding an input signal in a turbo decoder can be provided.

Further features of the method directly result from the functionality of the turbo decoder according to the first aspect as such or any preceding implementation form of the first aspect. The method can e.g. be performed by the turbo decoder according to the first aspect as such or any preceding implementation form of the first aspect.

According to a third aspect, the invention relates to a computer program for performing the method of the second aspect as such when executed on a computer. Thus, the method can be performed in an automatic and repeatable manner.

The computer program can be provided in form of a machine-readable code. The computer program can comprise a series of commands for a processor of the computer. The processor of the computer can be configured to execute the computer program.

The computer can comprise a processor, a memory, and/or an input/output means. The invention can be implemented in hardware and/or software.

Further embodiments of the invention will be described with respect to the following figures, in which:

Fig. 1 shows a schematic diagram of basic DSP blocks of a dual-polarization coherent optical receiver;

Fig. 2 shows a schematic diagram of a transmission system with differential encoding; and

Fig. 3 shows a schematic diagram of a turbo decoder for decoding an input signal.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Fig. 1 shows a schematic diagram of basic Digital Signal Processing (DSP) blocks of a dual- polarization coherent optical receiver 100.

The dual-polarization coherent optical receiver 100 comprises an analogue to digital converter (ADC) means 101 , an offset and gain adjustment, automatic gain control (AGC), means 103 arranged downstream of the ADC means 101 , a chromatic dispersion (CD) compensation means 105 arranged downstream of the AGC means 103, a frequency recovery means 107 arranged downstream of the CD compensation means 105, a finite impulse response (FIR) means 109 arranged downstream of the frequency recovery means 107, a timing estimation means 1 1 1 connected to the CD compensation means 105 and to the FIR means 109, a voltage controlled oscillator (VCO) means 1 13 arranged between the timing estimation means 1 1 1 and the ADC means 101 , a carrier recovery means 1 15 arranged downstream of the FIR means 109, and a decoding means 1 17 arranged downstream of the carrier recovery means 1 15.

The ADC means 101 can comprise a plurality of analogue to digital converters, e.g. one for each input signal.

The CD compensation means 105 can comprise a plurality of CD compensators, e.g. one for X-polarization and one for Y-polarization. - -

After an offset and gain correction in the AGC means 103, the four signals are equalized in the CD compensation means 105 for chromatic dispersion in frequency domain using two fast Fourier transformation (FFT) blocks. A frequency offset is removed in a frequency recovery means 107. Polarization tracking, PMD compensation, and residual CD

compensation are done in time domain (TD) using FIR filters arranged in butterfly structure in the FIR means 109. A residual frequency offset and a carrier phase recovery is done in the carrier recovery means 1 15. A forward error correction (FEC) repairs incorrect bits/symbols in the decoding means 1 17. The decoding means 1 17 (FEC block) could be configured to use hard information and could be placed on the line side. However, to improve the systems performance, the decoding means 1 17 (FEC block) can also be implemented in an ASIC and can use soft information. This way, the total performance can be improved regarding BER, power dissipation, size and/or DEMUX complexity.

A challenging problem in systems using phase modulation can be the phase ambiguity. To mitigate this problem, a differential encoder can be used at the transmitter side. At the receiver side, the received signal can be processed by the shown blocks and decoded differentially later.

Fig. 2 shows a schematic diagram of a transmission system 200 with differential encoding.

The transmission system 200 comprises an FEC encoding means 201 , a differential encoding means, differential encoder (DE), 203 arranged downstream of the FEC encoding means 201 , a modulator (MOD) means 205 arranged downstream of the DE means 203, a transmission link 207 arranged downstream of the MOD means 205, an OFE means 209 arranged downstream of the transmission link 207, a DSP means 21 1 arranged downstream of the OFE means 209, a differential decoding means, differential decoder (DD), 213 arranged downstream of the DSP means 21 1 , and an FEC decoder means 215 arranged downstream of the DD means 213.

The DE means 203 can comprise a plurality of differential encoders, e.g. one for X- polarization and one for Y-polarization.

The DD means 213 can comprise a plurality of differential decoders, e.g. one for X- polarization and one for Y-polarization. - -

The FEC decoding means 215 can comprise a plurality of FEC decoders, e.g. one for X- polarization and one for Y-polarization.

In optical systems, a differential encoder means 203 and a differential decoder means 213 can be used as shown in Fig. 2. Since both polarizations can be used in coherent optical systems, two differential encoders can be employed. In the FEC encoding means 201 and/or in the FEC decoding means 215 one FEC device can cover both polarizations or two FEC devices can be used alternatively, e.g. one per polarization.

Two times two electrical signals can modulate a laser signal in the modulator means 205. Link impairments can be compensated in the DSP means 21 1 after optical-to-electrical conversion in the optical front-end (OFE) means 209. Since CPE&CPR (continuous phase encoder and compact position report) can introduce cycle slips, it is desirable to correct them using the differential decoder means 213.

The differential decoder means 213 can be configured to output either soft or hard information. Since an enhanced performance can be achieved by using a soft FEC scheme, the DD means 213 provides soft information. The quality of soft information can influence the post-FEC BER.

A good performance can be achieved using a turbo demodulation approach, where a soft FEC and a differential decoder exchange extrinsic information. The maximum a posteriori probability (MAP) block can be realized e.g. via trellis using BCJR, max-star, SOVA or further algorithms to produce soft information for the FEC decoder.

Strong FEC schemes with medium implementation complexity are provided by a group of low-density parity check (LDPC) codes, the quasi cyclic (QC-LDPC) codes. This can enable a low complex encoder implementation. The encoder and the decoder can be realized by using well-arranged shift registers. Such codes can provide a high net coding gain (NCG) and a low error floor.

A simple soft demodulation followed by an LDPC decoder can result in a penalty of approximately 2.7 dB compared to systems without differential encoding. Using iterative demodulation and decoding more than 2 dB gain can be achieved, e.g. in a QPSK - - modulation format. Irregular LDPC codes can achieve better performance with increased encoding and decoding complexity.

A QC-LDPC code is given by a null space of an array of sparse circulants of the same size. For two positive integers c and t with c<=t, the parity check matrix of QC-LDPC code is a cxf (c by t) array of kxk (k by k) circulants over GF(2). Each circulant is derived from a kxk identity matrix by an appropriate column shift. Such a code is regular since row weights are identical and equal to c and all row weights are equal to t. The parity matrix of a QC-LDPC code can be given by

Carefully designed regular codes can enable a high NCG, moderate code word lengths, and an acceptable error floor. Regular QC-LDPC codes can perform well in the absence of a differential encoder/decoder. Irregular codes can perform better with differential decoding and can compensate for more differential encoding penalties. On the other hand, irregular codes can be difficult for realization and can exhibit a high error floor. Without a differential encoder, their performance can be low. Hence, a compromising solution to fulfil specifications for both scenarios with and without differential encoding is desirable.

Even with a good FEC code design, inappropriate exchanging information between MAP and FEC decoders can cause an error floor. In practical MAP decoders, log probabilities can be used in path metric calculations. The MAP decoder can deliver a log-likelihood ratio for each bit or symbol to the subsequent FEC decoder. This information can be used in the FEC decoder that produces extrinsic information for the MAP decoder in the next decoding iteration step. Both the information from the MAP and from the FEC decoder can represent a posteriori probabilities (APP) in logarithmic domain. Since over iterations the APP can grow rapidly at a high signal-to-noise ratio, it should be limited due to complexity reasons. Normally a few bits can be used to quantize and/or represent these values, e.g. a six (6) bit quantization can - - be a good choice. Hence, the quantization circuit can serve as a limiter, i.e. when an absolute APP value crosses certain limits defined by a quantization resolution the value can be limited. The APP value limitation can depend on the applied decoding algorithms and the used decoding scenario. In differentially encoded systems, the decoding can be very specific. The differential encoder can be a non-systematic encoder with a code rate equal to 1. An MAP decoding using a trellis and a BCJR, a max-star or an SOVA scheme can be implemented. Due to complexity the original BCJR scheme is rarely used.

The received signal alone can be used in a first iteration step without a priori information from the FEC decoder. Noise can be supposed to be Gaussian so that the forward and backward calculations, e.g. through the trellis, can be done using simple log probabilities. The MAP output can be a log-likelihood ratio (LLR) that can have any value. This value may also be limited.

The aforementioned problem can be more emphasized in presence of a frequency offset and/or phase noise. A feed-forward carrier phase estimation and recovery scheme can be applied in optical coherent systems. Each cycle slip position can be more prone to errors than others. When inappropriate limiting is used, such locations can mostly contribute to an error floor generation.

An LDPC code can be used. Each bit can contribute in four (4) equations so that extrinsic information can comprise four (4) parts. The total extrinsic information can be limited to 128, e.g. as a quantized value. The MAP output information may not be limited. A differential encoder can be used for a QPSK signal. Laser phase noise and residual frequency offset can be added and a feed-forward carrier phase recovery can be used. Cycle slips can happen at least once in one code word. In this example, after a 10th iteration step, 3 errors are left and may not be eliminated by increasing the iteration step number. The errors can be shown in a plot with LLR coordinates for I and Q signal components. It can be observed that also others points can be regarded as suspicious.

Fig. 3 shows a schematic diagram of a turbo decoder 300 for decoding an input signal. - -

The turbo decoder 300 can be used as the decoding means 1 17 in the dual-polarization coherent optical receiver 100 as shown in Fig. 1 or as the FEC decoding means 215 in the transmission system 200 as shown in Fig. 2. The turbo decoder 300 for decoding an input signal comprises a first decoder 301 , a second decoder 303, a first limiter 305 arranged between the first decoder 301 and the second decoder 303, and a second limiter 307 arranged between the second decoder 303 and the first decoder 301. The turbo decoder 300 further comprises summation means 309, an adder 31 1 , a decider 313, a subtracting means 315, a deviation estimator 319, a multiplier 321 , and a determiner 323. The second limiter 307 can be configured to transmit an output 317 to the second decoder 303. The turbo decoder 300 can be configured to decode an input signal encoded with a forward error correction code.

The input signal can be a sampled and quantized communication signal. The input signal can be derived from an optical fiber communication signal.

The first decoder 301 can be configured to output information in the form of a log-likelihood ratio for each bit or symbol of the sampled and quantized communication signal. The first decoder 301 can further be configured to output information representing a posteriori probabilities (APP) in logarithmic domain.

The second decoder 303 can be configured to generate extrinsic information for the first decoder 301 from the output information of the first decoder 301 . The second decoder 303 can further be configured to output information representing APP in logarithmic domain. The first limiter 305 can be configured to limit the APP values determined by the first decoder 301.

The second limiter 307 can be configured to limit the extrinsic information determined by the second decoder 303. - -

The summation means 309 can be configured to provide a signal comprising extrinsic information for the first decoder 301 by summing up the output information signals of the second limiter 307. The adder 31 1 can be configured for adding output signals from the first limiter 305 and from the summation means 309.

The decider 313 can be configured for performing a hard decision upon the basis of the addition signal.

The subtracting means 315 can be arranged between the first decoder 301 and the first limiter 305. The subtracting means 315 can be configured to subtract the limited information of the second decoder 303 from the output of the first decoder 301 . The output 317 can be transmitted from the second limiter 307 to the second decoder 303.

The deviation estimator 319 can be configured to determine a standard deviation of the input signal and to provide the standard deviation to the first decoder 301 for MAP decoding. The multiplier 321 can be arranged between the second decoder 303 and the second limiter 307. The multiplier 321 can be configured to multiply an output of the second decoder 303 by an output of the deviation estimator 319.

The determiner 323 can be configured for determining a first limitation parameter for the first limiter 305 upon the basis of an output of the deviation estimator 319 and a first

predetermined parameter, and for determining a second limitation parameter for the second limiter 307 upon the basis of the first limitation parameter and a second predetermined parameter. The first decoder 301 (MAP decoder) can produce APP values based on an input signal and extrinsic information from the second decoder 303 (LDPC decoder). After subtracting extrinsic information of the second decoder 303 (LDPC decoder) from the output of the first decoder 301 (MAP decoder), the APP values can be limited by the first limiter 305 (limiter 2). The second decoder 303 (LDPC decoder) can use the limited information and previously generated limited extrinsic information to generate new extrinsic information for the first decoder 301 (MAP decoder). - -

According to an implementation form, both extrinsic information values forwarded to the first decoder 301 (MAP decoder) and to the decision block can be limited. The final decoding can use a limited output of the first decoder 301 (MAP decoder) and limited extrinsic information of the second decoder 303 (LDPC decoder).

The first limiter 305 (limiter 2) applied to the output of the first decoder 301 (MAP decoder) after subtraction of the extrinsic information of the second decoder 303 (LDPC decoder) can use the limiting value L2=n/s ² , where s represents a standard deviation of the input signal of the first decoder 301 (MAP decoder). In the case of QPSK, it can be enough to estimate the standard deviation of either the real or the imaginary part of the received signal. The standard deviation can be estimated in the deviation estimator 319 (standard deviation estimation block SDE). To improve the performance of iterative decoding, the standard deviation can be used in the first decoder 301 (MAP decoder). The standard deviation can also weight the extrinsic information of the second decoder 303 (LDPC decoder). The weighted extrinsic information of the second decoder 303 (LDPC decoder) can be limited by the second limiter 307 (limiter 1 ). The limiting value of the second limiter 307 (limiter 1 ) can be L1 =p/m=n/(ms ² ) where m<1 .

The limiters, e.g. the first limiter 305 and/or the second limiter 307, can be defined by their absolute limiting values. One can define a minimum column weight of an LDPC parity matrix by P. When P is greater than 1 , the parameter m can be set to 1 . Otherwise, this parameter can be less than 1 .

In an example, m=0.91 is set and a code with P=4 is used. The standard deviation is close to 0.5. A value of n=2.5 is selected and it follows that L1 =1 1 and L2=10 as non-quantized values wherein quantization is straightforward. For QPSK after the 6th iteration step no error is observed. The constellation made of LLRs after decoding is clear around the decision boundaries. The maximum absolute LLR value is equal to 4L1 +L2=54. In an implementation form, the invention relates to coherent optical receivers using enhanced digital signal processing including soft error correction codes and differential encoders.

In an implementation form, the invention relates to a scheme for error floor correction and performance improvement in differentially encoded systems using error correction codes. - -

In an implementation form, the invention relates to a method for improving the performance in differentially encoded systems using turbo demodulation.

In an implementation form, the invention relates to a method which limits a demodulator APP value that is free of any a priori information coming from other decoders. The limitation can enable lower complexity and error floor mitigation or avoiding, especially in the presence of frequency offset and/or phase noise that can be compensated by enhanced carrier phase recovery schemes. In an implementation form, the error correction code extrinsic information is limited according to the limiter used in the differential decoding step.

In an implementation form, a relationship between the limiters' parameters is defined providing a desired performance.

In an implementation form, the invention relates to a method which provides optimum parameters for a practical turbo demodulation system including limiter values and the weighting of extrinsic information. In an implementation form, the invention relates to a method for error floor suppression caused by uncontrolled APP growing in systems using turbo demodulation.

In an implementation form, the invention relates to a method for improving performance and decreasing complexity in differentially encoded systems.

In an implementation form, an influence of MAP weak log-likelihood information is suppressed which can enable an improved decoding after the LDPC decoder.