Title:
AN OR-TYPE MEMORIZING INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1998/025344
Kind Code:
A1
Abstract:
An OR-Type memorized integrated circuit, characterized that RS trigger and monostable trigger etc. are constituted by one OR gate instead of by two gates as in the prior art, and that the temporarily memorizing time of the monostable trigger can be controlled by timing level and oscillating frequency can be changed in a wide range, both of them are determined by timing level, resistor and capacitor. The BiMOS circuit disclosed in the present invention is of simple structure and has good performances. A fundamental new CMOS device having variety of functions is also provided by the present invention.
More Like This:
| JPH0832438 | HIGH OUTPUT IMPEDANCE INVERTER AND FLIP-FLOP USING IT AND PHASE MODULATOR |
| JPH03135109 | SEMICONDUCTOR DEVICE |
| JPS574616 | POWER-ON RESETTING CIRCUIT |
Inventors:
ZHANG ZONGXUE (CN)
Application Number:
PCT/CN1997/000138
Publication Date:
June 11, 1998
Filing Date:
December 03, 1997
Export Citation:
Assignee:
ZHANG ZONGXUE (CN)
International Classes:
H03K3/355; H03K19/0944; (IPC1-7): H03K3/353
Foreign References:
| EP0176211A1 | 1986-04-02 | |||
| EP0023127A1 | 1981-01-28 |
Attorney, Agent or Firm:
CCPIT PATENT AND TRADEMARK LAW OFFICE (2 Fuchengmenwai Street, Beijing 7, CN)
Download PDF: