Title:
UNIT SHIFT REGISTER CIRCUIT, SHIFT REGISTER CIRCUIT, METHOD FOR CONTROLLING UNIT SHIFT REGISTER CIRCUIT, AND DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/208123
Kind Code:
A1
Abstract:
Provided is a unit shift register circuit which constitutes each stage of a shift register circuit, and which includes: an output transistor (T1) in which a predetermined clock signal is input to the drain terminal, and which outputs an output signal (OUT) from the source terminal; and a setting transistor (T2), wherein the transistor (T2) is connected at the source terminal thereof to one gate electrode of the output transistor (T1), an input signal (S) is input to the drain terminal, and an input signal (VS) of higher voltage than the voltage of the input signal (S) is input to the gate electrode during charging of the gate electrode (node (VC)) of the output transistor (T1).
Inventors:
YAMAMOTO KAORU
OGAWA YASUYUKI
OGAWA YASUYUKI
Application Number:
PCT/JP2014/054517
Publication Date:
December 31, 2014
Filing Date:
February 25, 2014
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
G11C19/28; G09G3/20; G09G3/36; G11C19/00
Foreign References:
| JP2010250303A | 2010-11-04 | |||
| JP2011070761A | 2011-04-07 | |||
| JP2011199851A | 2011-10-06 | |||
| JP2003101406A | 2003-04-04 | |||
| JP2003242797A | 2003-08-29 | |||
| JP2003249848A | 2003-09-05 |
Attorney, Agent or Firm:
FUNAYAMA Takeshi et al. (JP)
Takeshi Funayama (JP)
Takeshi Funayama (JP)
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