Technical Field

The invention is related to a multi-port circuit creating simple structure realizations of circuits and circuit components which are theoretically defined, however do not have any realization or are implemented with complicated and costly structures, applied in electric/electronic, control, biomedical, computer engineering as well as other fields of engineering.

The invention is particularly related to a 4-port Mutator (Metamutator) which realizes various components such as universal filters, all pass filters, oscillators, gyrators, transimpedance/transconductance amplifiers and 2-terminal (1 -port) electronic circuit components such as memristor, memcapacitor, meminductor which constitute the basic blocks of receiver/transmitter structures in communication.

State of the Art

Especially dramatic reduction of device dimensions used in the electronic industry and the frequent appearance of new circuit components, systems require new realization techniques and methods. Some circuit elements which are defined theoretically with ease do not have a simple and cheap realization although they are very beneficial.

In the realization of components/systems such as universal filters, all pass filters, oscillators, transimpedance-transconductance amplifiers, memristors, memcapacitors, meminductors, rather complicated and crowded circuits are used for each of them separately and therefore, energy expenses increase.

In addition, a multi-port main block, which carries out various tasks by means of connecting 1 -2 components at its terminals, with the purpose of being used in the design and production of these realizations has not been considered before; therefore, neither a microstructure nor a realization is provided. Since no such multi-port hardware realization is present, simple and original realizations made using this multi-port have naturally not been set forth.

As a result, because of the problems mentioned above and the insufficiency of the present solutions on the matter, it has become necessary to make an improvement in the related technical field.

The Purpose of the Invention

With the invention, the 4-port block being the key concept, first level and blocks of the various original lower levels of this 4-port, as shown in Figure 1 from top down, having various original realizations for each level, and which solves the above listed problems has been made possible.

The developed 4-port Mutator (Metamutator) has been realized by means of various structures, the simplest containing 12 transistors. Universal filters, all pass filters, transimpedance/transconductance amplifiers, oscillators, gyrators, inverter circuits, 2- terminal (1 -port) electronic circuit components such as memristor, memcapacitor, meminductor which constitute the basic blocks of receiver/transmitter structures in communication have been realized with the 4-port without adding external components or with adding 1 -2 components. Original circuits have been designed for each of the listed applications. In brief, it was possible to fulfil many functions by making use of a single Integrated Circuit (IC) which can be used in many applications.

In order to realize the above purposes, the Metamutator circuit sub-block structure realized by means of Add and Subtract blocks is generally in the form of:

• a subtract circuit formed with at least six transistors and composed of an inverting amplifier and two level shifter blocks, giving at the output the difference of port 1 and port 2 voltages when one input voltage is applied to port 1 and the other to port 2. where there is a port 3 between one terminal of port 1 and one terminal of the output port,

• an adder circuit formed with at least 6 transistors and composed of two level shifters and an inverting amplifier block, giving the sum of port 1 and port 2 voltages at the output when one input voltage is applied to port 1 and the other input voltage to port 2, where there is a port 4 between one terminal of port 2 input and one terminal of the output port.

The structural and characteristic features and all the advantages of the invention will be understood more clearly from the figures given below and the detailed explanation written by making references to these figures; hence, the evaluation should be made by taking these figures and their detailed description into consideration.

Figures Illustrating the Invention

Figure 1 shows the reference directions of the currents and voltages used in the 4-port Mutator (Metamutator) describing relations (element defining relations).

Figure 2 is the schematic of the 4-port Mutator configuration created with 1 adder and 1 subtractor circuit blocks.

Figure 3.1 is the view of the adder circuit separated into blocks and realized at the transistor level.

Figure 3.2 is the view of the subtractor circuit separated into blocks and realized at the transistor level.

Figure 4 is the view of the level shifter circuit.

Figure 5 is the circuit diagram of the 4-port mutator, consisting of add-subtract circuits whose port connections are shown, at the transistor level.

Figure 6 is the realization of the memristor 1 -port composed of the 4-port mutator, a nonlinear resistor, a capacitor and an inductor.

Figure 7 is the realization of the meminductor 1 -port composed of the 4-port mutator, a resistor, a capacitor and a memristor.

Figure 8 is the view of the generalized-gyrator 2-port obtained from the 4-port mutator and two resistors.

Figure 9 is the view of the transconductance amplifier circuit composed of the 4-port mutator and a resistor.

Figure 10 is the view of the transimpedance amplifier composed of the 4-port mutator and a resistor.

Figure 11 is the view of the oscillator circuit created by feeding back the outputs of the 4-port mutator to its inputs. Figure 12 is the view of the universal filter and oscillator circuit having 4-port mutator, 3 resistors, 2 capacitors and 3 source entries. All filter functions such as low pass, high pass, etc. can be realized according to which source is activated.

Figure 13.1 shows the reference directions of the currents and voltages used in the defining relations of the adder circuit used in the invention and whose realization is an invention itself.

Figure 13.2 shows the reference directions of the currents and voltages used in the defining relations of the subtract circuit used in the invention and whose realization is an invention itself.

The drawings do not need to be absolutely scaled and the details which are not essential for understanding the invention have been neglected. Furthermore, the components which are identical to a large extent or at least, which have identical functions to a large extent are shown by the same number.

Description of the Part References

A. Adder circuit

S. Subtract circuit

L. Level shifter

I. Inverting amplifier

K1. Port 1

K2. Port 2

K3. Port 3

K4. Port 4

V _B : Supply voltage

Detailed Description of the Invention

In this detailed description, the preferred structures of the invention are described to enable better understanding of the subject of the invention only, and it should be considered that these structures are given so as not to limit the scope of the invention.

1.1 Main Block: 4-port Mutator (Metamutator) As the most important part of the invention which has been developed for the first time as a concept, the defining relations have been given in Figure 1 with the equations; it is completely original and its original realizations have been given at various stages in the sequel. When suitable components are connected to two of the ports, it behaves like a 2-port known as the Mutator in the literature: Moreover it performs many other functions, that the Mutator cannot, by means of other suitable terminations. Flence it is usable in many electrical and electronic applications.

1.2 Add-Subtract Realizations

Being composed of one add and one subtract, two integrated blocks in total, the realization of the blocks at the transistor level and the structure of the Metamutator are original. The internal structure of the add-subtract blocks will be given below, in Section

1 .3 in detail.

The Add 3-port circuit shown in Figure 13.1 gives the sum of the voltages at its inputs to its output, which means ½2= ½1 + Va2, whereas the Subtract circuit (S) in Figure 13.2 gives the difference of the voltages at its inputs to its output, that is I4i= ½1 - Vs2. The input currents of both blocks are zero, which means: I _ai =l _a2 =l _si =l _s2 =0.

When the “add-subtract” blocks are connected as shown in Figure 2, the given description connections of the Metamutator 4-port in Figure 1 are obtained by using the Kirchoff law:

V ₄ =-Vl, V3=V ₂ , h=k l2=l ₄ [1]

1.3 Realizations of Add-Subtract Blocks at Transistor Level

1.3.1 Realization of the Adder Circuit (A) with Transistors

In the NMOS transistor circuit, given in Figure 3.1 , which performs the add operation, Vi and 14 shows the input voltages and the addition of V _out = Vi + 1 shows the output voltage which is the sum of two input voltages. Since the circuit is realized with 6 transistors only, the number of transistors used is minimal. 14, VDD and 14s in Figure

3.1 show the voltages of the power supplies; the numerical values, the used technology and the transistor dimensions being given in Section 1.4.1 below. The transistors Mi and M ₂ in Figure 3.1 constitute a level shifter (L) circuit. The structures of the blocks in the adder circuit (A) realization are as follows: • a level shifter (L) consisting of two transistors, so that the port 1 (K1 ) voltage is connected to the gate and supply voltage (V _B ) with negative sign to the source of one of them, while twice the supply voltage (V _B ) is connected to the other’s gate,

• another level shifter (L) consisting of two transistors, giving the sum of port 1 (K1 ) and port 2 (K2) voltages with negative sign from the drain and source connection point at its output, wherein combined drain and source with voltage difference of the supply voltage (V _B ) and port 1 (K1 ) is connected to the gate of a transistor, and the port 2 (K2) voltage is given to the other’s gate and supply voltage (V _B ) with negative sign is given to its source,

• an inverting amplifier (I) consisting of two transistors where one of them operates as an active load and on the other hand, total voltages of port 1 (K1 ) and port 2 (K2) of drain and source is negatively connected to other transistor’s gate, gives the total voltages of port 1 (K1 ) and port 2 (K2) from the drain and source connection point.

Description of the Adder Circuit (A)

The output voltage, Vo, of the level shifter (L) in Figure 4 can be given with the Vo = V _a - Vi + Vss equality using Kirchoff voltage law where V _a is the gate voltage of Mi transistor, Vi is the gate voltage of M2 transistor, Vss is the supply voltage. This equality becomes the following equation in terms of the values in Figure 3.1 :

V ₀ = 2VB - VI - VB = VB - VI [2]

Likewise, M3 and M4 are a second level shifter (L) wherein M4 transistor takes the place of M2 transistor, M3 transistor takes the place of Mi transistor. If V _p = V0 - V2 - VB is written from Figure 3.1 and placed into [2] equality, equality [3] is found:

V _p = - Vi - V ₂ [3]

Finally, since transistors Ms and Me in the adder circuit given in Figure 3.1 constitute an inverting amplifier (I) whose gain is -1 , the output of the adder circuit (A) is obtained as Vout = -Vp = Vi + V2. The Ms transistor operates as the active load for Me in the inverter circuit. 1.3.2 Realization of the Subtract Circuit (S) with Transistors

In the NMOS transistor circuit shown in Figure 3.2 which carries out the subtraction, 14 and 14 show the input voltages and the difference between V _out = 14 - 1 shows the output voltage which is the difference between the two input voltages. The number of transistors used is minimal since the circuit is realized with 6 transistors only. The 14, VDD and 14s voltages in Figure 3.2 show the voltages supply source and the numerical values, the technology used and the transistor dimensions will be provided in the sub section 1.4.2. The block structures in the subtract circuit (S) realization is as mentioned below:

• an inverting amplifier (I) consisting of two transistors wherein one operates as an active load and the other which gives port 1 (K1 ) voltage applied to the gate of the other with inverse sign from the drain and source connection point.

• a level shifter (L) of which the sum of the supply voltage (V _B ) and the port 1 (K1 ) voltage from the drain and source connection point is taken, consists of two transistors wherein an inverse sign of port 1 (K1 ) voltage is given to one of the gates and a supply voltage with negative sign is provided to the source, twice the amount of supply voltage (V _B ) is given to the gate of the other transistor,

• a level shifter (L), which provides the voltage difference of port 1 (K1 ) and port 2 (K2) from the drain and source connection point as the output, consists of two transistors wherein the total of the supply voltage (V _B ) and the port 1 (K1 ) voltage on the drain and source connection is coupled to one of the gates, and a port 2 (K2) voltage is given to the gate and supply voltage (V _B ) with negative sign is given to the source of the other one.

Description of the subtract circuit (S)

The subtract circuit (S) contains the same sub circuits: an inverting amplifier (I) formed of Mb-Mb transistors, the sub circuits formed of M1-M2 transistors and M3-M4 transistors both operate as a level shifter (L). The output of the inverting amplifier (I) is - 14, the first level shifter (L) output is V _p = 2VB + 14 - 1 = 14 + 14 and the second level shifter (L) output is V _out = V _p - V2 - VB = Vi - 14 as assumed. 1.4 Add-Subtract Integrated Circuit Layouts

1.4.1 1ntegrated Circuit Layout of the Adder Circuit (A)

The transistor sizes have been given in Table 1 and the feed voltage values have been given in Table 2. The process parameters of the TSMC (Taiwan Semiconductor Manufacturing Company) 0.25 pm technology has been used for layout.

Table 1 : Adder Circuit (A) MOS dimensions Table 2: Supply Voltages

The circuit provided in Figure 3.1 formed of a minimal number of transistors such as six of the adder circuit (A) and the integrated circuit (IC) layout which has a size of approximately 30x13 pm2 are original realizations.

1.4.2 Integrated Circuit Layout of the Subtract Circuit

The transistor sizes have been given in Table 3 and the values of the feed voltage values have been provided in Table 4. The process parameters of the TSMC 0.25 pm technology has been used for layout.

Table 3: Subtract Circuit (S) MOS dimensions Table 4: Supply Voltages

The circuit provided in Figure 3.2 formed of a minimal number of transistors such as six of the subtract circuit (S) and the integrated circuit layout which has a size of approximately 30x13 pm2 are original realizations.

The 4-port mutator scheme formed of add-subtract transistor circuits in Figure 5 have been provided with internal original realizations of the add-subtract blocks. Flow the main block is formed by coupling the add-subtract blocks and dashed lines is shown. The basic operation principal is based on obtaining elements acting as oscillators, universal filters, amplifiers, gyrators, memristors, memcapacitors from the remaining ports after suitable elements are connected to some of the 4-ports.

1.5 Realizations Obtained by Ending the Ports

1.5.1 1 -Ports Obtained by Ending the Three Port

1.5.1.1 1-Port Memristor

As shown in Figure 6, when port 1 (K1 ) is ended with a capacitor, port 2 (K2) with an inductor, port 4 (K4) with a nonlinear resistor, the circuit becomes a 2-terminal and acts as a memristor at port 3 (K3) or in other words a memristor is realized.

1.5.1.2 1-Port Meminductor

As shown in Figure 7, when port 2 (K2) is ended with a capacitor, port 3 (K3) with a memristor, port 4 (K4) with a linear resistor, the circuit becomes a 2-terminal and acts as a meminductor at port 1 (K1 ), or in other words a meminductor is realized.

Table 5: 1 - Port Elements Obtained by Ending the 3 Ports of the Main Block

1.5.22-Ports obtained by Ending Two Ports

1.5.2.1 2-ports Gyrator

Generalized gyrator connections are obtained between the port 1 (K1 ) and port 2 (K2) current and voltages such as Vi=-R ₂ .h and V ₂ =Ri _. h, with the connection of R1 to port 2 (K2), and R2 to port 4 (K4) as shown in Figure 8. These equations can be written as a matrix as below.

If Ri = R ₂ = R is selected instead of different resistors, the equations becomes V _I =-FU ₂ and V2=R.h so that this is an expression for a known gyrator.

1.5.2.2 Transconductance Amplifier Realization

As shown in Figure 9, Vi=-R4.h or in other words h=-Vi/R ₄ is obtained if port 3 (K3) is kept as an open circuit, and port 4 (K4) is ended with R4 resistance and this shows a transconductance amplifier relationship between ports 1 and 4 (K1 , K4).

1.5.2.3 Transimpedance Amplifier Realization

As shown in Figure 10, V2=R3-h is obtained if port 4 (K4) is kept as an open circuit and port 3 (K3) is ended with R3 resistance and this shows a zero input current impedance amplifier between ports 1 and 2 (K1 , K2).

1.5.2.4 Quadrature Oscillator Circuit Realization

As shown in Figure 1 1 , if dashed line feedback connections are made, it can be seen that a sinusoidal oscillation is carried out by V _os and V _oa voltages with 90° phase difference at / frequency. In the frequency expression, the R ₀ a and

Ros show the output resistors of the transistors, C _a and C _s represent the leakage capacitance of the transistors.

1.5.2.5 Universal Filter and Oscillator Circuit

The output voltage expression of the 4-port that ends as shown in Figure 12 by voltage sources When port 1

(K1 ) ends with a resistor, port 4 (K4) with a capacitor, port 2 (K2) with a voltage source ( l / _s i) serially connected to a resistor, port 3 (K3) with parallel connection of the serially connected voltage source to the capacitor and a voltage source serially connected to a resistor, the circuit provides different filtering functions and these provide the realizations as listed in Table 6 respectively:

• a high pass if a voltage source is serially connected only to the resistor on the port 2 (K2), • a band pass if a voltage source is serially connected only to the resistor on the port 3 (K3),

• a low pass if a voltage source is serially connected only to the capacitor on the port 3 (K3),

• a stop band if the same voltage sources are serially connected only to the resistor on the port 2 (K2) and capacitor on the port 3 (K3),

• an all pass in the presence of the voltage sources that are serially connected to the resistor of port 2 (K2), the capacitor of port 3 (K3) and the resistor of port 3 (K3).

Table 6: Realized Filters