Title:
USE OF A JFET AS A FAILSAFE SHUTDOWN CONTROLLER
Document Type and Number:
WIPO Patent Application WO/2012/087615
Kind Code:
A3
Abstract:
Various embodiments disclose methods and systems for controlling operation of a regulator controller integrated circuit. The regulator controller integrated circuit may include a run input and a voltage supply input. A voltage supply, having an on state and an off state, may be coupled with the voltage supply input of the regulator controller integrated circuit. A JFET that has a source, a drain, and a gate may be present. The source of the JFET may be coupled with electrical ground. The drain of the JFET may be coupled with the run input of the regulator controller integrated circuit. The gate of the JFET may be coupled with the voltage supply. Such embodiments may disable a regulator unless a supply voltage is present without requiring a supply voltage for control circuitry.
Inventors:
SCHNEIDER LON (US)
Application Number:
PCT/US2011/064202
Publication Date:
April 10, 2014
Filing Date:
December 09, 2011
Export Citation:
Assignee:
ICC NEXERGY INC (US)
International Classes:
G05F1/613
Foreign References:
| US20100141233A1 | 2010-06-10 | |||
| US7643322B1 | 2010-01-05 | |||
| US20030208646A1 | 2003-11-06 | |||
| US6100678A | 2000-08-08 | |||
| US7564264B1 | 2009-07-21 | |||
| US7679340B2 | 2010-03-16 | |||
| US5627413A | 1997-05-06 | |||
| US20080048631A1 | 2008-02-28 | |||
| US20100039083A1 | 2010-02-18 | |||
| US7418605B1 | 2008-08-26 |
Attorney, Agent or Firm:
PANIAGUAS, John, S. (NWWashington, DC, US)
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