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Patent Searching and Data


Title:
USE OF LDPC BASE GRAPHS FOR NR
Document Type and Number:
WIPO Patent Application WO/2019/033422
Kind Code:
A1
Abstract:
An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

Inventors:
LADDU KEETH SALIYA JAYASINGHE (LK)
ZHANG YI (CN)
SUN JINGYUAN (CN)
Application Number:
PCT/CN2017/098135
Publication Date:
February 21, 2019
Filing Date:
August 18, 2017
Export Citation:
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Assignee:
NOKIA SOLUTIONS & NETWORKS OY (FI)
NOKIA SHANGHAI BELL CO LTD (CN)
NOKIA TECHNOLOGIES OY (FI)
International Classes:
H03M13/11; G06F11/10; H03M13/00
Foreign References:
CN101073205A2007-11-14
CN1731363A2006-02-08
US20020120890A12002-08-29
US20090106626A12009-04-23
CN102414991A2012-04-11
CN1825770A2006-08-30
Other References:
INTEL CORPORATION: "LDPC Coding Chain", 3GPP DRAFT
ERICSSON: "CRC Attachment for Code Block Group", 3GPP DRAFT
See also references of EP 3669460A4
Attorney, Agent or Firm:
KING & WOOD MALLESONS (CN)
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