ICs are built from single chips of semiconductor material. A single IC chip contains a number of electrical components, such as diodes, transistors and resistors, built in to the semiconductor material. Today, Very Large-Scale Integrated (VLSI) circuit chips contain hundreds of thousands of transistors and other components arranged in arrays and built directly onto the chip.

Interconnected chip components usually operate under a synchronization scheme in order to function properly. For example, a simple serial bank of flip-flop memory registers successively access and transfer data elements according to a predetermined clock cycle. For every active clock signal, each register turns on and performs a function, such as accessing information from a data source, storing the data, or transferring the data to the next register. Flip-flop memory circuits are just one example of interconnected components that operate under a synchronized environment according to a common clock signal.

Synchronized components on a chip are traditionally clocked from one clock source. A clock device, normally a separate oscillator chip or circuit, distributes timing signals to components on the chip from a single source input on the chip. The clock source is distributed to various locations around the chip by a system of signal lines.

Buffers or repeaters may be added depending on the number of locations to be clocked or their relative distances from the clock source.

A major problem affecting the synchronization of multiple components is clock skew. Skew is a relative timing deviation, either in phase or in frequency, between a given clock signal and a reference signal, usually the clock source.

One cause of clock skew is that the components that need to be clocked are located on the chip at varying distances from the clock source. Signal delay, a function of electrical path length, causes the clock signal to arrive at components near the clock source earlier than more distant components. Chip layout and design generally prohibits building equal-length signal lines from a common clock source. Clock signal buffers and repeaters, which require their own power source and control circuitry, also add delay to the distributed clock signal. Further, because they have inherently performance variances, it is infeasible to employ buffers and repeaters in an a scheme to equalize clock signals.

The trend is toward building larger VLSI semiconductor chips with many times more components, all of which are being operated under increasingly faster computing speeds. In faster computing systems, clock signal frequency increases, so that the time between successive clock cycles correspondingly decreases. Under this scenario, clock skew represents a significantly greater portion of shrinking clock cycle times. Therefore, what is needed is a more precise clock system to minimize skew to avoid disruptions in synchronized chip operations.

SUMMARY OF THE INVENTION The present invention is directed to distribution of a number of precisely synchronized clock signals at each of a plurality of locations on a chip. In one embodiment of a clock signal distribution system according to the present invention, a ring of control structures distributes clock signals to a number of locations on a chip. In effect, each location has a substantially identically timed clock signal source, although they might vary by a fixed, predetermined phase shift. Each control structure in the ring is associated with the previous control structure, which in turn is

associated with its predecessor, and so on. The signal delay between successive structures is substantially equal. The clock signal is input into one structure as it is output from the previous structure, thus oscillating the signal through the ring. A clock distribution node at each control structure outputs a local clock signal of substantially equal phase and frequency, with minimal skew.

According to a further aspect of the invention, the clock signals are distributed to a number of locations on a chip by a ring of asynchronous First-In, First-Out (FIFO) control circuits. The FIFO control circuits are asynchronous in that each FIFO control circuit is non-clocked, but the ring will oscillate the clock signal according to an initialization method which produces a synchronized output clock signal from each control circuit.

In another embodiment of a clock distribution system according to the present invention, each FIFO control structure is a pseudo-dynamic asP* [is there a better or more descriptive name?] control circuit. The configuration of the control circuit alternates from stage to stage, and the configuration pattern is repeated in equivalent, repetitive blocks. The configuration of each FIFO control structure will be discussed in further detail below.

In a third configuration of a clock distribution system according to the present invention, the control structures comprising the ring are micropipeline control circuitry. The micropipeline circuitry is arranged in double rail implementation where each signal has a true and complement version 180 degrees out of phase. The stages have identical signals at corresponding nodes within each stage.

According to a further aspect of the invention, in a ring of control structures, each control structure is associated with a previous control structure in the ring and a next control structure in the ring. Whenever a data transfer event occurs, such as a FIFO circuit's data register transitioning from high to low or low to high, the clock output node outputs a signal. Further, by phase-shifting or delaying the transition outputs, it is possible to have

multiples of clock outputs in-phase.

The clock distribution system according to the present invention produces synchronous clock signals with a unique configuration of asynchronous FIFO control circuits.

Because each stage is interdependent on both the stage immediately preceding and immediately following, clock signals transition through the ring in highly precise timing sequences. The result is a synchronized clock distribution technique that is far less prone to clock skew than traditional clock distribution systems.

A further understanding of the nature and advantages of the invention may be realized by reference to the remaining portions of the specification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a high-level schematic diagram of a system for distributing clock signals on a chip; FIG. 2 is a block diagram of a FIFO control circuit ; FIG. 3 is a block diagram of an asynchronous FIFO control ring; FIG. 4a is a schematic diagram of a pseudo-dynamic asP* FIFO control stage; FIG. 4b is a schematic diagram of a ring of pseudo- dynamic asP* FIFO control circuits; FIG. 4c is a schematic diagram of a pseudo-dynamic asP* FIFO control stage with series transistors added to control frequency; FIG. 4d is a schematic diagram of a static asP* FIFO control stage; FIG. 4e is a schematic diagram of a ring of static asP* FIFO control circuits; FIG. 5a is a schematic diagram of one alternative of a micropipeline FIFO control stage; FIG. 5b is a schematic diagram of an asynchronous FIFO control ring composed of stages of the first micropipeline FIFO alternative; FIG. 6a is a schematic diagram of a second SUBSTITUTE SHEET (RULE 26)

alternative of a micropipeline FIFO control stage; and FIG. 6b is a schematic diagram of an asynchronous FIFO control ring composed of stages of the second micropipeline FIFO alternative.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a high-level schematic diagram of a system for distributing clock signals on a chip 10. In a preferred embodiment, the chip 10 is a VLSI circuit chip, however, the clock distribution system according to the present invention can be used to distribute clock signals on any IC chip where one or more components operate under clock cycles. A ring 15 of control structures 20a-j is built into the semiconductor material of chip 10. The manufacture of IC chips with built- in circuit devices is well-known in the art, and will not be further described here.

Each of the control structures 20 in ring 15 has an input 30 and an output 35. The input of any one control structure 20 and the output of its immediate preceding control structure 20 is coupled by a signal line 25. Signal lines 25a-j are substantially equal in length and connect control structures 20 serially into a ring. Ring 15 is shown as a circle in FIG. 1, but it should be realized that ring 15 can take any form or shape as long as its control structures 20 are connected in series by signal lines 25. Furthermore, the number of control structures 20 shown in FIG. 1 is for purposes of example only. In the preferred embodiment of a clock distribution system of the present invention, there can be any number of control structures 20 built around chip 10.

Control structures 20 are strategically placed in a number of locations around chip 10. Each control structure 20 is associated with an immediate predecessor control structure and a next immediate control structure. For example control structure 20a is associated with predecessor control structure 20j and next control structure 20b. In this configuration, at any moment in time the present state of each control structure 20 is interdependent on the present state of all other control

structures 20. In the example, the output 35j of control structure 20j feeds the input 30a of control structure 20a, the output 35a of which feeds the input 30b of control structure 20b, etc.

A clock signal is placed on ring 15 by initializing control structures 20. Control structures 20 are initialized so that data elements (logic high and low signals) propagate through ring 15. Control structures 20 occupy one of two states: full (containing logic high and ready to shift out the logic high signal) or empty (logic low and ready to receive the logic high signal). In the present example of the first embodiment, control structure 20j is initialized full, control structure 20a is initialized empty, and control structure 20b is initialized full, repeating the initial pattern.

Control structure 20a, being empty, changes its state to full as it latches the data element from control structure 20j. Control structure 20j, in turn, changes its state to empty as it outputs its data element to the input 35 of control structure 20a, and then looks to its immediate predecessor for its next data element input. Control structure 20b also changes its state to empty as it outputs its data element to the next control structure 20 in the ring 15, and looks to the output 30 of control structure 20a for its next data element input. In this way control structures 20a-j oscillate between full and empty states. Each time any one control structure 20 changes its state a clock signal is output at clock distribution node 40. Clock distribution nodes 40 can output a local clock signal of substantially equal phase and frequency as other nodes in ring 15 depending on the combined signal delay of control structures 20 and signal lines 25.

FIG 2. is a block diagram of a First-In, First-Out ("FIFO") circuit 50 to aid in understanding of the control structures 20 shown in the general structure of ring 15 in FIG. 1. FIFO circuit 50 includes an input 115 and an output 120 and a series of control structures 20, which further comprise data registers 100 and control circuits 110. Data registers 100a-d store and move data through FIFO circuit 50

in one direction, as illustrated by the direction of the arrows on data lines 25a-d. Coupled to each data register is a control circuit 110a-d, to control the state of each associated data register 100a-d, respectively. Each pair of data register 100 and control circuit 110 makes up a control structure 20.

A FIFO circuit is so named because data put into an input of the FIFO is output in the same order it is received.

FIFO circuits are made up of stages. As described above, a stage can either be"full" (contain a logic high) or it can be "empty" (contain a logic low). The concepts of full and empty and their importance in FIFO circuit operation is more fully explained in the following description.

The FIFO circuit 50 of FIG. 2 is shown having four FIFO stages 20a-d. In each FIFO stage 20, control circuits 110a-d monitor memories 100a-d, and set the memories'state as being"empty"and ready to receive data, or"full"and ready to transfer out data, depending on the memories'present state. The logic for moving data along FIFO circuit 11 from one stage to another is: 1) transfer data from a full stage to the next empty stage, 2) set the empty control state to full; and 3) set the full control state to empty. To function properly, somewhere along the FIFO circuit 50 a full stage must precede an empty stage, so that the data element in the full stage can transition out and nearly simultaneously enter the empty stage.

In general, FIFO circuits may either be clocked (synchronous) or non-clocked (asynchronous). A clocked FIFO memory has a clock circuit distributed to each of its separate circuits, and each operates in lock-step according to clock cycles received from an external circuit or source. An asynchronous FIFO circuit is not clocked. Rather, a data transfer operation is a localized communication between successive stages. Each stage operates at its own pace using control information from adjacent stages. By being free of waiting for a clock pulse to transfer data and reset the stage, the data transfer speed of an asynchronous FIFO circuit is basically limited by two factors: the transfer speed of the

individual circuits, and the particular state of all stages in a circuit at any particular moment in time.

Data in an asynchronous FIFO memory moves through empty stages until stopped by a full stage. A full stage will not transition to empty until the next stage ahead of it is empty. Thus, the data transfer speed of each individual FIFO stage 20 is dependent on the time required for the individual registers and their control elements to sense the present state of each register as either full or empty, and then move the data accordingly.

Returning to FIG. 2, when input 115 has a data element ready to be transferred into memory 100a, input 115 checks the status of control circuit 110a. If control circuit 110a indicates memory 100a is empty, input 115 transfers the data element to memory 100a and control circuit 110a changes its state to indicate that memory 100a is now full. Control circuit 110a next checks for the state of memory 100b by communicating with control circuit 110b. If memory 100b is full, control circuit 110b will indicate to control circuit 110a that memory 100b cannot receive the data element currently stored in memory 100a. When memory 100b is empty, control circuit 110b indicates to control circuit 100a that memory 110b is ready to receive a next data element from memory 100a. Control circuit 110b will change its state again to indicate that memory 100b has transferred the data element it momentarily stored, and is currently in empty state.

FIG. 3 is a block diagram of a FIFO control circuit 50 shown in FIG. 2 formed into a FIFO control ring 300, according to the present invention. In control ring 300 input 115 and output 120 from FIG. 2 are removed and the stages 20 are connected in a ring 300. Each stage 20 in FIFO control ring 300 has a clock output 130. Clock outputs 130a-d are shown in FIG. 3 as being coupled to memories 100a-d, respectively. This is simply to illustrate that a clock signal may be fed to an output from any point in the FIFO control ring 300 where a data element transition occurs. The clock output 130 outputs a signal when the structure to which it is attached transitions from low to high voltage, or from

high to low voltage.

FIFO control ring 300 operates substantially the same as the ring 50 of control stages 20 illustrated in FIG 1.

Data elements move from one data register to the next as long as the next immediate data register in the ring is empty. Not shown in FIG. 3 is a circuit for initializing data registers 100 so that the ring circuitry 300 can oscillate, or transition data elements around FIFO control ring 300. For transitioning to occur, all of the control structures 20 in FIG. 3 should neither be initialized completely full nor completely empty, so that at some point in the FIFO control ring 300, adjacent stages can transition their respective states.

FIG. 4a is a schematic diagram of a pseudo-dynamic asP* FIFO control stage 20 in the preferred embodiment of the present invention. FIFO circuits use combinational circuitry.

They rely on sequential logic circuits having a memory characteristic where the circuit's output is dependent not only on the current input conditions but also on the current output state of the circuit. The primary building block in combinational circuits is the logic gate. Complimentary metal oxide semiconductor (CMOS) technology is one example of an IC switching logic used in modern first-in first-out (FIFO) digital systems.

The MOSFET switch is essentially turned off and has a very high channel resistance by applying the same potential to the gate terminal as the source. An n-channel MOSFET is turned on and has a very low channel resistance when a high voltage with respect to the source is applied to the gate. A p-channel MOSFET operates in the same fashion, but with opposite polarities-the gate must be more negative than the source to turn on the transistor. When a HIGH logic level is applied to the input of a PMOS, it will be turned OFF. A HIGH logic level applied to an NMOS transistor will turn it ON.

In the preferred embodiment shown in FIG. 4a, control stage 20 contains two asynchronous pseudo-dynamic asP* FIFO control circuits 410 and 420. Control circuit 410 is shown with NOR gate 430 and inverter 435. The source nodes of

PMOS transistors 440 and 445 are connected to power supply Vdd. The drain node of PMOS transistor 440 is connected to one input of NOR gate 430 as well as the output 401 of a previous control structure 20. The drain node of PMOS transistor 445 is connected to a second input of the NOR gate 430 as well as the input to control circuit 420. The gates of PMOS transistors 440 and 445 are connected to the output of inverter 435.

Control circuit 420 is shown with NAND gate 450 and inverter 455. Transistors 460 and 465 are NMOS transistors, and their drain nodes are connected to a common ground node.

The source node of NMOS transistor 460 is connected a first input to NAND gate 450 as well as to the drain node of PMOS transistor 445, or node 402. The source node of NMOS transistor 465 is connected to a second input to NAND gate 450 as well an input 403 of a next control stage 20. The gates of NMOS transistors 460 and 465 are coupled to the output of inverter 455.

In order for the stage shown in FIG. 4a to oscillate correctly, nodes 401,402 and 403 of control stage 20 must be initialized so that they are neither all full nor all empty at the same time. To illustrate, nodes 401,402 and 403 are assigned with initial values of low, high, and high, corresponding to states of Full, Full and Empty, respectively.

Since the values at the input of NOR gate 430 are low and high, the output of inverter 435 will be high, causing a high signal to be applied to the gates of PMOS transistors 440 and 445, placing them in an"off"state. Likewise, since the values at the input of the NAND gate 450 are both high, the output of inverter 455 will be high, causing a high signal to be applied to the gates of the NMOS transistors, placing them in an"on"state. Now nodes 401,402 and 403 exhibit the respective states of Full, Empty, and Full. Thus, the Full condition at node 402 has moved to node 403, leaving node 402 in an Empty state. The data values associated with the states will continue to flow through each control structure only if Empty nodes are available to hold them.

FIG. 4b is a circuit diagram of clock distribution

ring 400 using the asynchronous FIFO control structures discussed from FIG. 4a. In the preferred embodiment shown in FIG. 4b, FIFO control stage 20 from FIG. 4a is repeated five times, alternating between the FIFO control circuit 410 and FIFO control circuit 420, described above. The FIFO control ring having five stages is shown for purposes of example only.

It should be understood that a ring may be formed by serially connecting any number of stages 20 depending on the size of the chip and the desired number of clock output nodes.

Each pair of control circuits 410 and 420 form a stage 20, also described above. Each control stage 20 exhibits a phase delay of the same magnitude of a clock signal oscillating around FIFO ring 400. For example, when control ring 400 is initialized half full, all nodes labelled the same are in-phase. Nodes labelled"a"are 120 out of phase with nodes labelled"b"and"c"which in turn are also 120 degrees out of phase. Thus, a clock distribution node may be tapped off from any like-labelled node for a synchronous clock output. The asynchronous FIFO control ring 400 can be built to generate any number of phases, depending on the number of stages 510.

FIG. 4c shows an alternative circuit of the preferred embodiment according to the present invention.

Control circuits 410 and 420, similar to those shown in FIG.

4a, make up control stage 20. In this alternative embodiment, control circuit 410 has PMOS transistors 470 and 475 connected in series with PMOS transistors 440 and 445, respectively.

Likewise, control circuit 420 has NMOS transistors 480 and 485 connected in series with NMOS transistors 460 and 465, respectively.

The additional series transistors to the control structures 410 and 420 allow the frequency of FIFO control stage 20 to be controlled. For example, to match the frequency of a clock distribution ring to an off-chip oscillator, the gates of the additional series transistors may be connected to an analog input. The analog voltage may be adjusted to limit the current passing through these transistors and therefore limit the frequency at which the

FIFO control ring, made of stages 20 from FIG. 4b, can oscillate.

FIG. 4d is a schematic diagram of an alternative circuit of the preferred embodiment. The stage shown in FIG.

4d is a static asP* FIFO control. [How is the static asP* functionally different from the pseudo-dynamic asP*?] FIG. 4e is a schematic diagram of a FIFO control ring using the static asP* alternative control stage. The FIFO control ring 490 is initialized half full by setting the nodes labelled"a"to low and the nodes labelled"b"to high.

All of the nodes labelled"a"will be in phase with each other and 180 degrees out of phase from the nodes labelled In a second embodiment of the present invention, the control stages can be made of micropipeline control structures. FIG. 5a is a schematic diagram of one alternative of a micropipeline FIFO control stage according to the second embodiment of the present invention. Micropipeline control circuit 700 is event-controlled, meaning that the circuit oscillates without processing and instead relies on transition events in adjacent circuits. [How do the micropipeline circuits generally work?] FIG. 5b is a schematic diagram of an asynchronous FIFO control ring composed of multiple stages of the first alternative micropipeline control structure shown in FIG. 5a.

FIFO control ring 510 is a double rail implementation, with true and complement signals which are 180 degrees out of phase with each other. The control ring 510 is intitialized half full when the nodes labelled"a"and"b"are initialized low and the nodes labelled"c"and"d"are initialized high.

There is a 90 degrees phase shift between adjacent stages.

All nodes with the same label are in phase.

FIG. 6a is a schematic diagram of an alternative micropipeline control stage according to the second embodiment of the present invention.

FIG. 6b is a schematic diagram of an asynchronous FIFO control ring composed of multiple, replicated stages of the second micropipeline FIFO alternative. The FIFO control

ring 610 is initialized half-full when the nodes labelled"a" and"b"are initialized low and the nodes labelled"c"and"d" are initialized high. There is a 90 degrees phase shift between adjacent stages. All nodes with the same label are in-phase with each other.

The above description explains how to make and use several preferred embodiments of a system for generating and distributing precisely synchronized clock signals on a chip according to the present invention. While the above is a complete description of the preferred embodiments of the invention, various alternatives, modifications, and equivalents may be used. For example, other FIFO circuits may be used in the control stages of the FIFO ring. Further, the number of stages comprising a ring may vary depending on the desired number of clock output nodes or size of the chip.

Therefore, the above description should not be taken as limiting the scope of the invention which is defined by the appended claims.