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Title:
VARIABLE RESISTANCE MEMORY
Document Type and Number:
WIPO Patent Application WO/2016/042880
Kind Code:
A1
Abstract:
A variable resistance memory according to one embodiment of the present invention is provided with: a semiconductor layer (AA1); a gate electrode (27) that covers the upper surface and the lateral surface of the semiconductor layer (AA1); a first conductive line (SLj) that is connected to a first end of the semiconductor layer (AA1); a variable resistance element (MTJ) that is connected to a second end of the semiconductor layer (AA1); a second conductive line (BLj) that is connected to the variable resistance element (MTJ); and a third conductive line (WLi) that is connected to the gate electrode (27). The first and second conductive lines (SLj, BLj) are arranged between the semiconductor layer (AA1) and the third conductive line (WLi).

Inventors:
TANAKA CHIKA (JP)
NOGUCHI HIROKI (JP)
FUJITA SHINOBU (JP)
Application Number:
PCT/JP2015/068824
Publication Date:
March 24, 2016
Filing Date:
June 30, 2015
Export Citation:
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Assignee:
TOSHIBA KK (JP)
International Classes:
H01L21/8246; H01L27/105; H01L29/82; H01L43/08
Foreign References:
JP2012019105A2012-01-26
JP2009164319A2009-07-23
JP2005277189A2005-10-06
Attorney, Agent or Firm:
S & S International PPC (JP)
Patent business corporation スズエ international patent firm (JP)
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