VARISTOR-FUNCTION-EQUIPPED STACKED SEMICONDUCTOR CERAMIC CAPACITOR AND MANUFACTURING METHOD FOR SAME

WIPO Patent Application WO/2015/072277

A1

A varistor-function-equipped stacked semiconductor ceramic capacitor comprises a component element (4), in which a plurality of semiconductor ceramic layers (1a to 1g) which are formed with a SrTiO3-type grain boundary insulated semiconductor ceramic, and a plurality of internal electrode layers (2a to 2f), are alternately stacked and sintered. For the semiconductor ceramic, average particle size of crystal particles is less than or equal to 1.0 μm, and a coefficient of variation indicating particle size unevenness of the crystal particles is less than or equal to 30%. The stacked semiconductor ceramic capacitor is fabricated by weighing predetermined amounts of a Sr compound, a Ti compound, and a donor compound, mixing and pulverizing the same, fabricating a calcined powder, introducing a dispersant together with an acceptor compound and wet mixing the same, subsequently fabricating a thermally treated powder, slurrying the thermally treated powder and filter-processing the same, and using the filter-processed slurry. As a result, it is possible to achieve a varistor-function-equipped stacked semiconductor ceramic capacitor which can suppress reduction of insulation properties even if ESD repeatedly occurs and secure desired electrical characteristics and which is superior in durability, as well as a manufacturing method for same.

KAWAMOTO MITSUTOSHI (JP)

PCT/JP2014/077584

May 21, 2015

October 16, 2014

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MURATA MANUFACTURING CO (JP)

H01G4/12; H01B3/12; H01G4/30

WO2009001690A1	2008-12-31
WO2012017967A1	2012-02-09
WO2013039045A1	2013-03-21

JP2004284897A	2004-10-14
JPH0521266A	1993-01-29
JP2007173714A	2007-07-05

KUNIHIRO YASUTOSHI (JP)
Kunihiro Yasutoshi (JP)

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