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Title:
VCO WITH LINEAR GAIN OVER A VERY WIDE TUNING RANGE
Document Type and Number:
WIPO Patent Application WO/2015/017307
Kind Code:
A1
Abstract:
An oscillating circuit with linear gain is presented. The oscillating circuit may include a relaxation oscillator and a current compensation block. The relaxation oscillator includes a capacitor, a pair of resistors operative to deliver a first current to the capacitor, and a first current source adapted to generate the first current having a first predefined level. The current compensation block includes a second current source, and a pair of cross-coupled transistors coupled to the second current source and adapted to steer a current exceeding the first predefined level in the relaxation oscillator away from the capacitor and to the second current source. The proposed oscillating circuit generates an output signal which has a linear gain over a wide tuning range.

Inventors:
SWAMINATHAN, Ashok (5775 Morehouse DriveSan Diego, California, 92121-1714, US)
GALTON, Ian (5775 Morehouse DriveSan Diego, California, 92121-1714, US)
Application Number:
US2014/048361
Publication Date:
February 05, 2015
Filing Date:
July 28, 2014
Export Citation:
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Assignee:
QUALCOMM INCORPORATED (5775 Morehouse DriveSan Diego, California, 92121-1714, US)
International Classes:
H03B5/24; H03K3/282
Foreign References:
US6201450B12001-03-13
US8207763B12012-06-26
US7315220B12008-01-01
Other References:
SANTIN E ET AL: "Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs", IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. ISCAS 2010 - 30 MAY-2 JUNE 2010 - PARIS, FRANCE, IEEE, US, 30 May 2010 (2010-05-30), pages 1927 - 1930, XP031725237, ISBN: 978-1-4244-5308-5
Attorney, Agent or Firm:
BINDSEIL, James J. et al. (Arent Fox LLP, 1717 K Street N, Washington District of Columbia, 20036, US)
Download PDF:
Claims:
WHAT IS CLAIMED IS:

1. An oscillating circuit, comprising:

a relaxation oscillator comprising:

a capacitor;

a pair of resistors operative to deliver a first current to the capacitor; and

a first current source adapted to generate the first current having a first predefined level; and

a current compensation block comprising:

a second current source; and

a first pair of cross-coupled transistors coupled to the second current source and adapted to steer a current exceeding the first predefined level in the relaxation oscillator away from the capacitor and to the second current source.

2. The oscillating circuit of claim 1, wherein said relaxation oscillator further comprises:

a second pair of cross-coupled transistors forming a comparator.

3. The oscillating circuit of claim 2, wherein

a first transistor of the second pair of cross-coupled transistors has a source terminal coupled to a first terminal of the capacitor, a gate terminal coupled to a first terminal of a second one of the resistors and a drain terminal coupled to a first terminal of a first one of the resistors; and

a second transistor of the second pair of transistors has a source terminal coupled to a second terminal of the capacitor, a gate terminal coupled to the first terminal the first resistor and a drain terminal coupled to a first terminal of the second resistor.

4. The oscillating circuit of claim 1, wherein said current compensation block is adapted to maintain a voltage across the capacitor to a value defined by a resistance of the pair of resistors and the first predefined current level.

5. The oscillating circuit of claim 1, wherein the first pair of cross- coupled transistors in the current compensation block comprises

a first transistor having a source terminal coupled to the second current source, a drain terminal coupled to a first terminal of a first one of the resistors and a gate terminal coupled to a first terminal of a second one of the resistors, and

a second transistor having a source terminal coupled to the second current source, a gate terminal coupled to the first terminal of the first resistor and a drain terminal coupled to the first terminal of the second resistor.

6. The oscillating circuit of claim 1, wherein second terminals of the pair of resistors are coupled to a supply voltage.

7. A method for linearizing output of a relaxation oscillator, comprising:

delivering a first component of a current having a value up to a predefined level to a capacitive element disposed in the relaxation oscillator; and

steering a second component of the current exceeding the predefined level away from the capacitive element.

8. The method of claim 7, further comprising:

coupling a first pair of cross-coupled transistors to the capacitive element.

9. The method of claim 8, further comprising:

comparing a voltage across the capacitive element with a predefined value using the first pair of cross-coupled transistors.

10. The method of claim 7, further comprising:

maintaining a voltage across the capacitive element to a value defined by a resistance of a resistor disposed in the relaxation oscillator and the first predefined current level.

11. The method of claim 7, wherein steering a second component of the current exceeding the predefined level away from the capacitive element comprises: coupling a second pair of cross-coupled transistors to the relaxation oscillator; and

steering the second component of the current exceeding the predefined level through the second pair of cross-coupled transistors.

12. The method of claim 7, wherein the second component of the current is smaller than the first component of the current.

13. The method of claim 7, further comprising:

generating an oscillating output signal using the relaxation oscillator.

14. An apparatus for linearizing output of a relaxation oscillator, comprising:

means for delivering a first component of a current having a value up to a predefined level to a capacitive element disposed in the relaxation oscillator; and

means for steering a second component of the current exceeding the predefined level away from the capacitive element.

15. The apparatus of claim 14, further comprising:

means for coupling a first pair of cross-coupled transistors to the capacitive element.

16. The apparatus of claim 15, further comprising:

means for comparing a voltage across the capacitive element with a predefined value using the first pair of cross-coupled transistors.

17. The apparatus of claim 14, further comprising:

means for maintaining a voltage across the capacitive element to a value defined by a resistance of a resistor disposed in the relaxation oscillator and the first predefined current level.

18. The apparatus of claim 14, wherein the means for steering a second component of the current exceeding the predefined level away from the capacitive element comprises: means for coupling a second pair of cross-coupled transistors to the relaxation oscillator; and

means for steering the second component of the current exceeding the predefined level through the second pair of cross-coupled transistors.

19. The apparatus of claim 14, wherein the second component of the current is smaller than the first component of the current.

20. The apparatus of claim 14, further comprising:

means for generating an oscillating output signal using the relaxation oscillator.

Description:
VCO WITH LINEAR GAIN OVER A VERY WIDE TUNING RANGE

CLAIM OF PRIORITY

[0001] The present Application for Patent claims priority to U.S. Non-Provisional Application No. 13/954,277 entitled "VCO WITH LINEAR GAIN OVER A VERY WIDE TUNING RANGE" filed July 30, 2013, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.

BACKGROUND

[0002] The present disclosure relates to electronic circuits, and more particularly to voltage controlled oscillators (VCOs).

[0003] A voltage controlled oscillator (VCO) is an electronic oscillator whose oscillation frequency is controlled by a voltage input. The input voltage may determine the instantaneous oscillation frequency. A VCO may also be connected to a phase- locked loop (PLL) circuit. In general, oscillators can be designed with a very large frequency range. However, oscillator gain tends to be nonlinear across the whole frequency range. For example, an LC VCO (in which L represents an inductor and C represents a capacitor) could have up to lOx change in VCO gain over a 3x frequency range. Similar issues may arise in ring oscillators. VCO gain may also be sensitive to variations in process, voltage and temperature (PVT). It should be noted that wide variations in VCO gain may lead to variations in PLL bandwidth which may result in large jitter variations over PLL range.

[0004] Techniques are known in the art to compensate the nonlinearities in the VCO gain, such as gain estimation and correction for digital PLLs (also known as Veyron PLL), matching VCO gain variations with charge pump current variations (e.g., in replica biased ring oscillators), and the like. However, these techniques may rely on correction of the nonlinearities in the VCO output in the PLL. It is therefore desirable to implement VCOs with linear gain over a very wide tuning range. SUMMARY

[0005] An oscillating circuit, in accordance with one embodiment of the present invention includes, in part, a relaxation oscillator and a current compensation block. The relaxation oscillator may include, in part, a capacitor, a pair of resistors operative to deliver a first current to the capacitor, and a first current source adapted to generate the first current having a first predefined level. The current compensation block includes, in part, a second current source, and a first pair of cross-coupled transistors coupled to the second current source and adapted to steer a current exceeding the first predefined level in the relaxation oscillator away from the capacitor and to the second current source.

[0006] The first pair of cross-coupled transistors in the current compensation block include, in part, a first transistor having a source terminal coupled to the second current source, a drain terminal coupled to a first terminal of a first one of the resistors and a gate terminal coupled to a first terminal of a second one of the resistors, and a second transistor having a source terminal coupled to the second current source, a gate terminal coupled to the first terminal of the first resistor and a drain terminal coupled to the first terminal of the second resistor.

[0007] In one embodiment, the oscillating circuit further includes a second pair of cross-coupled transistors forming a comparator. A first transistor of the second pair of cross-coupled transistors has a source terminal coupled to a first terminal of the capacitor, a gate terminal coupled to a first terminal of a second one of the resistors and a drain terminal coupled to a first terminal of a first one of the resistors. A second transistor of the second pair of transistors has a source terminal coupled to a second terminal of the capacitor, a gate terminal coupled to the first terminal the first resistor and a drain terminal coupled to a first terminal of the second resistor.

[0008] In one embodiment, the compensation block is adapted to maintain a voltage across the capacitor to a value defined by a resistance of the pair of resistors and the first predefined current level.

[0009] A method for linearizing output of a relaxation oscillator, in accordance with one embodiment of the present invention includes, in part, delivering a first component of a current having a value up to a predefined level to a capacitive element disposed in the relaxation oscillator, and steering a second component of the current exceeding the predefined level away from the capacitive element.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 illustrates a block diagram of a digital circuit, in accordance with certain embodiments of the present disclosure.

[0011] FIG. 2 illustrates an example schematic diagram of an oscillating circuit having a linear gain over a wide frequency range, in accordance with certain embodiments of the present disclosure.

[0012] FIG. 3 illustrates an exemplary set of voltage waveforms of selected nodes in the example schematic diagram of the oscillating circuit as illustrated in FIG. 2, in accordance with certain embodiments of the present disclosure.

[0013] FIG. 4 illustrates an exemplary flowchart for generating an oscillating signal with a linear gain over a wide frequency range, in accordance with certain embodiments of the present disclosure.

[0014] FIG. 5 illustrates an example computing system in which one or more aspects of the disclosure may be implemented.

DETAILED DESCRIPTION

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0016] For circuit elements known as Voltage-Controlled Oscillators (VCOs), the voltage-frequency gain is very critical. The voltage-frequency gain directly affects bandwidth of a phase lock loop (PLL), which in turn affects the integrated noise or jitter of the PLL. In most LC and ring oscillator structures, VCO gain may vary by an order of magnitude over process- voltage and temperature (PVT) variations and tuning range. The tuning range refers to the difference between minimum and maximum frequencies that are supported by the VCO.

[0017] In general, design of relaxation oscillators or VCOs may involve adjusting the current, resistive load and capacitor values. Typically, these methods will only result in a constant VCO gain characteristic over a very small frequency range relative to the oscillator frequency. Therefore, the oscillator may illustrate nonlinear behavior in other frequencies.

[0018] Nonlinearities in the VCO gain over larger frequency ranges may be compensated using different methods. For example, PLL parameters may be adjusted based on estimated gain of the VCO. Another method may be cancelling out gain variations in the VCO using adaptive biasing of the VCO and charge pumps (CPs). However, these methods may be costly in hardware. Certain embodiments of the present disclosure propose a method for designing a VCO with linear gain over a wide tuning range.

[0019] FIG. 1 illustrates a block diagram of a digital circuit 100, in accordance with certain embodiments of the present disclosure. Generally, the digital circuit may be part of digital device such as cellphones, base stations, computers, etc. The digital circuit may include a digital clock generator 102 which is connected to a digital logic (e.g., a CPU) 110 through a buffer 108. The digital clock generator may include a PLL 104, a VCO 106 and a buffer 108. The PLL and the VCO may generate a digital clock and send it to the digital logic 110 through a digital clock route. In general, the VCO may be a relaxation oscillator, such as an RC relaxation oscillator, in which R represents a resistor and C represents a capacitor. Relaxation oscillators are well known and are also commonly referred to as Schmitt trigger, RC oscillator, or multi vibrator.

[0020] For certain aspects, in an RC relaxation oscillator or any other type of relaxation oscillators, a constant or nearly constant VCO gain over a wide tuning range may be achieved by connecting a parallel cross-coupled differential pair of transistors to the oscillator load. As a result, frequency tuning in the oscillator may be achieved by reducing current in the core of the relaxation oscillator, and simultaneously (or near simultaneously) increasing the current in the cross-coupled differential pair by substantially equal amounts.

[0021] FIG. 2 illustrates an example schematic diagram of an oscillating circuit 200 having a linear gain over a wide frequency range, in accordance with certain embodiments of the present disclosure. Oscillating circuit 200 is shown as including an oscillator 210 and a current compensating block 230. Oscillator 210 may be a conventional relaxation oscillator, which may include resistors 212, 214, transistors 216, 218, 220, 222, and current source 224.

[0022] Relaxation oscillator 210 operates as described below. Transistors 216, 218 operate as a comparator thereby enabling current to flow from either node Ni (shown as having voltage Vi) to node N 2 (shown as having voltage Vi) via capacitor 226, or from node N 2 to node Ni via capacitor 226. As illustrated, the source terminal of the transistor 216 is connected to the drain terminal of transistor 222 and one of the terminals of the capacitor 226; the gate terminal of transistor 216 is connected to the resistor 214 and the drain terminal of the transistor 218; and the drain terminal of the transistor 216 is connected to the gate terminal of the transistor 218 and one of the terminals of the resistor 212.

[0023] FIG. 3 illustrates an exemplary set of voltage waveforms 300 of selected nodes in the example schematic diagram of the oscillating circuit 200, in accordance with certain embodiments of the present disclosure. Referring to FIGs. 2 and 3 concurrently, it is seen that, for example, when voltage V 2 ramps down, voltage Vi remains constant until V 2 reaches a predefined value at which point transistor 218 turns on, in turn causing V 2 to remain at a constant level. During the next cycle, Vi ramps down while V 2 remains constant. The ramp-down of Vj continues until Vj reaches a predefined value (e.g., -V c ) at which point transistor 216 turns on, in turn causing Vi to remain at a constant level.

[0024] In a conventional relaxation oscillator and in the absence of current compensation block 230, the amount of voltage drop at node N 2 (or Ni) required to cause transistor 218 (or 216) to turn on may be defined by * R L , where ias is a fixed current that is supplied by the current source 224, ΔΙ is a variable current that flows through current source 224 during switching, and R L represents value of the resistors 212 and 214. It should be noted that the current source 224 supplies both hi as and -ΔΙ currents. Alternatively, the current source 224 may be replaced by two separate current sources, one supplying a fixed current luas and the other supplying the current ΔΙ. In addition, the voltage input in a voltage controlled oscillator or a relaxation oscillator may be converted to current using a voltage to current converter. As an example, the voltage input may be converted into ΔΙ. [0025] The amount by which voltages Vi and V 2 have to ramp down in order for the oscillations to occur determines the oscillation frequency. As is well known, the relaxation oscillator 210 has a nonlinear gain over a wide frequency range.

[0026] It should be noted that in a more general oscillating circuit, transistors 220 and 222 may be removed from the example schematic diagram of FIG. 2, and the current source may be replaced with two current sources of magnitude Ibias-ΔΙ connected to the source terminals of 216 and 218.

[0027] Current compensation block 230 is adapted to maintain voltages Vi and V 2 within upper and lower bounds of +V C and—V c . For example, as Vj remains constant, voltage V 2 varies from +V C to—V c . Similarly, as remains constant, voltage Vj varies from +V C to— V c . In accordance with the present invention, voltages +V C are determined

[0028] As is seen from FIG. 3, the current compensation block 230 includes a pair of cross-coupled transistors 232, 234-that are coupled to resistors 212, 214-and a current source 236 adapted to supply and/or absorb current Δ/. Therefore, any current in excess of ia that may be generated during switching in relaxation oscillator 210 is steered to current compensation block 230. Consequently, the current flow through resistors 212, 214 of relaxation oscillator 210 is maintained at h ias , in turn causing the upper and lower bounds of voltages Vi and V 2 to be at +V C and— V c , respectively. As is seen from FIG. 2, current compensation block 230 includes a pair of cross-coupled transistors 232, 234 that are connected to the output nodes of the RC oscillator, and a current source 236 adapted to flow current Δ/ steered by oscillating circuit 210.

[0029] For certain aspects, frequency of the VCO (e.g., F VC o) may be written as follows:

Vc = I bias in which C represents the timing capacitor, V c represents the maximum amplitude of the voltage on the timing capacitor, and R L represents the resistive load. Certain aspects of the present disclosure propose a method that keeps the IR drop (in which / represents current and R represents the resistance) on the resistive load constant or nearly constant. Thus, V c is constant or nearly constant. As a result, frequency becomes a linear function of the current that is passing through the core of the oscillator. The proposed oscillator may operate over a wide frequency range (e.g., 3x or 4x) and maintain integrated phase noise nearly constant. Moreover, the jitter is proportional to the integrated phase noise, and inversely proportional to the oscillator frequency.

[0030] FIG. 4 illustrates an exemplary flowchart for generating an oscillating signal with a linear gain over a wide frequency range, in accordance with certain embodiments of the present disclosure. At 402, a first component of a current having a value up to a predefined level is delivered to a capacitive element disposed in a relaxation oscillator. At 404, a second component of the current exceeding the predefined level is steered away from the capacitive element. For certain embodiments, the second component of the current may be smaller than the first component of the current. An oscillating output signal may be generated using the relaxation oscillator.

[0031] For certain embodiments, a first pair of cross-coupled transistors may be coupled to the capacitive element. The first pair of cross-coupled transistors may compare a voltage across the capacitive element with a predefined value.

[0032] For certain embodiment, a second pair of cross-coupled transistors may be coupled to the relaxation oscillator. The second component of the current exceeding the predefined level may be steered through the second pair of cross-coupled transistors and away from the capacitive element. For certain embodiments, a voltage may be maintained across the capacitive element to a value defined by a resistance of a resistor disposed in the relaxation oscillator and the first predefined current level.

[0033] The methods, systems, and devices discussed above are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, in alternative configurations, the methods described may be performed in an order different from that described, and/or various stages may be added, omitted, and/or combined. Also, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Also, technology evolves and, thus, many of the elements are examples that do not limit the scope of the disclosure to those specific examples.

[0034] Having described multiple aspects above, an example of a computing system in which such aspects may be implemented may now be described with respect to FIG. 5. According to one or more aspects, a computer system as illustrated in FIG. 5 may be incorporated as part of a computing device, which may implement, perform, and/or execute any and/or all of the features, methods, and/or method steps described herein. For example, one or more of the processor 510, memory 535, and communications subsystems 530 may be used to implement any or all of the blocks as shown in FIGs. 2 and 4. For example, computer system 500 may represent some of the components of a hand-held device. A hand-held device may be any computing device with an input sensory unit, such as a camera and/or a display unit. Examples of a hand-held device include but are not limited to video game consoles, tablets, smart phones, and mobile devices. In some embodiments, the system 500 is configured to implement the devices 100 or 200 described above. FIG. 5 provides a schematic illustration of one embodiment of a computer system 500 that can perform the methods provided by various other embodiments, as described herein, and/or can function as the host computer system, a remote kiosk/terminal, a point-of-sale device, a mobile device, a set- top box, and/or a computer system. FIG. 5 is meant only to provide a generalized illustration of various components, any and/or all of which may be utilized as appropriate.

[0035] The computer system 500 is shown comprising hardware elements that can be electrically coupled via a bus 505 (or may otherwise be in communication, as appropriate). The hardware elements may include one or more processors 510, including without limitation one or more general-purpose processors and/or one or more special-purpose processors (such as digital signal processing chips, graphics acceleration processors, and/or the like); one or more input devices 515, which can include without limitation a camera, a mouse, a keyboard and/or the like; and one or more output devices 520, which can include without limitation a display unit, a printer and/or the like.

[0036] The computer system 500 might also include a communications subsystem 530, which can include without limitation a modem, a network card (wireless or wired), an infrared communication device, a wireless communication device and/or chipset (such as a Bluetooth® device, an 802.11 device, a WiFi device, a WiMax device, cellular communication facilities, etc.), and/or the like. The communications subsystem 530 may permit data to be exchanged with a network (such as the network described below, to name one example), other computer systems, and/or any other devices described herein. In many embodiments, the computer system 500 may further comprise a non-transitory working memory 535, which can include a RAM or ROM device, as described above.

[0037] The computer system 500 also can comprise software elements, shown as being currently located within the working memory 535, including an operating system 540, device drivers, executable libraries, and/or other code, such as one or more application programs 545.

[0038] Various examples have been described. These and other examples are within the scope of the following claims.