Background

[0001] Computing devices such as laptop computers, desktop computers, tablets, servers, and/or other types of computing devices may include a virtual memory system. In a virtual memory system, each process of the computing device may be provided a virtual address space (VAS). The address space for each process is virtual because the computing system may not actually include enough physical memory for every processes' address space to be loaded into physical memory at the same time.

Brief Description of the Drawings

[0002] Figure 1 is a block diagram of an example of a device for versioning of virtual address spaces (VAS)s according to the disclosure.

[0003] Figure 2 illustrates an example of a non-transitory processor readable medium according to the disclosure.

[0004] Figure 3 is a flow chart illustrating an example of a method suitable for versioning VASs according to the disclosure.

[0005] Figure 4 is a flow chart illustrating an example of a method suitable for versioning VASs according to the disclosure.

[0006] Figure 5 is a flow chart illustrating an example of a method suitable for versioning VASs according to the disclosure. Detailed Description

[0007] Devices with a virtual memory system may allow a process to include a virtual address space (VAS). For instance, a process may be associated with a particular VAS. Data and/or metadata among other information of the VAS associated with the VAS may change. For example, information of the VAS may change during and/or or as a result of execution of the process. It may be desirable to undo some changes to the VAS, for instance, to revert the VAS to a previous version of the VAS. However, some approaches such as those employing a fork system call may not permit tracking and/or undoing changes and/or may create an additional process as a result of their approaches.

[0008] Accordingly, examples of the disclosure relate to versioning virtual address spaces. As used herein, a versioned VAS refers to data and metadata of a VAS that is maintained in non-volatile memory beyond execution of a process and beyond powering off of a device including the non-volatile memory. As described herein, a versioned VAS is identified by a respective VAS version identifier. In an example, versioning virtual address spaces can employ a non- transitory processor readable medium including instructions to store first data and first metadata of a VAS associated with a process in a non-volatile memory to form a first version of the VAS, and store at least second data of the VAS associated with the process in the non-volatile memory to form a second version of the VAS. Desirably, versioning VASs can promote readily associating a plurality of versions of a VAS with a particular process (i.e., a single operating system process), in contrast to other approaches that may not version a VAS and/or create additional processes in an effort to version a VAS.

[0009] Figure 1 is a block diagram of an example of a device for versioning VASs according to the disclosure. As illustrated in Figure 1 , a device 1 10 can include a processor 120, a physical memory 130, a non-volatile memory 132 including a plurality of versions of a VAS 134-1 , ... , 134-P, and a non-transitory processor readable medium 140.

[0010] The device 1 10 may be a computing device, such as a server computer, a desktop computer, a laptop computer, a tablet, a smartwatch, and/or a smartphone, among other suitable devices to promote versioning VASs. The processor 120 can refer to a central processing unit (CPU), graphics processing unit (GPU), an application specific integrated circuit (ASIC), and/or another type processor to promote versioning VASs. The physical memory 130 can refer to dynamic random access memory (DRAM), static random access memory

(SRAM), non-volatile random access memory (NVRAM), phase change memory, and/or another suitable form of physical memory to promote versioning VASs. The physical memory 130 can store processor executable instructions and data. The physical memory 130 can be separate and distinct from the non-volatile memory 132 and/or can be formed, at least in part, of the non-volatile memory 132, among other possibilities.

[0011] The non-volatile memory 132 can refer to memory that does not depend upon power to store information such as metadata and/or data.

Examples of non-volatile memory can include solid state media such as flash memory, electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PCRAM), magnetic memory such as a hard disk, and/or a solid state drive (SSD), resistive memory such as memristors, etc., as well as other types of machine-readable media.

[0012] As mentioned, the non-volatile memory 132 includes plurality of versions of the VAS 134-1 , ... , 134-P. While illustrated as including two versions (e.g., a first version of the VAS and a second version of the VAS) the disclosure is not so limited. Rather, a total number of the versions can be varied to include more or less versions. Further, while aspects of the disclosure as described with reference to the first version of the VAS and/or the second version of the VAS it is understood that the disclosure applies to a plurality of versions including various numbers of sequential versions and is not limited to the first version of the VAS and/or the second version of the VAS.

[0013] Each version of the versions of the VAS 134-1 , ... , 134-P can be formed of at least respective data of the VAS at a given time. Note additional information such as respective metadata can be included in a particular version, as described herein. As a result, each version of the VAS can include respective data and metadata that respectively represent a particular version of the VAS. In some examples, a version of a VAS can be formed of data and metadata of a whole data structure. Notably, storing a whole data structure, as compared to other approaches that do not store a whole data structure, can provide

accelerated reboots of the device 1 10, rapid switching between versions of the VAS, as described herein, and/or provide comparatively decreased latency during operation of device 1 10 such as when attempting to reuse and restore metadata (e.g., existing address mappings to pages and/or objects) stored in another version of the VAS. In some examples, metadata stored in the nonvolatile memory 132 included in a version of a VAS can include objects at a sub- page size in contrast to other approaches employing process check pointing, object check pointing, and/or memory mapped files that may not be able to readily recognize, store, and/or employ individual sub-page sized objects.

[0014] A whole data structure can include pages (e.g., data and memory resources), translation structures (e.g., access metadata), data, and description information such as meta-metadata (e.g., which processor, address space size, endian, etc.). In some examples, a whole data structure can include functions. The functions can be stored as instructions in the non-volatile memory as loadable code and/or indirectly as pointers, among other possibilities. As described herein, the processor 120 can cause receipt and storage of data and metadata of a whole data structure of a process to form a version of the VAS. A version such as those in the plurality of versions of the VAS 134-1 , ... , 134-P can be maintained (e.g., maintained in a manner suitable to promote reuse thereof and restoration to a version of VAS as described herein) in the non-volatile memory across a system boot. A system boot can include powering off and powering on a device.

[0015] The non-transitory processor readable medium 140, as detailed with respect to Figure 2, can include instructions, which when executed by the processor 120 or other processor to cause the processor to implement aspects of the examples described herein. For example, the non-transitory processor readable medium 140 may include virtual memory system instructions 142. The virtual memory system 142 can abstract the physical memory 130 of the device 1 10 from processes running on the device 1 10. For example, each process running on the device can be provided with a respective virtual address space. The respective virtual address spaces can be sized according to various constraints of the virtual memory system 142, among other possibilities. In some examples, each process can utilize virtual address space in a manner that the process may not be aware of (e.g., aware of a size of) the physical memory 130 included in the device 1 10.

[0016] In operation, a process 150 executes on the device 1 10. That is, a process (e.g., a virtual machine) refers to instructions and/or data that can exist within a virtual address space and are executable by a processor to complete a task. For example, a database program running on the device 1 10 may be comprised of a number of processes. A process can run under control of an operating system and/or other type of controller such as a hypervisor.

[0017] In various examples, the process 150 is a single operating system process. That is, each version of a VAS of a plurality of versions of a VAS is associated with a single operating system process in contrast to other

approaches that may utilize at least two processes when attempting to version information.

[0018] As mentioned, the virtual memory system 142 can include a plurality of virtual address spaces 160-1 , ... 160-V. While illustrated as including two virtual address spaces the disclosure is not so limited. Rather, a total number of the virtual address spaces can be varied to include more or less virtual address spaces. A process 150 can be associated with a VAS such as the first VAS 160-1 . A VAS can be used by the virtual memory system instruction 142 to make it appear to the process 150 that a full address space of the device 1 10 is available to the process, even though the device 1 10 may not be equipped with enough physical memory for the process's entire VAS to be loaded into physical memory.

[0019] Figure 2 illustrates an example of a non-transitory processor readable medium 240 according to the disclosure. As mentioned, the non- transitory processor readable medium 240 includes instructions executable by a processor to perform a number of functions described herein.

[0020] The non-transitory processor readable medium 240 can be internal and/or external to the device (e.g., the device can include non-transitory processor readable medium and/or have access to an external non-transitory processor readable medium). The instructions (e.g., machine-readable instructions (MRI)) can include instructions stored on the PRM to implement a particular function. The set of MRI can be executable by a processor (e.g., processor 120 described with respect of Figure 1 ). The non-transitory processor readable medium 240 can be coupled to the device in a wired and/or wireless manner. For example, the non-transitory processor readable medium 240 can be an internal memory, a portable memory, a portable disk, and/or a memory associated with another resource (e.g., enabling MRI to be transferred and/or executed across a network such as the Internet).

[0021] Non-transitory processor readable medium 240 can include volatile and/or non-volatile memory. Volatile memory can include memory that depends upon power to store information, such as various types of dynamic random access memory (DRAM) among others. Non-volatile memory can include memory that does not depend upon power to store information.

[0022] As illustrated in Figure 2, the non-transitory processor readable medium 240 can include instructions such as store instructions 246 and store instructions 248. Notably, such instructions can promote formation of a plurality of versions of a VAS, as described herein.

[0023] In various examples, the store instructions 246 can store first data and first metadata of a VAS associated with a process in a non-volatile memory to form a first version of the VAS. The first version of the VAS is identified by a first VAS version identifier. A version identifier (e.g., a first VAS version identifier or a second VAS version identifier) refers to a numeric, alphabetic, alphanumeric, and/or other identifier suitable to identify a particular version of a VAS and/or promote switch between various versions of a VAS, as described herein. [0024] A first VAS version identifier and a second VAS version identifier, as described herein, are formed of different version identifiers. That is, each version of a plurality of versions of a VAS has a respective version identifier to facilitate restoration to the version of the VAS, among other aspects of versioning VASs. For instance, in some examples, a first VAS version identifier and a second VAS identifier can be different version identifiers included in sequence of identifiers corresponding to respective versions of the VAS.

[0025] Similarly, each VAS has its own set and/or sequence of version identifiers. That is, a particular VAS can have a particular version identifier and/or sequence of version identifiers that is specific to the particular VAS and different from a version identifier and/or a sequence of version identifiers of another VAS.

[0026] In various examples, the store instructions can store a whole data structure. A whole data structure includes data and metadata along with other information of a VAS. As mentioned, formation of a version of a VAS can include storage of at least data of the VAS. For instance, all data included in a whole data structure of a VAS can be stored to form a version of the VAS.

[0027] The store instructions 248 can, in various examples, store at least second data of the VAS associated with the process in the non-volatile memory to form a second version of the VAS. For example, the store instructions 248 can store the second data or the second data and second metadata to form the second version of the VAS. The second version of the VAS can be identified by a second VAS version identifier such as a those version identifiers described herein.

[0028] In various examples, metadata (e.g., second metadata) of the VAS can be stored during and/or following formation of the version of the VAS. For instance, all metadata of the VAS can be stored during formation of a version of a VAS, some metadata of the VAS can be stored during and/or following formation of the version of the VAS, or all metadata of the VAS can be stored following formation of the version of the VAS. Whether metadata is stored during and/or following formation of a version of a VAS can depend upon a desired application of the version of the VAS, among other possibilities.

[0029] In some examples, the store instructions 248 can include

instructions to store at least a portion of second metadata of the VAS in the nonvolatile memory when the second version of the VAS is formed. The store instructions 248 can, in some examples, store all of the second metadata (e.g., segment descriptions, page tables, etc.) in the non-volatile memory when the second version of the VAS is formed (i.e., storing metadata "eagerly"). However, the disclosure is not so limited.

[0030] Rather, at least some of the second metadata can be incrementally stored following formation of the second VAS. For instance, in various examples, the store instructions can include instructions to store some but not all of the second metadata in the non-volatile memory when the second version of the VAS is formed (i.e., storing metadata "lazily"). For example, some (e.g., a page table) but not all of second metadata included in a whole data structure can be stored when the second version of the VAS is formed.

[0031] In some examples, the store instructions 248 can store the second metadata as copy-on write. For instance, in examples where all of the second metadata stored when the second version is formed can be stored as copy-on write, among other possible storage classifications (e.g., read-only, etc.).

[0032] The store instructions 248 can include instructions to delete the first metadata from the first version of the VAS. For instance, the first metadata can be deleted in response to forming the second version of the VAS including all of the second metadata.

[0033] The store instructions 248 can store a portion of the second metadata in response to an attempted write the VAS. For example, by copying the metadata from the previous version and then modifying it in response to the write to VAS.

[0034] In some examples, the instructions can include instructions to modify the first data, the first metadata, or a combination of the first data and the first metadata. In such examples, the store instructions 248 can include instructions to store the modified first data, metadata, or combination of the first data and the first metadata as the second data and the second metadata. In this manner, modifications to the first data and/or the first metadata can be stored in the second version of the VAS but not the first version of the VAS and/or otherwise promote versioning of VASs.

[0035] The versions of the VAS can be maintained in the non-volatile memory in response to powering off a device (i.e., a device power-off) that includes the non-volatile memory. That is, the versions of the VAS can be maintained across a system boot and/or a device resume (e.g., resuming from a sleep state such as an Advanced Configuration and Power Interface ACPI sleep state S3, S4, etc.), among other possibilities.

[0036] Figure 3 is a flow chart illustrating an example of a method suitable with versioning VASs according to the disclosure. As shown at 366, the method 365 can include storing first data and first metadata of a VAS in a non-volatile memory to form a first version of the VAS identified by a first VAS version identifier, as described herein.

[0037] As shown at 367, the method 365 can include modifying the first data, the first metadata, or a combination of the first data and the first metadata. As described herein, modifying metadata and/or data can include altering (e.g., adding, deleting, and/ changing, etc.) instructions included in the metadata and/or the data.

[0038] The method 365 can include storing second data, including the modified first data, and second metadata, including the modified first metadata, in the non-volatile memory to form a second version of the VAS identified by a second VAS version identifier, as shown at 368. For instance, the second data can include and/or be formed of the modified first data. Similarly, the second metadata can include and/or be formed of the modified first metadata.

[0039] In some examples, the method 365 can include retrieving the first data, the first metadata, or combination of the first data and the first metadata using the first VAS version identifier to restore the VAS to the first version as described herein. For instance, in some examples, such retrieving can occur in response to a page fault experienced by the second version of the VAS, among other possible triggers such as a user input that can cause retrieving of metadata and/or data of an earlier version of a VAS. That is, in some examples, a particular version of VAS experiencing a page fault can cause retrieving of metadata and/or data of a comparatively error version of the VAS to handle the page fault and/or restore the VAS to the earlier version of the VAS, among other possibilities.

[0040] Versions of a VAS can be stored in a persistent store. As used herein, a persistent store refers to non-volatile memory including a plurality of versions of VAS and/or VASs. Versions of a VAS in the persistent store can be accessed (e.g., restored), added to, compacted, and/or deleted, among other possibilities. For example, a version of a VAS can be restored as described herein.

[0041] Figure 4 is a flow chart illustrating an example of a method suitable with versioning VASs according to the disclosure. The method 475 can be employed through execution of instructions such as those described herein. The method 475 can promote formation/storage, access, and/or querying of a plurality of versions of a VAS. As illustrated at 476-1 , the method 475 can include execution of instructions, such as those described herein, to create a new empty VAS. An empty VAS refers to information such as that associated with a VAS stored in non-volatile memory that is without metadata and/or data but can receive metadata and/or data of a VAS which is a previous version of the given VAS.

[0042] At 476-2 the method 475 can include executing instructions to write protect an old memory region (e.g., write protecting a regions corresponding to an earlier/current version of a VAS) as compared to a comparatively version of the VAS being formed using the empty VAS formed at 476-2, among other possibilities. In some examples, the old memory region can correspond to that of a first version of the VAS, among other possible versions of the VAS.

[0043] The method 475 can include executing instructions to replicate old address mapping in the new (empty) address space as shown at 476-3. In some examples, the new address space can correspond to a second version of the VAS, among other possible versions. The mappings can be replicated through copying the address mapping "eagerly" and/or "lazily", as described herein.

[0044] At 476-4 the method 475 can switch to the new address space (formed at 476-1 ). Switching can include changing the address space pointer in a register (e.g., register CR3), among other possibilities.

[0045] The method 475 can proceed to 476-5 and continue execution (i.e., normal execution) of a version of the VAS corresponding to the version switched to at 476-4. Execution can continue until a page fault or/and user input requesting a different version is received. For example, as shown at 476-6 the method 475 can execute and it can be determined whether the version of the VAS experiences a page fault (i.e., write a page fault) during execution. When a page fault is handled the method can proceed to 476-7 and copy memory, change mappings, and mark memory writable. In short, the version of the VAS that handled a page fault and/or is associated with a page fault can be restored to another (e.g., previous version of the VAS) and execution can continue at 476- 5 with the restored version of the VAS. However, at 476-6 when it is determined that a page fault is not handled execution can continue at 476-5.

[0046] Figure 5 is a flow chart illustrating an example of a method 580 suitable with versioning VASs according to the disclosure. The method 580 can be employed through execution of instructions such as those described herein. At 581 -1 the method 580 can include finding a revision of a version of a VAS. For example, finding a revision can include retrieving data, metadata, or combination of data and metadata suitable to restore the VAS to another version (e.g., an earlier version) of the VAS.

[0047] As shown at 581 -2 the method 580 can include switching the VAS from a version of the VAS to another version of the VAS. For instance, switching the VAS can include restoration of the VAS to an earlier version of the VAS. It is noted such restoration can go back to any number of earlier versions such a first version (e.g., version 1 .0) or subsequent version (e.g., version 1 .2) of a VAS that are earlier than a current version of a VAS (e.g., version 2.0). [0048] The method 580 can include executing instructions to return an execution context to an application, as shown at 581 -3. For instance, returning an execution context can include returning a restored previous version of a VAS to the application, among other possibilities.

[0049] In some examples all address space and/or a region of a VAS can be versioned. A region of a VAS refers to a uniquely identified contiguous part of a VAS. For example, each region in a VAS can be evaluated to identify whether it is to be versioned.

[0050] As used herein, "logic" is an alternative or additional processing resource to perform a particular action and/or function, etc., described herein, which includes hardware, e.g., various forms of transistor logic, ASICs, etc., as opposed to computer executable instructions, e.g., software firmware, etc., stored in memory and executable by a processor. As used herein, "a" or "a number of" something can refer to one or more such things. When an element is referred to as being "on," "connected to", "coupled to", or "coupled with" another element, it can be directly on, connected, or coupled with the other element or intervening elements may be present.

[0051] Since many examples can be made without departing from the spirit and scope of the system and method of the disclosure, this specification merely sets forth some of the many possible example configurations and implementations. In the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of examples of the disclosure can be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure, and it is to be understood that other examples can be used and that process, electrical, and/or structural changes can be made without departing from the scope of the disclosure.

[0052] The figures herein follow a numbering convention in which the first digit corresponds to the drawing figure number and the remaining digits identify an element or component in the drawing. Elements shown in the various figures herein can be added, exchanged, and/or eliminated so as to provide a number of additional examples of the disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the examples of the disclosure, and should not be taken in a limiting sense.