Title:
VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION
Document Type and Number:
WIPO Patent Application WO/2014/137652
Kind Code:
A3
Abstract:
A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.
Inventors:
RABKIN PETER (US)
HIGASHITANI MASAAKI (US)
HIGASHITANI MASAAKI (US)
Application Number:
PCT/US2014/018125
Publication Date:
November 20, 2014
Filing Date:
February 25, 2014
Export Citation:
Assignee:
SANDISK 3D LLC (US)
International Classes:
H01L27/24; H01L27/105; H01L27/115; H01L29/786; H01L45/00; G11C13/00
Foreign References:
| US20120147644A1 | 2012-06-14 | |||
| US20060250837A1 | 2006-11-09 | |||
| JPH05160408A | 1993-06-25 | |||
| US5668391A | 1997-09-16 |
Attorney, Agent or Firm:
MAGEN, BURT (575 Market Street Suite 3750,San Francisc, California, US)
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