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Patent Searching and Data


Title:
VIA PROGRAMMABLE GATE ARRAY INTERCONNECT ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO2004015744
Kind Code:
A3
Abstract:
A segmentation architecture for wiring segments which provides interconnections for a gate array integrated circuit is described. Programming is provided by selectable vias (33 34) between wiring segments (31V 31H 32V 32H) and to the semiconductor substrate surface. The wiring segments of two interconnection layers (31 and 32) are arranged in two directions and a programmable buffer (NOT SHOWN) can drive signals in a selectable direction depending upon how the via contacts (33 34) are made to the buffer by the wiring segments carrying the buffer signals.

Inventors:
SPADERNA DIETER WOLF
WONG DALE
Application Number:
PCT/US2003/024863
Publication Date:
August 26, 2004
Filing Date:
August 08, 2003
Export Citation:
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Assignee:
LEOPARD LOGIC INC (US)
International Classes:
H01H73/00; H01L23/48; H01L27/10; H01L27/118; H01L; (IPC1-7): H01L27/10; H01L23/48
Foreign References:
US20030039262A12003-02-27
US6016000A2000-01-18
US4982114A1991-01-01
US4965651A1990-10-23
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