COMMUNICATIONS

FIELD

[0001] Embodiments described herein generally relate to a method of decoding and to a decoder. Some embodiments relate to a Viterbi decoder and to a method for decoding message bits based on a Viterbi algorithm.

BACKGROUND

[0002] To enhance communication quality or data transmission quality over a disturbed transmission channel it is known to encode a message prior to transmitting. So-called forward error correction (FEC) codes encode the message redundantly. By encoding message bits so-called parity bits are generated. Each parity bit may bear information about more than one message bit. These parity bits are transmitted over the transmission channel. That is, information on each message bit is transmitted over more than one transmitted bit.

[0003] At the receiver side, a decoder is used to decode the transmitted bit stream. The decoder generates probability values. The probability values correspond to a probability for a certain message bit or bit sequence. Or, in other words, they indicate which message bit sequence is most likely to be the origin of the received bit sequence.

Therefore, these decoders are also called most likelihood decoders .

[0004] Although powerful algorithms are known to decide for the most likely message bit sequence, an improvement of decoder performance is still required. [0005] A powerful decoder performance is the more important the more a correct message decoding is important. An example for an important message in which each bit is to be decoded correctly is a so-called master information block (MIB) . An MIB is used, e.g., in a physical broadcast channel (PBCH) in a long term evolution (LTE) mobile communication system. A correct decoding of the MIB transmitted over the broadcast channel enables a user equipment e.g. to take the most advantageous decision concerning whether to change to another cell and further allows the user equipment e.g. to adapt its functionalities to the cell.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of aspects and are incorporated herein and constitute a part of the specification. The drawings illustrate aspects and together with the description serve to explain principles of aspects. All the aspects and many of the intended advantages of aspects will be readily

appreciated as they become better understood by reference to the following detailed description. Like reference numerals designate corresponding similar parts.

[0007] Figure 1 schematically illustrates a broadcast channel transmission in a cellular mobile system.

[0008] Figure 2 schematically illustrates an MIB used in a PBCH in an LTE mobile communication system.

[0009] Figure 3 schematically illustrates a mobile phone comprising an embodiment of a decoder. [0010] Figure 4 schematically illustrates in a block diagram a decoder according to an embodiment.

[0011] Figure 5 schematically illustrates in a block diagram a Viterbi decoder according to an embodiment.

[0012] Figure 6 schematically illustrates in a block diagram a Viterbi decoder according to an embodiment.

[0013] Figure 7 illustrates in an exemplary Trellis diagram a decoder function according to an embodiment.

[0014] Figure 8 schematically illustrates a Viterbi decoder function according to an embodiment.

[0015] Figure 9 schematically illustrates in a flow diagram a method of decoding according to an embodiment.

[0016] Figure 10 schematically illustrates a method of decoding according to an embodiment.

[0017] Figure 11 shows in a diagram decoding failure rates depending on a transmission channel quality for a decoder according to the prior art compared decoding failure rates for embodiments.

DETAILED DESCRIPTION

[0018] In the following, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. However, it may be evident to a person skilled in the art that one or more aspects may be practiced to a lesser degree of these specific details. The following description is therefore not to be taken in a limiting sense. The scope of the protection is defined by the appended claims.

[0019] The various aspects summarized may be embodied in various forms. The following description shows by way of illustration various combinations and configurations in which the aspects may be practiced. It is understood that the described aspects and/or embodiments are merely examples and that other aspects and/or embodiments may be utilized and structural and functional modifications may be made without departing from the scope of the present disclosure.

[0020] In addition, while a particular feature or aspect of an embodiment may be disclosed with respect of only one of several implementations, such feature or aspect may be combined with one or more of the features or aspects of the other implementations as may be desired in advantages for any given or particular application. A particular feature or aspect disclosed with respect of an apparatus may be also applicable to a disclosed method.

[0021] Further, to the extent that the terms "include", "have", "with" or other variances thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also the term "exemplary" is merely meant as an example rather than the best optimum.

[0022] The specified embodiments may be part of a mobile communication system. The embodiments may be part of a cellular mobile radio system. They may be part of an LTE system and more specifically of a receiver used in an LTE system. More generally, a communication system may comprise a wireless LAN, a mobile radio system and a satellite communication system.

[0023] Figure 1 shows an exemplary cellular communication system comprising two cells 10.1 and 10.2. It is to be understood that the cellular system may comprise more than two cells. In cell 10.1 a base station 12 is schematically illustrated. The base station 12 may be referred to as NodeB. The base station may be an evolved NodeB (eNB) . The cellular system schematically represented in Figure 1 may be an LTE system. A mobile phone 14 is schematically represented in cell 10.2. The term "mobile phone" as used throughout the present application is to be understood in a broad sense. A mobile phone is any user equipment able to communicate in the LTE system or, more generally, in a radio communication system. For example, the mobile phone 14 may be also a tablet, a laptop, a watch adapted to communicate in a radio communication system, and so on. As shown in Figure 1, base station 12 broadcasts information via a PBCH. The mobile phone 14 receives the broadcast.

[0024] In a cellular mobile communication system a user equipment is frequently forced to change to another cell. For successfully selecting a new cell and deciding for a handover from one cell to another, the user equipment needs

information about the surrounding cells. In the LTE system, which is used as an example throughout the application without limiting the disclosure to the LTE system, this information is broadcasted via the physical broadcast channel PBCH. To cope with difficult transmission conditions the information is broadcasted in encoded form. It is a

prerequisite to successfully decode the PBCH information before a user equipment is able to reselect or handover to another LTE cell.

[0025] Figure 2 schematically represents a message in form of a control information block which is to be broadcasted over the PBCH. By way of example, the control information block may be a block containing system information such as, e.g., the master information block MIB which is broadcasted over the PBCH in, e.g., LTE communication systems. An FEC code may be used for encoding the MIB. The MIB (or, more generally, the control information block) may comprise information about a limited number of parameters which may be essential to know for initial access to a new cell. The parameters may, e.g., comprise a downlink system bandwidth, a physical hybrid automatic repeat request indicator channel

(PHICH) structure and the most significant 8 bits of a system frame number (SFN) . The MIB may, e.g., be an information block of a total of 24 bits. The 24 bits may comprise 3 bits for the downlink system bandwidth, 3 bits for the PHICH information, and 8 bits for the system frame number. The remaining 10 bits may be reserved for further information. For the user equipment to be able to decode any other

physical layer channels it is essential to know the downlink system bandwidth. Or in other words, the user equipment should decode correctly the 3 bits concerning the downlink system bandwidth. The PHICH information is important because it informs the user terminal or equipment about the duration of the PHICH which is essential for decoding the control channels completely. Finally the SFN allows for initial synchronization and for periodical synchronization. The frame number in which the base station transmits is further

required in a scrambling process. Therefore, it is important for the user equipment to know the frame number. Further, information of transmit antennas (e.g. the number thereof, etc.) may be needed for a de-precoding process at physical layer processing. Additionally, the PBCH redundancy check mask may be needed to be determined.

[0026] The PBCH may be a downlink only channel. The PBCH may use a 10 ms radio frame which is repeated four times. Each of the 10 ms sub-frames is self-decodable . In other words, a single signal obtained by encoding MIB is divided and

transmitted for a period of 40 ms . Every 10 ms the four PBCH radio frames include the same MIB which is transformed into different signals via scrambling.

[0027] FEC codes may generally distinguish between

convolutional codes and block codes. Convolutional codes are processed on a bit-by-bit basis and may be decoded by a

Viterbi decoder. Block codes are processed on a block-by- block basis. The forward error correction codes have in common that encoding involves computation of parity bits from a sequence of message bits and transmitting these parity bits via the transmission channel to the receiver. Using the parity bits implies that one message bit influences several parity bits and the other way round a parity bit comprises information about a plurality of message bits. In a block code the message bits are sent together with the parity bits while in a convolutional code it may be the case that only the parity bits are sent.

[0028] Decoders adapted to decode FEC codes are also called most likelihood decoders. The decoder calculates a

probability according to which a sequence of reconstructed message bits based on the received parity bits corresponds to the encoded sequence of message bits. Depending on the code, different measures for the probability values may be used. In a Viterbi decoder so-called branch metrics and state metrics (or path metrics) are calculated to recover the transmitted bit sequence. So-called log-likelihood ratios (LLR) also known as "soft-bits" may be generated as a measure for the confidence or probability of the decoder output.

[0029] Figure 3 schematically shows an embodiment of a user equipment 20. The user equipment may be a mobile phone. The user equipment 20 comprises a radio frequency (RF) module 22 which obtains radio samples. The user equipment 20 further comprises a baseband module 24 which is configured to perform baseband processing on the radio samples. The baseband module 24 may comprise a media access control (MAC) and a physical

(PHY) layer controller 26, a cell measurement module 28 and a downlink receiver module 30 which may comprise a decoder 32 according to an embodiment. The MAC, PHY controller 26 may control the RF module 22 and the baseband module 24. Decoder 32 may be a most likelihood decoder. Decoder 32 may, e.g., be a Viterbi decoder.

[0030] Figure 4 shows schematically in a block diagram a decoder 34 according to an embodiment. Decoder 34 comprises a first unit 36 and a second unit 38. The first unit 36 and the second unit 38 may be implemented in hardware. The first unit 36 and the second unit 38 may be implemented in software. The first unit 36 and the second unit 38 may be implemented in any combination of software and hardware. The first unit 36 may be configured to generate a probability value for a candidate sequence of bits to correspond to an original sequence of bits. Or, in other words, the probability value expresses a probability that a sequence of reconstructed message bits based on the received bits corresponds to the sequence of message bits encoded on the transmitter side. The candidate sequence of bits may have a defined length. For example, a sequence length may be 6 bits. Each bit may have one of two possible values. The value of a bit may be 1 or 0, H or L, +1 or -1 according to the terminology used. Without loss of generality, throughout the present application the terminology of, e.g., 1 and 0 is used. By way of example, for a sequence of 6 bits 2 ^s = 64 sequences of bits are possible. Only one of these possible bit sequences of reconstructed message bits is the original sequence of message bits sent by the transmitter. The first unit 36 may generate, based on an algorithm, a probability for each of the candidate sequences of bits. The function of the first unit is known as such in the prior art.

[0031] The second unit 38 may be configured to force the probability value to a pre-defined value of low probability if at least a value of one bit out of the candidate sequence of bits is known not to correspond to a value of the

respective bit of the original sequence of bits based on pre- knowledge of the original bit sequence. In other words, a- priori the decoder 34 does not know the bits to decode.

However, for example in the case of a master information block, as discussed with reference to Figure 2, it is

possible that, for example, the mobile device 20, as

discussed with reference to Figure 3, may have a pre- knowledge of at least one of the bits out of the defined transmitted sequence of bits. The defined transmitted

sequence of bits may be part of the twenty-four bits of the MIB.

[0032] As discussed previously, the MIB comprises 3 bits for the downlink system bandwidth (BW) . The downlink system bandwidth may, e.g., be blind detected beforehand. In this case, 3 bits out of the twenty-four MIB bits may be known as a pre-knowledge . Blind detecting of the bandwidth may, e.g., be performed by using cell-specific reference signals (CRS) . In an LTE system, CRS signals are, for example, used to perform channel estimation at the user equipment side. As the number of CRS available within a sub-frame depends on the system bandwidth, this allows blind detection of the

bandwidth. Because of the character of the FEC codes to interrelate the message bits for transmission, pre-knowledge of one or more bits enhances the quality of detection for the unknown bits. It is to be noted that pre-knowledge of one or more bits may also be gained other than by exploiting CRS.

[0033] Most likelihood decoding may be a step-by-step process in time. Setting a probability value to a very low probability influences subsequent decoding steps. In the step-by-step decoding process the most significant bit of the sequence may change in each (time) step. When setting the probability value of one or more of the candidate sequences to a very low probability, the bit which corresponds to a pre-known bit may be the most significant bit of the sequence of bits.

[0034] Pre-knowledge of the bit value may be obtained from a higher communication level. For example, in the embodiment of Figure 3 the pre-knowledge may be obtained from the MAC, PHY controller 26. In an embodiment, the pre-knowledge may be obtained during a cell detection phase performed by the cell measurement block 28 of Figure 3. By way of example, pre- knowledge may be obtained during a blind detection phase performance based on wide band RSRP (reference signal received power) and/or SINR (signal to interference plus noise ratio) measurements.

[0035] The pre-knowledge may also concern a message bit which is indicative of an SFN. This may be, for example, the case in an SFN synchronized network. In this case 10 bits of a neighbor cell SFN number may be known a-priori because they are the same as for the serving cell. Again, knowing these bits enhances decoding performance for the other unknown bits. They kind of protect their surrounding bits due to the nature of FEC code. Hence, the decoding performance of a most likelihood decoder can be increased by making use of the known bits.

[0036] Decoder 34 may be a Viterbi decoder decoding a convolutional code based on a Viterbi algorithm. In this case the probability value may be a state metric (also referred to as a path metric) . A Viterbi algorithm can be visualized in a trellis diagram. In a trellis diagram, the states of the encoder register (corresponding to the transmitted bit sequence) are plotted versus the discrete time i. Forcing the probability value to a pre-defined low probability value may concern all those trellis states at a time i+1 for which a value of the at least one bit in the trellis state is known not to be the correct value of the bit. The state metric

(path metric) of these trellis states may be forced to a pre ^¬ defined value, e.g. to the maximum state metric value at discrete time i+1 (which corresponds to a very low

probability) .

[0037] In other embodiments, decoder 34 may, e.g., be a turbo decoder adapted to decode a turbo code, or a low- density parity-check (LDPC) decoder configured to decode a LDPC code. Both codes are using the log-likelihood ratio (LLR) as metric. The LLR can be manipulated in the same way by forcing it to values which the decoder can interpret clearly (e.g. very high or very low probability) . That is, the probability value set to a very high or very low

probability may be a LLR related to, e.g., a (single) decoded bit or extrinsic information used in iterative decoding or, in general, other LLR quantities used in the decoding

process. In this case, the first unit 36 may be configured to generate a probability value for a single bit to correspond to an original single bit. Or, in other words, the

probability value expresses a probability that a single reconstructed message bit based on the received bits

corresponds to the single message bit encoded on the

transmitter side. By way of example, the LLR of a decoded bit may be forced to a high probability value given the decoded bit (or extrinsic information corresponding to the decoded bit) corresponds to the pre-known transmitted message bit.

[0038] Figure 5 schematically illustrates a Viterbi decoder 40 according to an embodiment. Viterbi decoder 40 comprises a memory 42 and a forcing unit 44. Forcing unit 44 may be implemented in hardware. Forcing unit 44 may be implemented in software. Forcing unit 44 may be implemented in any combination of software and hardware. Memory 42 may be a pre- knowledge memory which is configured to store pre-knowledge of at least one message bit out of the message bits to be decoded. The pre-knowledge may be obtained as discussed with reference to Figure 4. E.g., cell measurement unit 28 or MAC, PHY controller 26, as shown in Figure 3, may be

configured to write a pre-knowledge bit value into memory 42. The pre-knowledge bit value may also be written by another entity into the memory 42. [0039] The forcing unit 44 may be configured to set a state metric to a predefined high value for all those possible trellis states for which the most significant bit corresponds to a message bit for which pre-knowledge is stored in the memory 42 and for which trellis states a value of the most significant bit does not correspond to a value of the message bit according to the pre-knowledge stored. In a convolutional code decoding is effectuated on a bit-by-bit basis. At each time step in the decoding process of a convolutional code, the next bit is added to a previous sequence of bits as the most significant bit and the least significant bit out of the previous sequence of bits is dropped.

[0040] Viterbi decoder 40 may be used to decode an MIB received over a PBCH of an LTE mobile communication system. The pre-knowledge may, as discussed with reference to Figure 4, concern a message bit indicative of a downlink system bandwidth and/or a message bit indicative of a system frame number. The forcing unit 44 may be adapted to determine whether a most significant bit of a candidate sequence of bits, e.g. a trellis state, corresponds to a pre-known bit. In the case of an MIB to be decoded, the forcing unit 44 may determine to which bit out of the MIB the most significant bit corresponds. For example, the most significant bit of the trellis state may correspond to the first bit out of three bits indicating the downlink system bandwidth. The forcing unit 44 may then determine whether this bit is pre-known and stored in the memory 42. If the bit is pre-known, the forcing unit 44 may determine whether the value of the most

significant bit corresponds to the value of the corresponding bit stored in the memory 44. The message bit, for which the pre-knowledge is stored, defines the most significant bit of the successor state. E.g., if the stored bit is a "1", all states with a "0" as most significant bit are forced to low probability .

[0041] Figure 6 illustrates schematically in a block diagram a Viterbi decoder 46 according to an embodiment. Viterbi decoder 46 may comprise a first input 48, a second input 50 and a metric forcing unit 52. Metric forcing unit 52 may be implemented in hardware. Metric forcing unit 52 may be implemented in software. Metric forcing unit 52 may be implemented in any combination of software and hardware.

Viterbi decoder 46 may be configured to decode an MIB

received over a PBCH in an LTE mobile communication system. The first input 48 may be configured to receive a transmitted parity bit sequence representing the MIB in convolutional coded form. Referring to Figure 3, first input 48 may be coupled to the downlink receiver 30. The downlink receiver 30 may receive from the RF module the transmitted parity bits. The second input 50 may be configured to receive pre- knowledge information about a value of at least one of the message bits. Second input 50 may be coupled to the

measurement block 28 or to MAC, PHY controller 26 to receive the pre-knowledge as discussed above.

[0042] The metric forcing unit 52 may be configured to force a metric based on the message bit information received on the second input 50. The metric forcing unit 52 may be configured to set the metric to a maximum metric for all those possible trellis states for which a value of the most significant bit is known not to correspond to a value of the message bit based on the received pre-knowledge information. By way of example, the metric set by the metric forcing unit 52 may be the state metric of a trellis state. That is, the trellis state metric of a trellis state at discrete time i+1 is set to a maximum metric (i.e. very low probability) if the pre- known bit for the transition from discrete time i to i+1 excludes this trellis state from being accessed.

[0043] In the following, the function of the decoders is explained in more detail with reference to Figures 7 and 8. The function is explained based on a Viterbi decoder using a convolutional code. This is not meant to limit the

embodiments to a Viterbi decoder and the disclosure can easily be applied to other codes (decoders) such as, e.g., a turbo code (turbo code decoder) , a LDPC code (LDPC code decoder), or a block code (block code decoder) as well.

[0044] Figure 7 shows a trellis diagram. The trellis diagram of Figure 7 is based on a sequence of, e.g., 6 bits leading to 2 ^s = 64 possible trellis states 0 to 63. Actually, in convolutional coding, the length of a bit sequence is related to the so-called constraint length of the convolutional code. As an example, in LTE systems a constraint length K = 7 is used. With a constraint length K = 7, there are 64 possible states (generally, there are n states, and n = 2 ^K_1 ) . Figure 7 shows in a first column the state numbers n from 0 to 63. In the first horizontal line the discrete time t is noted as t = i, i+1, and i+2. The state corresponds to the state number in binary representation, i.e. the state 0 corresponds to a bit sequence "000000", state 1 corresponds to a bit sequence "000001", state 2 corresponds to a bit sequence "000010", state 3 corresponds to a bit sequence "000011", and so on. As such, state 63 corresponds to a bit sequence

"111111". These are all possible states for a 6 bit sequence

(corresponding to the 64 possible states of the encoder register) . More specifically, for the example used herein, the decision for a message bit is done based on the 6 bits of a state and of course the parity bits. Actually, three parity bits may represent one message bit (see the exemplary

encoding process) . That means that for calculating the likelihood metric (state metric) the 6 bits of a state and the assumed message bit are taken into account. This results in 7 relevant bits for the SELECT decision (see below) and explains the constraint length of K = 7.

[0045] At a time i no bit is known for sure, so any of states 0 to 63 may be possible states. At the transition from time i to i+1, it is assumed that a known message bit is transmitted. Pre-knowledge may concern in the case of an MIB for example the downlink bandwidth or the SFN. In the example shown in Figure 7, the value of the pre-known bit may be "1". This means that a bit "1" is added as the most significant bit to the binary sequence. Therefore, at a time i+1 any state having a "0" as most significant bit cannot be reached. Or, equivalently, only states having a binary representation of equal to or greater than 32 are valid states (since the message bit assumed is the most significant bit of the states the path leads to) . This is represented in the trellis diagram of Figure 7 by the use of broken lines for all transition arrows leading to invalid states having, in this example, a binary representation of less than 32. That is, as the broken lines indicate invalid branches for transitions from time i to i+1, the second unit 38, according to the embodiment shown in Figure 4, or the forcing unit 44,

according to the embodiment shown in Figure 5, or the metric forcing unit 54, as shown in Figure 6, may set the state metric of the invalid states to a value corresponding to a very low probability. On the other hand, solid lines are used for transitions into possible states having a binary representation of equal to or greater than 32. Note that arrows starting from states 29 to 34 are neglected for the sake of clarity in Figure 7.

[0046] For time i+2 (or, more precisely, the transition from time i+1 to i+2) it is assumed that the message bit is unknown at the receiver. As such, all state transitions

(branches) are possible again (broken lines and solid lines) . However, there are still invalid states (or states with a very low probability) due to the fact that states which could not be accessed at time i+1 do not have successor states (or, stated more generally, the successor states of these states will also have a very low probability) . This has the

consequence that not all states can be accessed at discrete times i+2, i+3, ... and so on.

[0047] This can be seen from the binary representation of the states. At time i+1, the valid states are described by the binary sequence "luuuuu". The most significant bit is "1" and "u" denotes an unknown bit. Invalid states are indicated by hatching. At time i+2, the bits in the states are shifted as explained above and the most significant bit is now unknown, leading to valid states represented by the binary sequence "uluuuu". States in the trellis are only valid states if they fulfil this condition (i.e. if they have a state number of 16 to 31 and 48 to 63, invalid states are indicated by hatching) . That is, again, 32 of the 64 states are excluded. This systematics holds for all next time steps until the "1" (i.e. the known bit) is eliminated by right shifting the sequence. In other words, knowledge of one bit value at a time i+1 propagates through the trellis diagram and thereby results in exclusion of subsets of trellis states at each of these K-l time steps. This "temporary" reduction of possible states in the trellis diagram increases the possibility that the convolutional decoding is successful.

[0048] Figure 8 schematically illustrates a Viterbi decoder 54 according to an embodiment. Figure 8 especially visualizes how an embodiment may add functionality to a conventional Viterbi decoder. Viterbi decoder 54 comprises an ACS unit 56 and a unit 58 according to an embodiment. Unit 58 may be implemented in hardware. Unit 58 may be implemented in software. Unit 58 may be implemented in any combination of software and hardware.

[0049] The Viterbi decoder comprises a so-called ACS unit. ACS stands for ADD-COMPARE-SELEC . In short, Viterbi decoding is based on finding the shortest path through a state diagram

(trellis) as depicted in Figure 7. According to the Viterbi algorithm, a branch metric (also referred to as a transition metric) which represents a measure of probability for a branch (transition from one state at time i to another state at time i+1) is calculated for each possible branch

(transition) between two states. The branch metrics are then added to the respective state metrics of the previous states

(ADD) . For branches leading to the same target state, the sums which are obtained in this way are compared (COMPARE) . That branch to the target state under consideration whose sum of the branch metric and state metric of the previous state is minimum is selected (SELECT) and forms the extension of the path leading to this previous state to the target state

(survivor path) . The other path running through the

deselected previous state is discarded. These three basic operations of the Viterbi algorithm are known as ACS

operations. ACS unit 56 processes these three basic

operations. As such, ACS unit 56 may generate state metrics (probability values) for each trellis state at times i, i+1, i+2, .... ACS unit 56 may correspond to the first unit 36 shown in Figure 4.

[0050] Unit 58 of Viterbi decoder 54 may correspond to the second unit according to the embodiment shown in Figure 4, or to the forcing unit 44 as shown in Figure 5 or to the metric forcing unit 52 as shown in Figure 6. Unit 58 may comprise a first input 60 and a second input 62. Unit 58 may further comprise a first output 66 and a second output 74.

[0051] Unit 58 may receive at a given time step at the first input 60 the selected state metric from the ACS unit 56. Unit 58 may receive at the second input 62 information about given pre-knowledge . Unit 58 may be configured to decide at 64 whether at the given time step a pre-knowledge about a bit, for example about the most significant bit of the bit

sequence corresponding to the binary state representation is available. As explained above, the pre-knowledge may be stored in a pre-knowledge memory (e.g. pre-knowledge memory 42) prior to be input to unit 58. The pre-knowledge may be received from a higher communication level. The pre-knowledge may be obtained, for example, by cell measurement, e.g. by doing system bandwidth blind detection based on RSRP and/or SINR measurement in different system bandwidth hypothesis.

[0052] If at the given time step there is no pre-knowledge, or in other words, if the most significant bit at this time is not pre-known, the state metric is not changed and is output at the first output 66. Output 66 may be coupled to ACS unit 56. In other words, the unchanged state metric is fed back to ACS unit 56. [0053] If, on the other hand, the answer to the question at 64 whether the bit at the given time step is pre-known is yes, the value of the pre-known bit is checked at 68. If the value of the bit is equal to "1", the state metric of states 0 to (n/2)-l is forced to a low probability as indicated in block 70. Referring back to Figure 7, this is the case shown at time i+1. The incoming bit is known to be a "1" and therefore, the states 0-31 are excluded or, more generally, may have a very low probability. Thus, their metrics are forced to a low probability by, e.g., setting them to the maximum metric among the state metrics calculated at time i+1. That is, when forcing the metric of a state to a low probability, one do not care for the branch metric leading to that state because one directly modifies the result to which the branch leads to. Therefore it does not matter which branch was chosen before as survivor branch in the SELECT step .

[0054] If the value of the pre-known bit at the given time is not "1", or in other words, if the value of the bit is "0", the state metrics of the states n/2 to n-1 at time i+1 are forced to a very low probability. Turning back to Figure 7, this would mean the states 32 to 63 would be excluded

(meaning that they will not have successor states) by, e.g., forcing their metrics to a very low probability at time i+1. In this case, the states accessed by branches indicated by broken lines would be the possible states at time i+1 and the states indicated by solid lines would be the states which metrics would be forced to a very low probability (and which then would typically not have successor states) .

[0055] The forced state metrics according to block 70 or 72 are output at the output 74. Output 74 may be coupled to ACS unit 56. In other words, the changed state metrics (path metrics) are used to replace the corresponding state metrics previously computed by the ACS unit 56. Stated differently, after a normal ACS operation for a (target) state, it is checked whether this state is possible according to an eventually pre-known bit. In case the state is not possible, the state metric of this state is forced to low probability.

[0056] The ACS operation is then processed for the next time step. Given only one message bit is pre-known, there is no pre-knowledge for the bit of the next trellis transition. Thus, in this case, information that there is no pre- knowledge available is received at the second input 62 for the next time step. At 64, it is thus decided that no pre- knowledge is available for this time step. The unchanged state metrics are fed back to ACS unit 56 via output 66.

However, the forced low probability states ("invalid states") of the latest time steps will typically not have successor states, as paths entering these states were deselected

(discarded) by the actual SELECT operation. In Figure 7, these "invalid" states at time step i+2 are exemplarily indicated by the states having the state numbers 0 to 15 and 32 to 47.

[0057] That is, pre-knowledge of one or more, e.g. scattered message bit(s) may improve the decoder performance by

temporarily excluding predecessor states for SELECT

operations. This improves the quality of the survivor paths which are decided by the SELECT operations. The finding of the most likely path out of the survivor paths may then be done conventionally. By way of example, a traceback operation may be initiated to extract all message bits once the trellis processing has reached the end of message length. Other concepts may use pre-known message tail bits, if available, to force the encoder register (and thus the trellis) into a known state, or may use an evaluation of the state metrics of the survivor paths at the end of the message length.

[0058] Figure 9 illustrates in a flow diagram an embodiment of a method for decoding message bits. First, at 90 a

probability value is generated. The probability value

expresses for a candidate sequence of bits the probability to correspond to an original sequence of bits. At 92 the

probability value is forced to a predefined value of low probability based on pre-knowledge. The pre-knowledge may comprise the knowledge that at least one bit out of the candidate sequence of bits is known not to correspond to the respective bit of the original sequence of bits.

[0059] The probability value may also express for a supposed bit the probability (e.g. LLR) to correspond to a defined bit. In this case, at 92, the probability value is forced to a predefined value of low probability based on pre-knowledge. The pre-knowledge may comprise the knowledge that the

supposed bit is known not to correspond to the defined bit.

[0060] Figure 10 illustrates in a flow diagram an embodiment of a method for decoding message bits based on a Viterbi algorithm. At 94 pre-knowledge of at least one message bit is stored. As explained above, the pre-knowledge may be obtained by different ways and may concern different bits out of message bits to be decoded. The pre-knowledge may, e.g., concern a single k-tuple of k consecutive bits, k=l,2,3,... within the message or, e.g., a plurality of such k-tuples of bits scattered across the message, etc. At 96 it is

determined whether the most significant bit of a trellis state at a discrete time i+1 corresponds to a pre-known message bit. The most significant bit at discrete time i is a bit which has just been received. It is a bit which is in fact received between time steps i and i+1, i.e. the bit which is added as most significant bit at time step i+1. For trellis states at a time i+1 for which the most significant bit does not correspond to the value of the stored pre-known message bit, their state metrics are set to a predefined high value .

[0061] Again, the message bits received may be part of an MIB which is received over a PBCH of an LTE mobile

communication system. The pre-knowledge may concern at least one of a message bit indicative of a downlink bandwidth and a message bit indicative of a system frame number. Of course, the pre-knowledge may also concern other message bits.

[0062] Figure 11 shows a graph of a decoding failure rate of PBCH versus a signal-to-noise ratio (SNR) in dB . Line 100 illustrates the results obtainable with a Viterbi decoder according to the prior art ("classic implementation", without pre-knowledge of bits of the MIB) . For example, a failure rate of 10 ^_1 is possible for an SNR of about -7.2 dB . A failure rate of 10 ^~2 is, for example, obtainable at an SNR of about -5.7 dB . A broken line 102 indicates the decoding failure rates obtainable for an embodiment where pre- knowledge of the 3 bits concerning the system bandwidth (BW) in an MIB is used. A decoding failure rate of 10 ^_1 is in this case obtainable for an SNR of about -7.6 dB . A decoding failure rate of 10 ^~2 can be obtained for an SNR of -6.0 dB . A dotted line 104 shows the results for an embodiment in which pre-knowledge of the 3 bits indicating the BW in an MIB and further of the bits of the SFN is used. A decoding failure rate of 10 can then be obtained for an SNR of -8.0 dB . A failure rate of 10 ^~2 can be obtained for an SNR of about -6.3 dB.

[0063] Thus, by using the pre-known bits of the system bandwidth (BW) alone, about 0.4 dB decoding gain can be achieved compared with the classic algorithm. By using the pre-known bits of the BW and pre-known bits of the SFN, about 0.8 dB decoding gain can be achieved compared with the classic algorithm. As such, the Viterbi decoder described herein is better in terms of decoding performance than the classical one. The additional information (i.e. pre-known bits) that effectively excludes certain states in the trellis lowers the decoding error probability and therefore enhances the chance of successfully decoding the PBCH or, more

specifically, in the example given the MIB.

[0064] Furthermore, as explained above, the MIB may be repeated e.g. four times to allow for successful decoding. By enhancing the performance of the PBCH decoding, PBCH decoding can be done more quickly, for example the decoding may be successful already in the first 10 ms so that there is no need to try to decode the PBCH again in the next 10 ms . This allows faster reselection and handover to a new cell, so mobility performance is enhanced.

EXAMPLES

[0065] The following examples pertain to further

embodiments. Example 1 is a decoder configured to decode a forward error correction (FEC) code comprising: a first unit configured to generate a probability value for a candidate sequence of bits to correspond to an original sequence of bits; and a second unit configured to force the probability value to a predefined value of low probability if at least a value of one bit out of the candidate sequence of bits is known not to correspond to a value of the respective bit of the original sequence of bits based on pre-knowledge of the original sequence of bits.

[ 0066] In Example 2, the subject matter of Example 1 can optionally include wherein the bit the value of which does not correspond to a value of the respective bit of the original sequence of bits is the most significant bit of the candidate sequence of bits.

[ 0067 ] In Example 3, the subject-matter of any of Examples 1 and 2 can optionally include wherein the original sequence of bits is part of a control information block received over a physical broadcast channel (PBCH) , in particular a master information block of a long term evolution (LTE) mobile communication system.

[ 0068 ] In Example 4, the subject-matter of any of the preceding Examples can optionally include wherein the second unit is configured to obtain the pre-knowledge from a higher communication level.

[ 0069] In Example 5, the subject-matter of any of the preceding Examples can optionally include wherein the second unit is configured to obtain the pre-knowledge during a cell detection phase.

[ 0070 ] In Example 6, the subject-matter of any of the preceding Examples can optionally include wherein the pre- knowledge concerns at least one of a message bit indicative of a downlink bandwidth and a message bit indicative of a system frame number (SFN) .

[0071] In Example 7, the subject-matter of any of the preceding Examples can optionally include wherein the FEC code is a convolutional code and wherein the decoder is configured to use a Viterbi algorithm.

[0072] In Example 8, the subject matter of Example 7 can optionally include wherein the candidate sequence of bits is a trellis state and the probability value is a state metric of a trellis state.

[0073] In Example 9, the subject-matter of any of Examples 7 and 8 can optionally include wherein the second unit is configured to force the probability value to the predefined value for all those trellis states of a same time for which a value of the at least one bit in the trellis states is known not to be the correct value of the bit.

[0074] In Example 10, the subject-matter of any of Examples 7 to 9 can optionally include wherein the second unit is further configured to force the state metric to a maximum state metric value.

[0075] In Example 11, the subject-matter of any of the preceding Examples wherein the code is one of a turbo code, in particular a Bahl-Cocke-Jelinek-Raviv (BCJR) code, and a low-density parity-check (LDPC) code.

[0076] Example 12 is a Viterbi decoder to decode message bits, the decoder comprising: a pre-knowledge memory

configured to store pre-knowledge of at least one message bit out of the message bits to be decoded; and a forcing unit configured to set a state metric to a predefined high value for all those possible trellis states for which the most significant bit corresponds to a message bit for which pre- knowledge is stored and for which trellis states a value of the most significant bit does not correspond to a value of the message bit according to the pre-knowledge stored.

[0077] In Example 13, the subject-matter of Example 12 can optionally include wherein the message bits are part of a control information block received over a physical broadcast channel (PBCH) , in particular a master information block of a long term evolution (LTE) mobile communication system.

[0078] In Example 14, the subject-matter of Example 13 can optionally include wherein the pre-knowledge concerns at least one of a message bit indicative of a downlink bandwidth and a message bit indicative of a system frame number (SFN) contained in the control information block.

[0079] Example 15 is a Viterbi decoder configured to decode a master information block received over a physical broadcast channel (PBCH) in an LTE mobile communication system, the master information block comprising a plurality of message bits, the Viterbi decoder comprising: a first input

configured to receive a parity bit sequence representing the master information block in convolutional coded form; a second input configured to receive pre-knowledge information about a value of at least one of the message bits; and a metric forcing unit configured to force a metric based on the message bit information received on the second input. [0080] In Example 16, the subject-matter of Example 15 can optionally include wherein the metric forcing unit is further configured to set the metric to a maximum metric for all those possible trellis states for which a value of the most significant bit is known not to correspond to a value of the message bit based on the received pre-knowledge information.

[0081] Example 17 is a method of decoding comprising:

generating a probability value for a candidate sequence of bits to correspond to an original sequence of bits; and forcing the probability value to a predefined value of low probability if at least one bit of the candidate sequence of bits is known not to correspond to the respective bit of the original sequence of bits based on pre-knowledge of the original sequence of bits.

[0082] In Example 18, the subject-matter of Example 17 can optionally include wherein forcing is effectuated if the most significant bit of the candidate sequence of bits is known not to correspond to the respective bit of the original sequence of bits.

[0083] In Example 19, the subject-matter of any of Examples 17 and 18 can optionally include wherein the candidate sequence of bits is a trellis state and the probability value is a state metric in a Viterbi algorithm.

[0084] In Example 20, the subject-matter of any of Examples 17 to 19 can optionally include wherein the original sequence of bits is part of a master information block received over a physical broadcast channel (PBCH) of a long term evolution

(LTE) mobile communication system. [0085] Example 21 is a method for decoding message bits based on a Viterbi algorithm, the method comprising: storing pre-knowledge of at least one message bit of the message bits to be decoded; determining if the most significant bit of a trellis state at a time corresponds to a stored pre-known message bit; and if the most significant bit of the trellis state at the time corresponds to a stored pre-known message bit, then setting the state metrics to a predefined high value for all those trellis states at the time for which a value of the most significant bit does not correspond to a value of the stored pre-known message bit.

[0086] In Example 22, the subject-matter of Example 21 can optionally include wherein the message bits are part of a master information block received over a physical broadcast channel (PBCH) of a long term evolution (LTE) mobile

communication system and the pre-knowledge concerns at least one of a message bit indicative of a downlink bandwidth and a message bit indicative of a system frame number (SFN) .

[0087] Example 23 is a mobile terminal comprising a decoder to decode message bits, the decoder comprising: a pre- knowledge memory configured to store pre-knowledge of at least one message bit out of the message bits to be decoded; and a forcing unit configured to set a state metric to a predefined high value for all those possible trellis states for which the most significant bit is known not to correspond to the message bit based on the stored pre-knowledge.

[0088] In Example 24, the subject-matter of Example 23 can optionally include wherein the pre-knowledge comprises pre- knowledge concerning at least one of a message bit indicative of a downlink bandwidth and a message bit indicative of a system frame number (SFN) .

[0089] Example 25 is a non-transitory computer readable medium comprising program instructions configured to cause a processor to set state metrics to a predefined high value for all those possible trellis states in a decoding process for which the most significant bit is known not to correspond to the message bit to be decoded based on pre-knowledge of the message bit.

[0090] In Example 26, the subject-matter of Example 25 can optionally include wherein the program instructions being further configured to cause the processor to determine whether the most significant bit corresponds to a message bit to be decoded.

[0091] Example 27 is a decoder comprising: a first unit for generating a probability value for a candidate sequence of bits to correspond to an original sequence of bits; and a second unit for forcing the probability value to a predefined value of low probability if at least one bit out of the candidate sequence of bits is known not to correspond to the respective bit of the original sequence of bits based on pre- knowledge of the original sequence of bits.

[0092] In Example 28, the subject-matter of Example 27 can optionally include wherein the not corresponding bit is the most significant bit of the candidate sequence of bits.

[0093] In Example 29, the subject-matter of any of Examples 27 and 28 can optionally include wherein the candidate sequence of bits is a trellis state and the probability value is a state metric in a Viterbi algorithm.

[ 0094 ] In Example 30, the subject-matter of Example 29 can optionally include wherein the second unit for forcing the probability value to the predefined value for all those trellis states at a same time for which the at least one bit in the trellis states is known not to be the correct bit.

[ 0095] Example 31 is a Viterbi decoder for decoding a master information block received over a physical broadcast channel

(PBCH) in an LTE mobile communication system, the master information block comprising a plurality of message bits, the Viterbi decoder comprising: a first input for receiving a parity bit sequence representing the master information block in convolutional coded form; a second input for receiving information about a value of at least one message bit; and a metric forcing unit for forcing a metric based on the message bit information received at the second input.

[ 0096] In Example 32, the subject-matter of Example 31 can optionally include wherein the metric forcing unit for forcing the metric of a trellis state to a maximum metric if the most significant bit of the trellis state is known not to be the correct bit because of the message bit information received on the second input.

[ 0097 ] Example 33 is a most-likelihood decoder comprising a metric unit configured to generate a metric for each of a plurality of possible bits or bit sequences for a specific number of message bits, the metric being indicative of a likelihood of each of the possible bits or bit sequences based on received FEC coded message bits; and a forcing unit configured to force the metric of at least one of the

plurality of possible bits or bit sequences to a specific value indicative for a low likelihood based on pre-knowledge of a message bit value.

[0098] In Example 34, the subject-matter of Example 33 can optionally include that the metric is a log-likelihood ratio.

[0099] In Example 35, the subject-matter of Example 33 can optionally include that the metric is a state metric.

[0100] Example 36 is a method of most-likelihood decoding comprising: generating a metric for each of a plurality of possible bits or bit sequences for a specific number of message bits, the metric being indicative for a likelihood of each of the bits or bit sequences based on received FEC coded message bits; and forcing the metric of at least some of the plurality of possible bits or bit sequences to a specific value indicative of a low likelihood based on a message bit value pre-knowledge.

[0101] In Example 37, the subject-matter of Example 36 can optionally include that the metric is one of a log-likelihood ratio and a state metric.

[0102] While the embodiments have been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the

illustrated examples without departing from the spirit and scope of the appended claims. In particular, with regard to the various functions performed by the above described components or structures, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g. that is functionally equivalent) , even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of invention.