AND METHODS TO FORM THE SAME

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, local volatile filamentary oxide for a magnetic tunnel junction memory device and methods to form the same.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with magnetic tunnel junction (MTJ) devices, e.g., on- chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a MTJ stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, as MTJ devices are scaled down in size decreasing critical switching current density, J _c , required to operate an MTJ memory device becomes important. As such, methods to reduce J _c , by integrating novel materials is an important area of ongoing development.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) coupled with an insulator to metal transition oxide, in accordance with an embodiment of the present disclosure.

Figure IB illustrates a cross-sectional view of individual layers of a synthetic

antiferromagnetic structure, in accordance with an embodiment of the present disclosure.

Figure 2 illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) coupled with an insulator to metal transition oxide, in accordance with an embodiment of the present disclosure.

Figures 3 A-3E illustrate cross-sectional views representing various operations in a method of fabricating a memory device.

Figure 3 A illustrates a cross-sectional view of the formation of a conductive interconnect above a substrate. Figure 3B illustrates a cross-sectional view of the structure in Figure 3 A following the formation of various layers for a magnetic tunnel junction (MTJ) in accordance with an embodiment of the present disclosure.

Figure 3C illustrates a cross-sectional view of the structure in Figure 3B following the formation of various layers in a material layer stack for a memory device in accordance with an embodiment of the present disclosure.

Figure 3D illustrates a cross-sectional view of the structure in Figure 3C following the patterning of the top electrode layer, the material layer stack for the memory device, and the bottom electrode, in accordance with an embodiment of the present disclosure.

Figure 3E illustrates a cross-sectional view of the structure in Figure 3D following the formation of a dielectric spacer on sidewalls of the memory.

Figure 4 illustrates a cross-sectional view of a method for operating a magnetic tunnel junction (MTJ) memory device coupled to a volatile filamentary oxide.

Figure 5 illustrates a cross-sectional view of a magnetic tunnel junction (MTJ) memory device formed on a conductive interconnect coupled to a transistor, in accordance with an embodiment of the present disclosure.

Figure 6 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 7 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

A local volatile filamentary oxide for a magnetic tunnel junction (MTJ) memory device and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations is described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

A memory device based on a magnetic tunnel junction (MTJ) functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. The resistance state of the memory device is defined by a relative orientation of magnetization (direction of magnetization) between a free magnetic layer and a fixed magnetic layer that are separated by a tunnel barrier. When the magnetization of the free magnetic layer and the magnetization of the fixed magnetic layer have orientations that are in the same direction, the memory device is said to be in a low resistance state. Conversely, when the magnetization of the free magnetic layer and the magnetization of the fixed magnetic layer have orientations that are in opposite directions, the memory device is said to be in a high resistance state. In an embodiment, resistance switching is brought about by passing a critical amount of spin polarized current through the MTJ so as to influence orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. The spin polarized current influences the orientation of magnetization by imparting a net spin torque on the magnetization of the free magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need power to maintain an orientation of magnetization, the resistance state of the MTJ is retained even when there is no power applied to the MTJ device. For this reason, MTJ belongs to a class of memory known as non-volatile memory.

Integrating a non-volatile memory device such as an MTJ memory device with an access transistor enables the formation of embedded memory for system on chip applications.

However, approaches to integrate an MTJ memory device onto an access transistor presents challenges that have become far more formidable with scaling. As scaling continues, the need for smaller memory devices to fit into a scaled cell size has driven the industry in the direction of "perpendicular" MTJ device. The word "perpendicular" in pMTJ devices refers to fact that magnetic dipoles in the free and fixed magnets are directed perpendicular to a plane of a substrate above which the MTJ device is formed. When pMTJ devices are scaled down to dimensions of 20nm or less, the threshold spin polarized current density required to switch the magnetization increases. When a pMTJ device is integrated with an access transistor, an increased switching current density can be burdensome and may require multiple access transistors to provide a requisite current. As such, a means by which the critical current density in the MTJ can be increased without imposing additional current requirements from an access transistor is highly desirable. Introduction of one or more layers that can enhance the current density to a free magnetic layer of an MTJ, during operation of the memory device, can enable scaling of pMTJ devices.

In accordance with an embodiment of the present disclosure, a material layer stack for a memory device includes a first electrode, a magnetic tunnel junction disposed above the first electrode, a metallic barrier layer disposed on the MTJ, an insulator-metal transition (EVIT) oxide disposed on the metallic barrier layer and a second electrode disposed above the EVIT oxide. An EVIT oxide belongs is a material that switches between an insulating state (high resistance) and metallic state (low resistance) on application of a voltage bias. When the applied voltage bias is above a threshold voltage, the EVIT oxide is in a low resistance metallic state. Conversely, when the applied voltage bias is turned off, the EVIT oxide is in a high resistance insulating state. Certain types of EVIT oxide materials exhibit a voltage bias dependent insulator to metal transition where the switching between insulating to metal transition occurs along a filamentary path and not via a bulk transition in the oxide material. The filamentary path manifests through a formation of volatile but conductive filament. The term "volatile filament" is used herein to distinguish the filament from other known "non-volatile filaments" that are formed in oxide based resistive random access memory (RRAM) devices. Some examples of EVIT oxides that exhibit volatile filament formation include oxides of elements such as niobium, vanadium, and tantalum.

In an embodiment, when a bias is applied to switch an EVIT oxide from an insulating state to a low resistive state, a localized filament forms in the oxide. The voltage bias shunts current through the filament to form a low resistance state. The filament when formed can have a width between 2nm-4nm and is thus, localized to a very small region. When a current carrying filament is localized to a small region, the current density in the small region can increase greatly. When an EVIT oxide is above and couple to a MTJ, such an increase in current density above a threshold switching current density can switch the direction of magnetization in the free magnetic layer of the MTJ.

For practical considerations an additional layer, such as TiAIN, is inserted between the MTJ and the EVIT oxide. The additional layer of TiAIN is conductive but has an appreciable specific resistivity which limits the spread of the localized burst of current density obtained from the filament formation.

Figure 1A illustrates a cross-sectional illustration of a memory device 100 disposed above a conductive interconnect 101. The memory device 100 includes a bottom electrode 106, a magnetic tunnel junction (MTJ) 108 disposed above the bottom electrode 106, a metallic barrier 110 disposed above the MTJ 108, an insulator-metal transition (EVIT) oxide 112 disposed above the metallic barrier 110 and a top electrode 114 disposed above the EVIT oxide 112.

In an embodiment, the IMT oxide 112 includes a material that exhibits filamentary conduction. In an embodiment, the EVIT oxide 112 includes a material consisting of an oxide of an element selected from the group consisting of niobium, vanadium and tantalum. In an embodiment, the EVIT oxide 112 includes an oxide such as vanadium (IV) oxide, V0 ₂ and vanadium (V) oxide, V2O5, niobium (V) oxide, Nb ₂ 05 and Ta (V) oxide, Ta ₂ 0 ₅ . In an embodiment, the EVIT oxide 112 includes an oxide such as LaSrCuO. In an embodiment, the EVIT oxide 112 is amorphous and has a columnar grain boundary. In another embodiment, the EVIT oxide layer 313 is crystalline. In an embodiment, the EVIT oxide layer 313 is crystalline after an electroforming process as will be described further below, In an embodiment, the EVIT oxide 112 further includes a dopant selected from the group consisting of silver, copper and gold. In an embodiment, the dopant concentration is between 0.1-10% of the total composition of the EVIT oxide 112. A dopant concentration between 0.1-10% facilitates filament conduction.

Reducing the thickness of the EVIT oxide 112 decreases the amount of applied voltage needed for filamentary conduction, but can lead to a breakdown and degradation of a volatile filament. In an embodiment, the EVIT oxide 112 has a thickness between lOnm and 50nm for a stable memory device operation at or above 1.5 V.

In an embodiment, the metallic barrier 110 includes a metal such as titanium and aluminum. In an embodiment, the metallic barrier 110 includes an alloy such as but not limited to TiSiN, TiAl or TiAlN. In an embodiment, the metallic barrier 110 is TiAlN. In an

embodiment, the metallic barrier 110 has a resistivity that is between ImOhm-cm and lOhm-cm when measured at a voltage of approximately 0. IV. A resistivity range between ImOhm-cm and 1 Ohm-cm is desirable so that the metallic barrier 110 can help to minimize spread of charge flow across an entire uppermost surface 130 of the MTJ 108, when the memory device 100 is operated. In an embodiment, when a charge flow is directed to a portion of the uppermost surface 130 of the MTJ 108, current crowding can take place. In an embodiment, current crowding can subsequently increase a spin polarized switching current density through the MTJ 108. In an embodiment, the metallic barrier 110 has a thickness between 2nm-10nm. The specific thickness is dependent on the choice of material and specific resistivity required. In an embodiment, the metallic barrier 110 includes a TiAlN having a thickness between 2nm-4nm.

Referring again to Figure 1 A, in an embodiment, the MTJ 108 includes a fixed magnet 116, a tunnel barrier 118 disposed above the fixed magnet 116 and a free magnet 120 disposed above the tunnel barrier 118. It is to be appreciated that the free magnet 120 is in direct contact with the metallic barrier 110 to benefit from the current crowding effect described above.

During memory device operation, the current crowding effect can increase the spin polarized current density. An increase in the spin polarized current density above a threshold level can switch a magnetization (indicated by arrow 132) in the free magnet 120.

In an embodiment, the free magnet 120 includes cobalt, boron and iron. In an

embodiment, the free magnet 120 of the MTJ 108 includes an alloy such as CoFe or CoFeB. In an embodiment, the free magnet 120 includes a layer of Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnet 120 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In an embodiment the free magnet 120 has a thickness that is between lnm-2.5nm. In an embodiment, free magnet 120 having a thickness between l .Onm and 2.5nm results in the free magnet 120 having a perpendicular magnetic anisotropy.

The tunnel barrier 118 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 118, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 118. Thus, the tunnel barrier 118 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 118 includes an oxide such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 118 is MgO and has a thickness of between lnm and 2nm.

In an embodiment, the fixed magnet 116 includes materials and has a thickness sufficient for maintaining a fixed magnetization. Fixed magnetization indicates that a magnetization (indicated by arrow 134) in the fixed magnet 116 does not change direction during spin transfer torque-current flow. In an embodiment, the fixed magnet 116 includes a magnetic metal such as cobalt, nickel and iron. In an embodiment, the fixed magnet 116 includes an alloy such as CoFe or CoFeB. In an embodiment, the fixed magnet 1 16 includes a layer of Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 116 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In another embodiment the fixed magnet 116 has a thickness that is between 1.5nm- 2.5nm. In an embodiment, a fixed magnet 116 having a thickness between 1.5nm and 2.5nm has perpendicular magnetic anisotropy.

Referring again to Figure 1 A, in an embodiment, the bottom electrode 106 is composed of a material or stack of materials suitable for electrically contacting the fixed magnet 116 side of the MTJ 108. In an embodiment, the bottom electrode 106 includes an amorphous conductive layer. In an embodiment, the bottom electrode 106 is a topographically smooth electrode. In a specific embodiment, the bottom electrode 106 is composed of Ru layers interleaved with Ta layers. In another embodiment, the bottom electrode 106 is TiN. In an embodiment, the bottom electrode 106 has a thickness between 20nm-50nm. In an embodiment, the top electrode 114 includes a material such as Ta or TiN. In an embodiment, the top electrode 114 has a thickness between 30nm-70nm. In an embodiment, the bottom electrode 106 and the top electrode 114 include a same metal such as Ta or TiN.

Referring again to Figure 1 A, the memory device 100 is disposed above a conductive interconnect 101 disposed in an interlayer dielectric 102 formed above a substrate 104. In an embodiment, the conductive interconnect 101 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the interlayer dielectric 102 includes a dielectric layer such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. As illustrated in Figure 1 A, the memory device 100 has a width, WM, and the conductive interconnect 101 has a width Wei. In an embodiment, the memory device 100 has a width, WM, that is less that the width, Wei, of the conductive interconnect 101. In an embodiment, the memory device 100 has a width, WM, that is greater than the width, Wei, of the conductive interconnect 101. In another embodiment, the memory device 100 has a width, WM, that is similar to the width, Wei, of the conductive interconnect 101. In an embodiment, the substrate 104 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 104 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 104. Logic devices such as access transistors may be integrated with memory devices such as memory device 100 to form embedded memory. Embedded memory including one or more memory devices 100 and logic MOSFET transistors can be combined to form functional integrated circuits such as a system on chip (SOC) or a microprocessor.

Figure IB illustrates cross-sectional view of the synthetic antiferromagnetic (SAF) structure 150 in accordance of an embodiment of the present disclosure. In an embodiment, the SAF structure 150 is disposed on the bottom electrode 106 and under the fixed magnet 116 in order to prevent accidental flipping of the magnetization (134) in the fixed magnet 116. In an embodiment, a SAF structure 150 is ferromagnetically coupled with the fixed magnet 116.

In an embodiment, the SAF structure 150 includes a non-magnetic layer 150B between a first ferromagnetic layer 150A and a second ferromagnetic layer 150C as depicted in Figure IB. The first ferromagnetic layer 150A and the second ferromagnetic layer 150C are anti- ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 150A includes a layer of a magnetic metal such as Co, Ni or Fe. In an embodiment, the first ferromagnetic layer 150A includes an alloy such as CoFe, CoFeB, CoFe, FeB. In an

embodiment, the second ferromagnetic layer 150C includes a layer of a magnetic metal such as Co, Ni or Fe. In an embodiment, the second ferromagnetic layer 150C includes an alloy such as CoFe, CoFeB, CoFe, FeB. In an embodiment, the non-magnetic layer 150B includes a ruthenium or an iridium layer. In an embodiment, a ruthenium based non-magnetic layer 150B has a thickness between 4-9 Angstroms to ensure that the coupling between the first

ferromagnetic layer 150A and the second ferromagnetic layer 150C is antiferromagnetic in nature.

In an embodiment, the SAF structure 150 includes a bilayer having a magnetic metal disposed on a non-magnetic metal such as a bilayer of Co/Pd or a bilayer of Co/Pt. In an embodiment, the SAF structure 150 includes a stack of bilayers, where each bilayer includes a magnetic metal disposed on a non-magnetic metal, where the total number of bilayers can range from 2-10.

In an embodiment, an additional layer of non-magnetic spacer material may be disposed between the SAF structure 150 and the fixed magnet 116. In an embodiment, a layer of nonmagnetic spacer material may include a metal such as Ta, Ru or Ir. In an embodiment, the thickness of the layer of non-magnetic spacer material is greater than 0. lnm but less than

0.23nm. A non-magnetic spacer material having a thickness greater than 0. lnm but less than 0.23nm can enable ferromagnetic coupling between the SAF structure 150 and the fixed magnet 116.

Figure 2 illustrates a cross-sectional view of a memory device 200 in accordance with an embodiment of the present disclosure. In an embodiment, the memory device 200 includes an FMT oxide 202 disposed on the bottom electrode 106, a metallic barrier 204 disposed on the FMT oxide 202 and a magnetic tunnel junction (MTJ) 206 disposed on the metallic barrier 204. In an embodiment, the MTJ 206 further includes a free magnet 208, a tunnel barrier 210 disposed on the free magnet 208 and a fixed magnet 212 disposed on the tunnel barrier 210. It is to be appreciated that ordering of the individual layers of the MTJ 206 is reversed relative to the individual layers of the MTJ 108. To extract benefit from current crowding during device operation, the free magnet 208 is directly on the metallic barrier 204.

In an embodiment, the IMT oxide 202 includes a material and has a thickness that is substantially similar to the material and thickness of the FMT oxide 112. In an embodiment, the metallic barrier 204 includes a material and has a thickness that is substantially similar to the material and thickness of the metallic barrier 110. In an embodiment, the free magnet 208 includes a material and has a thickness that is substantially similar to the material and the thickness of the free magnet 120. In an embodiment, the fixed magnet 212 includes a material and has a thickness that is substantially similar to the material and the thickness of the fixed magnet 116. In an embodiment, a SAF structure 150 is disposed between the fixed magnet 212 and the top electrode 114 to enable pinning of magnetization in the fixed magnet 212.

Additional non-magnetic spacer layers may be disposed between the SAF structure 150 and the fixed magnet 212 to ensure ferromagnetic coupling between the SAF structure 150 and the fixed magnet 212.

Figures 3 A-3E illustrate cross-sectional views representing various operations in a method of fabricating a MTJ device coupled to a local volatile filamentary oxide.

Figure 3 A illustrates a bottom electrode layer 303 formed on a conductive interconnect 302 surrounded by a dielectric layer 301 formed above a substrate 300.

In an embodiment, the substrate 300 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 300 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

In an embodiment, the conductive interconnect 302 is formed in a dielectric layer 301 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 302 includes a barrier layer, such as titanium nitride, ruthenium, tantalum, tantalum nitride, and a fill metal, such as copper, tungsten. In an embodiment, the conductive interconnect 302 is fabricated using a subtractive etch process when materials other than copper are utilized. In one such embodiment, the conductive interconnect 302 includes a material such as but not limited to titanium nitride, ruthenium, tantalum, tantalum nitride. In an embodiment, the dielectric layer 301 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 301 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 302. In an embodiment, the dielectric layer 301 has a total thickness between 70nm-300nm. In an embodiment, conductive interconnect 302 is electrically connected to a circuit element such as an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory.

In an embodiment, the bottom electrode layer 303 is then blanket deposited onto an uppermost surface of the conductive interconnect 302 and onto an uppermost surface of the dielectric layer 301. In an embodiment, the bottom electrode layer 303 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the bottom electrode layer 303 includes a metal such as but not limited to W, Ru, Ti or Ta or an alloy such as but not limited to WN, TiN or TaN. In an embodiment, the bottom electrode layer 303 is deposited to a thickness between 20nm to 30nm.

In an embodiment the bottom electrode layer 303 is first blanket deposited on an uppermost surface of the conductive interconnect 302 and on an uppermost surface of the dielectric layer 301, and subsequently polished to achieve a surface roughness of lnm or less. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process to form a topographically smooth uppermost surface having a surface roughness of less than lnm. A surface roughness of less than lnm is sufficient to enable a subsequent fixed magnetic layer and a tunnel barrier layer to be formed with well-ordered crystal planes.

In an embodiment, a material layer stack to form a SAF structure such as a SAF structure 150 is also formed (not shown) after forming the bottom electrode layer 303.

Figure 3B illustrates a cross-sectional view of the structure in Figure 3 A following the formation of various layers of a material layer stack for a MTJ device, in accordance with an embodiment of the present disclosure.

In an embodiment, a fixed magnetic layer 305 is deposited on an uppermost surface of the bottom electrode layer 303. In an embodiment, the fixed magnetic layer 305 is blanket deposited using a physical vapor deposition (PVD) process. The PVD deposition process ensures that the fixed magnetic layer 305 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate. In an embodiment, a fixed magnetic layer 305 deposited by a PVD process is amorphous in nature. In an embodiment, the fixed magnetic layer 305 includes cobalt, boron and iron. In an embodiment, the fixed magnetic layer 305 includes an alloy such as but not limited to CoFe, CoFeB or FeB. In an embodiment, fixed magnetic layer 305 includes a layer of Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent. In an embodiment, X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnetic layer 305 is blanket deposited to a thickness between 1.5nm-2.5nm to have a perpendicular magnetic anisotropy.

Atunnel barrier layer 307 is then blanket deposited on the fixed magnetic layer 305. In an embodiment, the tunnel barrier layer 307 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 307 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the MgO is deposited to a thickness between 0.8nm to lnm. In an embodiment, the reactive sputter deposition process is carried out in a manner that yields a tunnel barrier layer 307 having a mostly crystalline structure. In another embodiment, the tunnel barrier layer 307 is not crystalline as deposited, but becomes highly crystalline after an anneal process.

A free magnetic layer 309 is deposited on the tunnel barrier layer 307. In an

embodiment, the free magnetic layer 309 is blanket deposited using a physical vapor deposition (PVD) process. The PVD deposition process ensures that the free magnetic layer 309 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate. In an embodiment, a free magnetic layer 309 deposited by a PVD process is amorphous in nature. In an embodiment, the free magnetic layer 309 includes an alloy such as but not limited to CoFeB and FeB that is amorphous as deposited. In an embodiment, free magnetic layer 309 includes a layer of Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnetic layer 309 is FeB, where the concentration of boron is between 10-40 atomic percent of the total

composition of the FeB alloy. In an embodiment, a free magnetic layer 309 including an alloy of a magnetic metal and boron is deposited with a boron content of 10-20% to be amorphous as- deposited. In an embodiment, free magnetic layer 309 is deposited to a thickness between 1.0nm-2.5nm. Exemplary thickness of the free magnetic layer 309 is between 1.3nm- 2.3nm.

Figure 3C illustrates a cross-sectional view of the structure in Figure 3B following the formation of a metallic barrier layer 311 on the free magnetic layer 309 and the formation of an EVIT oxide layer 313 on the metallic barrier layer 311. In an embodiment, the metallic barrier layer 311 includes a metal such as titanium and aluminum. In an embodiment, the metallic barrier layer 311 includes an alloy such as TiAl or TiAlN. In an embodiment, the metallic barrier layer 311 has a resistivity that is between ImOhm-cm and lOhm-cm when measured at a voltage of approximately 0. IV. The resistivity range of ImOhm-cm and 1 Ohm-cm is desirable so that the metallic barrier layer 311 can help to concentrate charge flow to a portion of the surface area of the free magnetic layer 309, when a subsequent memory device is fabricated and operated. In an embodiment, the metallic barrier layer 311 has a thickness between 3nm and lOnm. The specific thickness is dependent on the choice of material and a resistivity required.

Referring again to Figure 3C, an EVIT oxide layer 313 is then deposited on the metallic barrier layer 311. In an embodiment, depending on the choice of material, the metallic barrier layer 311 is blanket deposited using a reactive sputtering, magnetron sputtering or an atomic layer deposition process. In an embodiment, the IMT oxide layer 313 includes a material consisting of an oxide of an element selected from the group consisting of niobium, vanadium and tantalum. In an embodiment, the EVIT oxide layer 313 is amorphous as deposited and has a columnar grain boundary. In another embodiment, the IMT oxide layer 313 is crystalline as deposited. In an embodiment, the IMT oxide layer 313 is crystalline after an electroforming process as will be described further below. In an embodiment, the IMT oxide layer 313 is in a monoclinic phase (insulating) or in a rutile phase (metallic) after an electroforming process.

In an embodiment, the IMT oxide layer 313 includes an oxide such as vanadium (IV) oxide, V0 ₂ and vanadium (V) oxide, V2O5, niobium (V) oxide, Nb ₂ 05 and Ta (V) oxide, Ta ₂ 0 ₅ . In an embodiment, the IMT oxide layer 313 includes an oxide such as LaSrCuO. In an embodiment, the EVIT oxide layer 313 further includes a dopant selected from the group consisting of silver, copper and gold. In an embodiment, the dopant concentration is between 0.1%-10% of the total composition of the EVIT oxide layer 313. In an embodiment, the EVIT oxide layer 313 is deposited to a thickness between lOnm and 50nm. hi an embodiment, the fixed magnetic layer 305, the tunnel barrier layer 307, the free magnetic layer 309, the metallic barrier layer 311 and the EVIT oxide layer 313 form a memory device stack 360 for a memory device.

Referring again to Figure 3C, in an embodiment, a top electrode layer 315 is deposited on the surface of the EVIT oxide layer 313. In an embodiment, the top electrode layer 315 includes a material suitable to act as a hardmask for etching the memory device stack 360 and the bottom electrode layer 303. In an embodiment, the top electrode layer 315 includes a material such as Ta. In an embodiment, the thickness of the top electrode layer 315 ranges from 30nm-70nm.

In an embodiment, after deposition of the memory device stack 360 and the top electrode layer 315, an anneal is performed. In an embodiment, the anneal is performed under conditions well known in the art to promote solid phase epitaxy of the free magnetic layer 309 following a template of a crystalline layer of the tunnel barrier layer 307. In an embodiment, a post- deposition anneal of the layers in the MTJ material layer stack 350 is carried out in a furnace at a temperature between 300-400 degrees Celsius. In an embodiment, the anneal is carried out in a forming gas environment. In an embodiment, the anneal is performed immediately post deposition but before patterning of the memory device stack 360 to enable a crystalline MgO- tunnel barrier layer 307 to be formed. The post-deposition anneal process also enables boron to diffuse away from an interface 323 between the tunnel barrier layer 307 and the free magnetic layer 309. The process of diffusing boron away from the interface 323 enables lattice matching between the free magnetic layer 309 and the tunnel barrier layer 307. In an embodiment, the process of boron out-diffusion enables an as-deposited amorphous free magnetic layer 309 including boron to form a (001) crystal structure by templating off of a (001) crystal structure of the tunnel barrier layer 307.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 305 and the free magnetic layer 309. An applied magnetic field that is directed parallel to a vertical axis of the memory device stack 360, during the annealing process, enables a perpendicular magnetic anisotropy to be set in the fixed magnetic layer 305 and in the free magnetic layer 309. The annealing process initially aligns the magnetization of the fixed magnetic layer 305 and the free magnetic layer 309 to be parallel to each other.

In an embodiment, the anneal process can also be performed after capping the MTJ material layer stack 350 with the metallic barrier layer 311 but prior to formation of the EVIT oxide layer 313.

Figure 3D illustrates a cross-sectional view of the structure in Figure 3C following an etch process to pattern the top electrode layer 315, the memory device stack 360, and the bottom electrode layer 303. In an embodiment, a layer photoresist (not shown) is formed above the top electrode layer 315. In an embodiment, the photoresist is patterned using well known lithographic processes known in the art. The lithography process defines the shape and size of a memory device and a location where the memory device is to be formed with respect the conductive interconnect 302. In an embodiment, the top electrode layer 315 is first patterned to form a top electrode 316 and the etch is stopped when an uppermost surface of the EVIT oxide layer 313 is exposed. The photoresist is then removed. In an embodiment, a subsequent plasma etch process is utilized to pattern the remaining layers in the memory device stack 360 and the bottom electrode layer 303 to form a memory device 370. In an embodiment, the plasma etch process utilized to etch the memory device stack 360 forms an EVIT oxide 314, a metallic barrier 312, magnetic tunnel junction(MTJ) 352 and a bottom electrode 304. The MTJ 352 includes a free magnet 310, a tunnel barrier 308, and a fixed magnet 306. In an embodiment, almost 30- 70% of the as deposited top electrode layer 315 may be consumed during the complete etch process. In an embodiment, the plasma etch forms a memory device 370 with a tapered profile (indicated by dashed lines 361).

Figure 3E illustrates a cross-sectional view of the memory device 370 in Figure 3D following the formation of a dielectric spacer 380 on the sidewalls of the top electrode 316, memory device stack 360, on sidewalls of the bottom electrode 304, and on an uppermost surface of the dielectric layer 301. In an embodiment, a dielectric spacer layer is deposited immediately following the plasma etch process utilized to form the memory device 370. In an embodiment, the dielectric spacer layer is deposited immediately following the plasma etch process without breaking vacuum.

In an embodiment, the dielectric spacer layer includes a material such as silicon nitride, silicon dioxide or carbon doped silicon nitride. In an embodiment, the dielectric spacer layer is chosen to exclude oxygen containing material to prevent oxidation of magnetic layers after the clean-up etch process. In an embodiment, the dielectric spacer layer is deposited at a process temperature between 25-300 degrees Celsius. In an embodiment, the dielectric spacer layer is deposited to a thickness between 5nm-20nm. In an embodiment, the dielectric spacer layer is etched by a plasma etch process to form a dielectric spacer 380 on sidewalls of the memory device 370. In an embodiment, the etch process may cause an uppermost portion of the dielectric layer 301 to become partially recessed.

In an embodiment, a second anneal process can be performed after formation of the memory device 370. In an embodiment, the second anneal process is carried out at a process temperature of at least 300 degrees Celsius but less than 400 degrees Celsius. In an embodiment, the post process anneal can help to recrystallize sidewalls of the tunnel barrier 308 that may have become potentially damaged during the etching process utilized to form the memory device 370.

The various process operations described in association with Figures 3B-3E can also be utilized to form a material layer stack to fabricate the memory device 200 depicted in Figure 2, although details of the sequences are not described here.

Figure 4 illustrates a plot of a current-voltage characteristic during the operation of a memory device such as the memory device 370 and states of the EVIT oxide 314 and the MTJ 352 at different points in the current-voltage cycle. The memory device 370 includes the EVIT oxide 314 coupled to the MTJ 352. In an embodiment, the memory device 370 undergoes a one- time electroforming process. In an embodiment, the EVIT oxide 314 is in an amorphous state and the electroforming process changes the EVIT oxide 314 to a monoclinic crystalline state. When the EVIT oxide 314 is in the monoclinic crystalline state, the EVIT oxide 314 is in an insulating state but the electrical resistance is orders of magnitude less than an electrical resistance of the EVIT oxide 314 in an amorphous state.

At the onset of the voltage cycling process (point A), the memory device 370 is in a high resistance state. The direction of magnetization 410 in the free magnet 310 is opposite to the direction of magnetization 412 in the fixed magnet 306. Referring to the plot in Figure 4, the cycling of the memory device 370 begins by applying a first voltage to the EVIT oxide 314 that is directly on and electrically coupled to the MTJ 352. The first voltage has a positive polarity and is increased from a value of 0V (point A on I-V plot) to a threshold voltage, VTH (point B). In an embodiment, threshold voltage, VTH, is between 1.0V and 1.5V.

Once threshold voltage, VTH, is reached a conductive filament 402 forms in the EVIT oxide 314 as is depicted in the cross-sectional illustration of memory device 370 (at point B). In an embodiment, the EVIT oxide 314 is transformed to a rutile phase and promotes the formation of the conductive filament 402. hi an embodiment, the filament 402 is formed in the middle of the EVIT oxide 3 14. In other embodiments, the filament 402 is formed away from the middle of the EVIT oxide 3 14.

Once the conductive filament 402 forms in the EVIT oxide 3 14, current begins to flow into the MTJ 352 through the metallic barrier 3 12. Due to a relatively high resistance of the metallic barrier 3 12, the current does not diffuse throughout a volume of the metallic barrier 3 12, but is concentrated in the vicinity of where the filament is formed. More specifically, the free magnet 3 10 directly in contact with the metallic barrier 3 12 receives a burst of current over a small area (indicated by lines 414). The current spreads out (indicated by the lines 414) in the free magnet 3 10, but the initial burst of current has a current density sufficiently large enough to impart spin transfer torque to magnetization 410 in a portion of the free magnet 3 10 to start a magnetization switching process but not enough to complete the switching.

Increasing the magnitude of the first voltage, beyond VTH, increases the magnitude of the current flow through the MTJ 352. At a voltage VSET, the current density through the MTJ 352 reaches a critical level and induces the magnetization 410 in the free magnet 3 10 to change direction, as is depicted in the cross-sectional illustration of memory device 370 (at point D). In an embodiment, the set voltage, VSET, is between 1.8V and 2.4V. The MTJ 352 changes state from a high resistance state to a low resistance state (at point D). As the magnitude of the first voltage is decreased (from point D to point E) to the previous threshold voltage, VTH, the current flow in the memory device 370 decreases. When the first voltage falls below VTH, (point B to A), the conductive filament 402 dissolves (not illustrated) and current flow through the memory device 370 is stopped. In an embodiment, the conductive filament 402 does not dissolve completely, but becomes insulating as the EVIT oxide 3 14 changes to a monoclinic state. On the return path through point A, it is to be appreciated that the MTJ 352 is a low resistance state and despite turning off the voltage the memory state in the MTJ 352 does not change.

The voltage cycling process is resumed by applying a second voltage to the EVIT oxide

3 14. The second voltage has a negative polarity and is increased in magnitude (from point A on I-V plot) to a threshold voltage, -VTHR (point F). In an embodiment, threshold voltage, -VTHR, is between - 1.0V and -1.5V. By reversing the voltage polarity of the second voltage the direction of current flow is reversed through the memory device 370.

Once threshold voltage, -VTHR, is reached a filament 403 forms in the EVIT oxide 3 14 as is depicted in the cross-sectional illustration of memory device 370 (at point F). Once the filament 403 is formed in the EVIT oxide 3 14, current begins to flow into the MTJ 352 through the metallic barrier 3 12. Due to a relatively high resistance of the metallic barrier 3 12, the current does not diffuse throughout a volume of the metallic barrier 3 12, but is concentrated in the vicinity of where the conductive filament 403 is formed. More specifically, the free magnet 3 10 directly in contact with the metallic barrier 3 12 receives a burst of current over a small area. The current spreads out (indicated by the lines 414) in the free magnet 3 10, but the initial burst of current has a current density sufficiently large enough to impart spin transfer torque to magnetization 410 in a portion of the free magnet 3 10 to start a magnetization reversal process but not enough to complete the switching.

Increasing magnitude of the second voltage, beyond -VTHR, increases the magnitude of the current flow through the MTJ 352. At a voltage -VRESET, the current density through the MTJ 352 reaches a critical level and induces the magnetization 410 in the free magnet 3 10 to change direction. The MTJ 352 changes state from a low resistance state to a high resistance state, as is depicted in the cross-sectional illustration of memory device 370 (at point H). In an embodiment, the set voltage, -VRESET, is between than - 1 .8V and -2.4V. As the magnitude of the second voltage is decreased (from point H to point F) to the previous threshold voltage, -VTHR, the current flow in the memory device 370 decreases. When the magnitude of the second voltage is reduced below -VTHR, (point F to A), the conductive filament 402 dissolves (not illustrated) and current flow through the memory device 370 is stopped. In an embodiment, the filament 403 does not dissolve, but becomes insulating as the EVIT oxide 3 14 changes to a monoclinic state.

It is to be appreciated that the burst in current density from the current crowding effect in the metallic barrier 3 12 enables the memory device 370 to switch at a lower net threshold switching current, ISET or IRESET. In the absence of the EVIT oxide 3 14, the memory device 370 would have threshold switching currents, ISET or IRESET that would be higher. Lowering the threshold switching current enables the memory device 370 to be more stable over the lifetime of the memory device 370.

Figure 5 illustrates a cross-sectional view of a memory device, such as the memory device 370 formed on a conductive interconnect 302 coupled to an access transistor 508, in accordance with an embodiment. In an embodiment, the memory device 370 includes the bottom electrode 304, the fixed magnet 306, the tunnel barrier 308 such as an MgO, the free magnet 3 10, the metallic barrier 3 12, the EVIT oxide 3 14 and the top electrode 3 16. In an embodiment, a magnetic tunnel junction (MTJ) contact 526 is disposed on the top electrode 3 16. In an embodiment, the memory device 370 has a width, WM, that is greater than a width, Wei, of the conductive interconnect 302. In one such embodiment, a portion of the bottom electrode 304 of memory device 370 is also disposed on a dielectric layer 503. In an embodiment, the memory device 370 has a width less than the width of the conductive interconnect 302. In an

embodiment, the memory device 370 has a width equal to the width of the conductive interconnect 302. In an embodiment, the conductive interconnect 302 is disposed on a contact structure 504 that is above and electrically coupled with a drain region 506 of an access transistor 508 disposed above a substrate 510.

In an embodiment, the underlying substrate 510 represents a surface used to manufacture integrated circuits. Suitable substrate 510 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 510 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 508 associated with substrate 510 are metal- oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 510. In various implementations of the disclosure, the access transistor 508 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, the access transistor 508 of substrate 510 includes a gate stack formed of at least two layers, a gate dielectric layer 514 and a gate electrode layer 512. The gate dielectric layer 514 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 514 to improve its quality when a high-k material is used.

The gate electrode layer 512 of the access transistor 508 of substrate 510 is formed on the gate dielectric layer 514 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 512 with a workfunction that is between about 4.9 eV and about 4.2 eV. For an MOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 512 with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode layer 512 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode layer 512 may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 512 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the disclosure, a pair of sidewall spacers 516 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 516 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 518 and drain region 506 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 518 and drain region 506 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 518 and drain region 506. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 518 and drain region 506. In some implementations, the source region 518 and drain region 506 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in-situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 518 and drain region 506 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 518 and drain region 506.

In an embodiment, a gate contact 520 and a source contact 522 are formed in a second dielectric layer 524 and in the dielectric layer 503 above the gate electrode layer 512 and source region 518, respectively.

Figure 6 illustrates a computing device 600 in accordance with one embodiment of the disclosure. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 6G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory devices, such as a memory device 370, fabricated using a memory device stack 360 in accordance with

embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes a magnetic tunnel junction memory device elements such as memory device 370 integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device 600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements such as memory device 370, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Figure 7 illustrates an integrated circuit (IC) structure 700 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 700 is an intervening structure used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer mother, or another integrated circuit die. The memory module may include one or more memory devices such as a memory device 100 or a memory device 370. Generally, the purpose of an integrated circuit (IC) structure 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the integrated circuit (IC) structure 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the integrated circuit (IC) structure 700. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 700.

The integrated circuit (IC) structure 700 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 700 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a

semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure 700 may include metal interconnects 708 and via 710, including but not limited to through-silicon vias (TSVs) 710. The integrated circuit (IC) structure 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, memory device such as memory devices 100 and 370, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 700. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 700.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a memory device 370. A large array of consisting of memory device 370 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include a local volatile filamentary oxide for a magnetic tunnel junction memory device and methods to form the same.

Specific embodiments are described herein with respect to magnetic tunnel junction memory device. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, certain class of oxide based resistive random access memory devices, and spin torque transfer memory (STTM) devices such as in-plane STTM or

perpendicular STTM devices.

Example 1 : A memory device includes a first electrode, a magnetic tunnel junction device disposed above the first electrode, a metallic barrier layer disposed above the magnetic tunnel junction (MTJ) memory device, an insulator-metal transition (JJVIT) oxide disposed above the metallic barrier layer, and a second electrode disposed above the JJVIT oxide.

Example 2: The memory device of example 1, wherein the JJVIT oxide includes a material that exhibits filamentary conduction.

Example 3 : The memory device of example 1 or 2, wherein the JJVIT oxide includes a material consisting of an oxide of an element selected from the group consisting of niobium, vanadium and tantalum.

Example 4: The memory device of example 1, 2 or 3, wherein the JJVIT oxide further includes a dopant selected from the group consisting of silver, copper and gold.

Example 5: The memory device of example 4, wherein the dopant concentration is between 0.1% to 10% of the total composition of the JJVIT oxide.

Example 6: The memory device of example 1, 2 or 3, wherein the JJVIT oxide has a thickness between lOnm and 50nm.

Example 7: The memory device of example 1, wherein the metallic barrier layer includes

Ti and Al, a material selected from the group consisting of TiAl and TiAlN.

Example 8: The memory device of example 1 or 7, wherein the metallic barrier layer has a resistivity that is between ImOhm-cm and 1 Ohm-cm when measured at a voltage of approximately 0.1V.

Example 9: The memory device of example 1, 7 or 8, wherein the metallic barrier layer has a thickness between 3nm and lOnm.

Example 10: The memory device of example 1, wherein the MTJ memory device includes, a fixed magnet, a tunnel barrier above the fixed magnet, and a free magnet above the tunnel barrier.

Example 11 : A method to fabricate a memory device includes forming a conductive electrode above a substrate. The method further includes forming a bottom electrode on the conductive interconnect. The method further includes forming a material layer stack for a magnetic tunnel junction (MTJ) memory device on the bottom electrode. The method further includes forming a metallic barrier layer on the material layer stack for an MTJ memory device. The method further includes forming an insulator-metal transition (JJVIT) oxide layer on the metallic barrier layer, wherein the forming includes sputter depositing an oxide of an element selected from the group consisting of niobium, vanadium and tantalum. The method further includes forming a top electrode layer on the JJVIT oxide layer. The method further includes patterning the top electrode layer to form a top electrode and patterning the JJVIT oxide layer after patterning the top electrode layer to form an JJVIT oxide. The method further includes patterning the metallic barrier layer to form a metallic barrier, patterning the material layer stack to form a MTJ memory device, and patterning the bottom electrode layer to form a bottom electrode.

Example 12: The method of example 1 1 , wherein forming the EVIT oxide layer further includes doping with one or more elements selected from the group consisting of silver, copper and gold wherein the total amount of the one or more elements is between 0. 1% to 10% atomic percent of the total composition of the EVIT oxide layer.

Example 13 : The method of example 1 1 , wherein forming the material layer stack for a MTJ memory device includes, forming a fixed magnetic layer above the bottom electrode, forming a tunnel barrier layer above the fixed magnetic layer, and forming a free magnetic layer on the tunnel barrier layer.

Example 14: The method of example 1 1 , wherein forming the memory device includes annealing the material layer stack for the magnetic tunnel junction (MTJ) memory device at a temperature between 350-400 degrees Celsius prior to deposition of the EVIT oxide layer.

Example 15 : A method of operating a memory device includes applying a first voltage to an EVIT oxide directly on and electrically coupled to a magnetic tunnel junction (MTJ) memory device to induce a first concentrated charge flow through a portion of the IMT oxide and into a portion of the MTJ memory device. The method further includes increasing magnitude of the first voltage to increase magnitude of the first concentrated charge flow to change a memory state of the MTJ memory device from a first memory state to a second memory state and decreasing the magnitude of the first voltage to stop the first concentrated charge flow. The method further includes applying a second voltage to the EVIT oxide to induce a second concentrated charge flow in a portion of the EVIT oxide and into a portion of the MTJ memory device and increasing magnitude of the second voltage to increase magnitude of second concentrated charge flow to change the memory state of the MTJ memory device from the second memory state back to the first memory state.

Example 16: The method of example 15, wherein the first voltage has a positive polarity and the second voltage has a negative polarity.

Example 17: The method of example 15, wherein the first concentrated charge flow has a first direction and the second concentrated charge flow has a second direction, wherein the first direction is opposite to second direction.

Example 18 : The method of example 15, wherein the first charge flow is induced in the EVIT oxide by applying a threshold voltage, VTH, where VTH is between 1.0V and 1.5V.

Example 19: The method of example 18, wherein the memory state of the MTJ memory device is changed from the first memory state to the second memory state by applying a set voltage, VSET, where VSET is greater VTH. Example 20: The method of example 19, wherein the set voltage, VSET, is between than 1.8V and 2.4V.

Example 21 : The method of example 15, wherein the first voltage is decreased to a value near the threshold voltage, VTH to stop the first concentrated charge flow, after changing the memory state of the MTJ memory device to the second memory state.

Example 22: The method of example 15, wherein the second charge flow is induced in the EVIT oxide by applying a threshold voltage, -VTHR, where -VTHR is between - 1.0V and -1.5V.

Example 23 : The method of example 22, wherein the memory state of the MTJ memory device is changed from the second memory state to the first memory state by applying a reset voltage, -VRESET, where -VRESET has a magnitude greater than a magnitude of the threshold voltage -VTHR.

Example 24: The method of example 23, wherein the reset voltage, -VRESET, is between - 1.8V and -2.4V.