TECHNICAL FIELD

The disclosure relates to a voltage buffer and to an amplifier circuit. The disclosure further relates to a device comprising an analog electrical circuit and a digital electrical circuit, the analog electrical circuit comprising a voltage buffer.

BACKGROUND

The disclosure is in the field of voltage buffers. In particular, the disclosure is directed to a voltage buffer for electrically connecting an analog electrical circuit supplied by a first supply voltage to an input of a digital electrical circuit, the digital electrical circuit being supplied by a second supply voltage that is lower than the first supply voltage.

SUMMARY

Embodiments of the invention have been motivated by the following considerations made by the inventors:

The requirement of high data-rate communications increases the demand of broadband transimpedance amplifiers (TIAs) and drivers, in which signal bandwidth in the order of tens of GHz are processed. In optical communication system, at least one TIA is typically mounted on a complex electro-optical module (E/O module) together with at least one photo-diode (PD), and a digital chip, the digital chip may comprise an analog-to-digital converter (ADC) and a digital signal processor (DSP). Such an E/O module is exemplarily shown in Figure 15. The E/O module 201 of Figure 15 comprises at least one PD 204 electrically connected to an input 202b of an analog section 202 or analog electrical circuit 202 of the E/O module 201. The term “electrically connected” may be abbreviated by the term “connected”. The analog electrical section 202 may correspond to an analog chip. The analog section 202 comprises at least one TIA 202a. In particular, the at least one PD 204 is connected to an input of the at least one TIA 202a. The E/O module 201 further comprises a digital section 203 that comprises an ADC 203a and a DSP 203b. The digital section 203 may be a digital chip.

The analog section 202 and digital section 203 of the E/O module 201 are typically implemented in different technologies. Thus, while the analog supply voltage for supplying the analog section 202 is typically about 3.3 V (or above), the digital supply voltage for supplying the digital section

203 is approximately IV (or below). In other words, the analog section 202 is supplied by a first supply voltage and the digital section 203 is supplied by a second supply voltage that is lower than the first supply voltage. For this reason, off-chip decoupling capacitors 205 are used to provide AC coupling with a cutoff frequency below 1 MHz. That is, an output of 202c of the analog section 202 is connected via decoupling capacitors 205 to an input 203 of the digital section 203 for electrically connecting the analog section 202 with the digital section 203. Such decoupling capacitors 205 are usually bulky in order to achieve a sufficient AC coupling. However, as system bandwidth increases, the use of bulky off-chip decoupling capacitors 205 causes significant losses and reduces the availability of suitable packaging options. As a result, the electrical connection of the analog section 202 and the digital section 203 via AC coupling capacitors 205 is disadvantageous.

A typical output amplifier stage (or output gain stage) made of a cascoded differential pair with a resistive load in BiCMOS technology is shown in Figure 16. The terms “amplifier stage” and “gain stage” may be used as synonyms. Such an output amplifier stage may be an output stage of the analog section 202 of the E/O module 201 of Figure 15. As shown in Figure 16, each circuit branch of the amplifier stage may comprise a resistor Ri _oad and two bipolar junction transistors (BJTs), wherein the emitter terminal of a first BJT is connected to a collector terminal of a second BJT of a respective circuit branch. The collector terminal of the first BJT of each circuit branch is connected via the respective resistor Ri _oa d to a supply terminal for supplying a supply voltage avdd. The emitter terminal of the second BJT of each circuit branch is connected with a bias current source for providing a bias current Ibias,drv. The term “current generator” may be used as a synonym for “current source”. A voltage v _casc may be provided to the two base terminals of the two first BJTs. A respective input voltage Vm, _P or Vm,m is provided to the base terminal of each second BJT. A respective output voltage Vdiv.p or Vdiv.m is provided at each node between the resistor Ri _oa and the first BJT of each circuit branch. The output voltages Vdiv.p and Vdrv.m may form the output voltage of the analog section 202 (comprising the amplifier stage of Figure 16 as output stage) of the E/O module of Figure 15, as indicated in Figure 16 by the dashed line labelled with “off-chip” that indicates the output 202c of the analog section 202. The amplifier stage is connected to a digital section, such as the digital section 203 of the E/O module 201 of Figure 15, via decoupling capacitors which correspond to the decoupling capacitors 205 of Figure 15. The input of the digital section is indicated in Figure 16 by the dashed line labelled with “digital chip”. The amplifier stage of Figure 16 is configured to provide a DC voltage vdcin,digitai to the digital section. For an output amplifier stage as shown in Figure 16, main requirements are a wide bandwidth (from DC to tens of GHz); a matched output (i.e. 50 Q single-ended); a linear gain with large output swings; and a gain greater than or equal to one (Gain > 1) or greater than or equal to 0 dB (Gain > 0 dB) to relax the linearity requirements of previous stages (previous amplifier stages). The term “gain stage” may be used as a synonym for the term “amplifier stage”. In order to have a well matched input impedance of the digital section, the input impedance is 50 Q or about 50 Q, as indicated in Figure 16. In order to have a well matched output impedance of the output amplifier stage from low frequency, the resistor Ri _oa d is 50 Q or about 50 Q. Thus, the DC output voltage Vdrv of a respective circuit branch of the output amplifier stage of Figure 16 may be computed as: v _drv = avdd

Such DC output voltage Vd _re is typically set around 2 V to 2.5 V to avoid compression of heterojunction bipolar transistor (HBT) devices in the case of large output swings, assuming that the BJTs of the output amplifier stage are implemented by HBT devices. Any bipolar junction transistor (BJT) mentioned herein may be implemented by a heterojunction bipolar transistor (HBT).

To lower the DC output voltage of the analog section, a bipolar emitter-follower (EF) stage 300 may be used for electrically connecting the output amplifier stage of the analog section to the digital section, as shown in Figure 17. The bipolar EF stage 300 of Figure 17 comprises two circuit branches, wherein each circuit branch comprises a BJT, an resistor R _out and a bias current source for providing a bias current Ibias- A respective output voltage v _ou t,p or v _O ut,m is provided at each node between the resistor R _out and the bias current source of each circuit branch of the bipolar EF stage 300. The output voltages v _O ut, _P and v _O ut,mform the output voltage of the bipolar EF stage 300 and, thus, of the analog section (when the analog section comprise the EF stage 300 as an output stage). The output impedance of a circuit branch of the bipolar EF stage 300 is the parallel between the output resistance r _Oigen of the current source of the circuit branch and the series connection of the resistor Rout and the emitter resistance l/g _m of the BJT. Since the output resistance r _Oigen of the current source is typically much larger than 50 Q and, on the contrary, the emitter resistance l/g _m of the BJT is much smaller, the resistor R _out has a resistance of 50 Q or in the order of 50 Q for achieving a well matched output impedance of the bipolar EF stage 300. Therefore, the DC output voltage v _ou t of a respective circuit branch of the bipolar EF stage 300 becomes: vout ^{— V} drv ^— ^BE ^— Ibias ' ^out (2) The variable VBE in the above equation (2) denotes the base-emitter-voltage of the BJT of the respective circuit branch. The DC output voltage Vdiv of a respective circuit branch of the output amplifier stage is assumed to be about 2 V to 2.5 V as done already above with respect to the example of Figure 16. Given these constrains, to reduce the DC output voltage v _out of the bipolar EF stage 300 well below 1 V (it is assumed that the digital section is supplied by a voltage lower than or equal to IV), large bias currents Ibias are needed (to increase the voltage drop on the respective resistor R _ou t), which in turn increases power consumption. Another drawback of the circuit topology of the bipolar EF stage 300 of Figure 17 is its low gain: the bipolar EF stage 300 introduces an attenuation of 6 dB (gain G _E F = 0.5) meaning that the preceding stage (i.e. the output amplifier stage) has to provide twice the signal amplitude, thus degrading the overall system linearity.

Another option for connecting the output of an analog section (e.g. the analog section 202 of Figure 15), in particular its output amplifier stage, to the input of a digital section (e.g. digital section 203 of Figure 15) is to use an NMOS common source (CS) stage 400 that is AC -coupled to the output amplifier stage (i.e. the preceding stage), as shown in Figure 18. The NMOS CS stage 400 may be referred to as NMOS CS amplifier stage or NMOS CS gain stage. The NMOS CS stage 400 of Figure 18 comprises two circuit branches, wherein each circuit branch comprises a resistor R _out and an n-type metal-oxide-semiconductor field effect transistor (NMOS FET). The circuit branches are connected via a resistor R _S hift to the supply terminal of the analog section for supplying the supply voltage avdd. The gate terminal of the NMOS FET of each circuit branch of the NMOS CS stage 400 is AC-coupled via a capacitor (decoupling capacitor) to a respective circuit branch of the output amplifier stage. A respective output voltage v _ou t,p or Vout.m is provided at each node between the resistor R _out and the drain terminal of the NMOS FET of each circuit branch of the NMOS CS stage 400. The output voltages v _ou t,p and v _O ut,mform the output voltage of the NMOS CS stage 400 and, thus, of the analog section (when the analog section comprise the NMOS CS stage 400 as an output stage)

The DC output voltage v _ou t of a respective circuit branch of the NMOS CS stage 400 is: vout ^— avdd — Ibias, mos ' (Rout T 2 ■ R _s hift) (3)

In the above equation (3), the variable “Ibias, mos’’ denotes a bias current sunk by the NMOS FET of the respective circuit branch. The resistor R _ou t of each circuit branch has a resistance of 50 Q or around 50 Q assuming a much larger NMOS FET output impedance r ₀ ,Mos- As apparent from the above equation (3), the DC output voltage v _ou t is independent from the bias current Ibias, a™ of the output amplifier stage and, thus, a power consumption of the output amplifier stage. Further, the DC output voltage v _ou t may be well below 1 V by simply increasing the value of the resistor Rsiuft. However, as the resistor R _S hift becomes large, the common mode gain of the NMOS CS stage 400 increases (i.e. worse common-mode rejection) and the output single-ended impedance matching degrades as well. The differential gain Ges of the NMOS CS stage 400 is:

Ges = gm - ^ = 25 ■ g _m (4)

Given the poor ratio g _m /Ibias,mos of NMOS FET devices, a large bias current must be used to obtain a gain larger than one (Gain > 1) or greater than 0 dB (Gain > 0 dB), causing large parasitic capacitance and low NMOS FET output impedance r ₀ ,Mos, deteriorating both bandwidth and return loss. In addition, the large output swing causes the NMOS FET device to operate in class B, thus seriously impairing linearity. The variable “g _m ” denotes the transconductance of each of the NMOS FET devices.

As an alternative, a PMOS amplifier stage 500 may be employed, as shown in Figure 19. In this case, the DC output voltage v _ou t of a circuit branch of the PMOS amplifier stage 500 may be computed as follows: vout ^— Ibias.mos ' (Rout T 2 ■ R _s hift) (5)

The variable “Ibias,mos” denotes the bias current of each of the NMOS FET devices. Compared to the NMOS CS stage 400 of Figure 18, the PMOS amplifier stage 500 of Figure 19 allows to avoid the input AC coupling capacitors. However, as the PMOS amplifier stage 500 exhibits the same gain of the NMOS CS stage 400 of Figure 18, it retains the same drawbacks as for limited bandwidth, return loss and linearity.

In view of the above disadvantages and drawbacks, embodiments of the invention aim to provide means that overcomes at least one of the above described disadvantages and drawbacks. An object may be to provide optimized means for electrically connecting an analog electrical circuit, in particular an amplifier stage of the analog electrical circuit, to an input of a digital electrical circuit compared to the above described means, in case the digital circuit is supplied by a lower supply voltage compared to the analog circuit.

The objective is achieved by the embodiments of the invention as described in the enclosed independent claims. Advantageous implementations of the embodiments of the invention are further defined in the dependent claims. As outlined already above, the term electrically connected may be abbreviated by the term “connected”.

A first aspect of the disclosure provides a voltage buffer. The voltage buffer comprises one circuit branch or two circuit branches, wherein each circuit branch comprises a transistor, a resistor and a current source electrically connected in series, and a DC level shifter electrically connecting an input terminal of the circuit branch to a control terminal of the transistor. A first terminal of the transistor is electrically connected to a supply terminal of the voltage buffer. The resistor is electrically connected between a second terminal of the transistor and the current source. A node between the resistor and the current source is electrically connected to an output terminal of the circuit branch. The DC level shifter is configured to provide a reduced voltage to the control terminal of the transistor, the reduced voltage being lower than a voltage applied at the input terminal.

The voltage buffer has the advantage of featuring low DC output voltage and output impedance matching. In particular, the voltage buffer allows obtaining an amplifier stage (optionally a unity amplifier stage or a unity gain stage) featuring low DC output voltage and output impedance matching. The use of the DC level shifter allows relaxing or reducing the current consumption of the voltage buffer, in particular of the series connection of the transistor, the resistor and the current of the respective circuit branch. Namely, the output DC voltage mostly depends on a voltage drop of the DC level shifter and does not depend on a voltage equaling to the product of the resistor of the respective circuit branch and a current sunk or provided by the current source of the respective circuit branch. In addition, the use of the DC level shifter allows achieving a better linearity compared to the other circuit topologies discussed above with regard to Figures 17, 18 and 19. Thus, the first aspect provides a voltage buffer by combining for each circuit branch of the voltage buffer a DC level shifter with a series connection of a transistor, a resistor and a current source. This allows obtaining a voltage buffer (optionally a unity amplifier stage) with low DC output voltage and an impedance-matched output, targeting broadband applications. The use of the DC level shifter allows reducing the DC output voltage while negligibly impacting the overall power consumption. The voltage buffer may be referred to as “unity amplifier stage” or “unity gain stage”.

In particular, the DC level shifter may be referred to as programmable DC level shifter, because the DC level shifter may be configured to configure or set (i.e. “program”) the reduced voltage providable by the DC level shifter. An input of the voltage buffer may be connected to an output of an amplifier stage, for example. The input of the voltage buffer comprises or is formed by the input terminal of each circuit branch of the voltage buffer. In particular, an output of the voltage buffer may be connected to an input of an electrical circuit, especially a digital electrical circuit. The output of the voltage buffer comprises or is formed by the output terminal of each circuit branch of the voltage buffer.

In particular, the transistor (of a respective circuit branch) is configured to provide a voltage at its second terminal following a voltage at its control terminal. In other words, the transistor may be configured to provide at its second terminal a voltage equaling a voltage at its control terminal minus a fixed bias DC voltage (intrinsic to the physic of the transistor). That is, the voltage gain between the voltage at the second terminal of the transistor and the voltage at the control terminal of the transistor is (approximately) unity.

In particular, a first terminal of the resistor is electrically connected to the second terminal of the transistor and the current source is electrically connected between a second terminal of the resistor and ground.

In an implementation form of the first aspect, the DC level shifter comprises a resistor electrically connected between the input terminal of the circuit branch and the control terminal of the transistor, a capacitor electrically connected in parallel with the resistor, and a current source electrically connected to the control terminal of the transistor.

That is, the DC voltage level shifter (of a respective circuit branch) may be implemented by a parallel resistor capacitor circuit (RC circuit) and a current source. In particular, in case the input of the voltage buffer is a stage of a cascade connection, then the control terminal of the transistor of a respective circuit branch of the voltage buffer is connected through the DC voltage level shifter of the respective circuit branch to a previous stage (in particular output of the previous stage) of the cascade connection. The resistance of the resistor of the DC level shifter of a respective circuit branch may be set to a very high value. Therefore, the output DC voltage of the voltage buffer may be arbitrarily set using a very low current (sunk/provided by the current source of the respective circuit branch), thus practically not impacting on the overall current consumption of the voltage buffer.

The capacitor may be electrically connected, in parallel with the resistor, between the input terminal of the circuit branch and the control terminal of the transistor. In particular, the current source is electrically connected between the control terminal of the transistor and ground. In an implementation form of the first aspect, the DC level shifter comprises two resistors electrically connected in series between the input terminal of the circuit branch and the control terminal of the transistor, a capacitor electrically connected in parallel with the two resistors, and a current source electrically connected to a node between the two resistors.

The two resistors connected in series allow reducing the effect of a parasitic capacitance of the current source of the DC level shifter on the overall transfer function of the DC level shifter.

The capacitor may be electrically connected, in parallel with the two resistors, between the input terminal of the circuit branch and the control terminal of the transistor of the circuit branch. In particular, the current source is electrically connected between ground and a node between the two resistors.

In an implementation form of the first aspect, the current source of the DC level shifter comprises a transistor. Optionally the transistor is an n-type metal-oxide-semiconductor field-effect transistor (NMOS FET).

Thus, the current source may be implemented in a cost effective way using a known semiconductor device in the form of a NMOS FET.

In particular, the current source of the DC level shifter may be a transistor. The transistor may be a NMOS FET, for example.

In an implementation form of the first aspect, the transistor of each circuit branch is a bipolar junction transistor (BJT), wherein the first terminal of the transistor is a collector terminal of the BJT, the second terminal of the transistor is an emitter terminal of the BJT and the control terminal of the transistor is a base terminal of the BJT. Alternatively, the transistor of each circuit branch may be a n-type metal-oxide-semiconductor field-effect transistor (NMOS FET), wherein the first terminal of the transistor is a drain terminal of the NMOS FET, the second terminal of the transistor is an source terminal of the NMOS FET and the control terminal of the transistor is a gate terminal of the NMOS FET.

Thus, in case the transistor of a respective circuit branch of the voltage buffer is a BJT, the respective circuit branch is provided by combining the DC voltage level shifter of the respective circuit branch with an emitter-follower (EF) circuit. The EF circuit may be referred to as an emitter-follower (EF) stage. Optionally, the transistor of each circuit branch is a heterojunction bipolar transistor (HBT).

Optionally, the current source of each circuit branch (connected in series to the resistor and transistor of the circuit branch) comprises or is implemented by a transistor, for example a NMOS FET.

In an implementation form of the first aspect, the voltage buffer comprises the one circuit branch, and the input terminal of the circuit branch is electrically connected or configured for being electrically connected to the output of a single-ended amplifier circuit.

The single-ended amplifier circuit may be a single-ended amplifier stage, in particular a single- ended amplifier stage of an analog electrical circuit. Optionally, the single-ended amplifier circuit may be a single-ended amplifier stage of a cascade amplifier circuit. The cascade amplifier circuit may comprise two or more amplifier stages that are cascade connected with each other.

In an implementation form of the first aspect, the voltage buffer comprises the two circuit branches. The input terminal of a first circuit branch of the two circuit branches is electrically connected or configured for being electrically connected to a first output terminal of a differential amplifier circuit. The input terminal of a second circuit branch of the two circuit branches is electrically connected or configured for being electrically connected to a second output terminal of the differential amplifier circuit.

The differential amplifier circuit may be a differential amplifier stage, in particular a differential amplifier stage of an analog electrical circuit. Optionally, the differential amplifier circuit may be a differential amplifier stage of a cascade amplifier circuit. The cascade amplifier circuit may comprise two or more amplifier stages connected in series.

In an implementation form of the first aspect, in case the voltage buffer comprises the two circuits branches, the current source of each circuit branch comprises a NMOS FET. The gate terminal of the NMOS FET of the first circuit branch may be electrically connected via a first AC coupling to the input terminal of the second circuit branch. The gate terminal of the NMOS FET of the second circuit branch may be electrically connected via a second AC coupling to the input terminal of the first circuit branch. In particular, a drain terminal of the NMOS FET of a respective circuit branch is electrically connected to the resistor of the respective circuit branch. Thus, according to an implementation form of the first aspect, the current source of the two circuit branches may be implemented using an NMOS common source (CS) topology to obtain a voltage buffer (or unity amplifier stage) with low DC output voltage and impedance matched output. In case the transistor of each circuit branch is a BJT, each circuit branch is provided by combining a DC voltage level shifter, a bipolar EF topology and an NMOS CS topology. A source terminal of the NMOS FET of the respective circuit branch may be electrically connected to ground. The current source of each circuit branch may be a NMOS FET. That is, the current source of each circuit branch may be provided or be implemented by a NMOS FET.

The voltage buffer may be implemented in BiCMOS (e.g. SiGe BiCMOS) technology or CMOS technology. In case the voltage buffer is implemented in BiCMOS technology, the transistor of each of the two circuit branches may be a bipolar junction transistor (BJT). In case the voltage buffer is implemented in CMOS technology, the transistor of each of the two circuits branches may be a n-type metal-oxide-semiconductor field-effect transistor (NMOS FET).

In an implementation form of the first aspect, in case the voltage buffer comprises the two circuits branches, the current source of each circuit branch comprises a NMOS FET. The gate terminal of the NMOS FET of the first circuit branch may be electrically connected via a first AC coupling to the second terminal of the transistor of the second circuit branch. The gate terminal of the NMOS FET of the second circuit branch may be electrically connected via a second AC coupling to the second terminal of the transistor of the first circuit branch.

Thus, the NMOS FET of a respective circuit branch may be driven by the second terminal of the transistor of the other circuit branch. This topology allows reducing the capacitive load seen by a previous stage without impairing the performance, when the voltage buffer is connected to the previous stage (i.e. the input of the voltage buffer is connected to the output of the previous stage). That is, this topology allows reducing the equivalent input capacitance of the voltage buffer without impairing the performance.

In particular, a drain terminal of the NMOS FET of a respective circuit branch is electrically connected to the resistor of the respective circuit branch. Further, a source terminal of the NMOS FET of the respective circuit branch may be electrically connected to ground.

The current source of each circuit branch may be a NMOS FET. That is, the current source of each circuit branch may be provided or be implemented by a NMOS FET. In an implementation form of the first aspect, the first AC coupling and the second AC coupling are each configured as a high-pass filter.

Thus, the first AC coupling and the second AC coupling may each be configured to achieve the function of a high-pass filter. In particular, the first AC coupling and the second AC coupling may comprise or be a high-pass filter.

In an implementation form of the first aspect, the first AC coupling comprises a capacitor electrically connected between the second circuit branch and the gate terminal of the NMOS FET of the first circuit branch. The second AC coupling may comprise a capacitor electrically connected between the first circuit branch and the gate terminal of the NMOS FET of the second circuit branch.

Thus, each of the first AC coupling and the second AC coupling may be implemented in a cost effective way using a known semiconductor device in the form of a capacitor.

The capacitor of the first AC coupling may be connected between the input terminal of the second circuit branch and the gate terminal of the NMOS FET of the first circuit branch. Alternatively, the capacitor of the first AC coupling may be connected between the second terminal of the transistor of the second circuit branch and the gate terminal of the NMOS FET of the first circuit branch. The capacitor of the second AC coupling may be connected between the input terminal of the first circuit branch and the gate terminal of the NMOS FET of the second circuit branch. Alternatively, the capacitor of the second AC coupling may be connected between the second terminal of the transistor of the first circuit branch and the gate terminal of the NMOS FET of the second circuit branch.

In an implementation form of the first aspect, the first AC coupling comprises a resistor electrically connected between the gate terminal of the NMOS FET of the first circuit branch and a voltage source for providing a bias voltage. The second AC coupling may comprise a resistor electrically connected between the gate terminal of the NMOS FET of the second circuit branch and the voltage source.

Thus, each of the first AC coupling and the second AC coupling may be implemented in a cost effective way using a known electrical device in the form of a resistor. In an implementation form of the first aspect, the voltage buffer comprises a resistor, wherein the first terminal of the transistor of each circuit branch is electrically connected via the resistor to the supply terminal of the voltage buffer.

Thus, the first terminal of the transistor may be connected to a supply voltage (e.g. fixed supply) via the resistor and the supply terminal of the voltage buffer. The resistor may be referred to as common-mode resistor. The resistor allows the transistor of each circuit branch to operate in a safe region by reducing the voltage between the first terminal and second terminal of the transistor of each circuit branch without effecting the differential-mode operation of the voltage buffer. Therefore, in case the transistor of each circuit branch is a BJT, the resistor allows the transistor of each circuit branch to operate in a safe region by reducing the voltage between the collector terminal and the emitter terminal (i.e. the collector-to-emitter voltage) without effecting the differential mode operation of the voltage buffer.

The voltage buffer may comprise a circuit part for controlling a current sunk by the DC level shifter of each circuit branch of the two circuit branches such that the average voltage of an output voltage provided by the output terminal of the first circuit branch and an output voltage provided by the output terminal of the second circuit branch equals a reference output voltage. The average output voltage may be or may define the common-mode output voltage of the voltage buffer. The circuit part comprises an operational amplifier, wherein the output of the operational amplifier is electrically connected to a control terminal of the current source of the DC level shifter of each circuit branch. In particular, the output of the operational amplifier is electrically connected to the control terminal of a transistor (e.g. gate terminal of a NMOS FET) that may provide the current source of the respective DC level shifter. The non-inverting input terminal of the operation amplifier is electrically connected via a first resistor to the output terminal of the first circuit branch and via a second resistor to the output terminal of the second circuit branch. The inverting terminal of the operation amplifier is electrically connected to a voltage source for providing the reference output voltage. In particular, the circuit part may be a DC loop.

The voltage source, to which the resistor of the first AC coupling and second AC coupling is electrically connected, may comprise a current mirror. For example, the voltage source, to which the resistor of the first AC coupling and second AC coupling is electrically connected, may be implemented by a current source electrically connected to the drain terminal of a NMOS FET. The drain terminal of the NMOS FET is electrically connected to the gate terminal of the NMOS FET. The resistor of the first AC coupling and second AC coupling is electrically connected to the gate terminal of the NMOS FET. In order to achieve the voltage buffer according to the first aspect of the disclosure, some or all of the implementation forms and optional features of the first aspect, as described above, may be combined with each other.

A second aspect of the disclosure provides an amplifier circuit (e.g. a cascade amplifier circuit) comprising an amplifier and a voltage buffer according to the first aspect as described above. The output of the amplifier is electrically connected to the input of the voltage buffer. The amplifier may comprises one or more amplifier stages.

The amplifier circuit of the second aspect and its implementation forms and optional features achieve the same advantages as the voltage buffer of the first aspect and its respective implementation forms and respective optional features.

A third aspect of the disclosure provides a device that comprises an analog electrical circuit configured to be operated with a first supply voltage, and a digital electrical circuit configured to be operated with a second supply voltage that is lower than the first supply voltage. The analog electrical circuit comprises the voltage buffer of the first aspect, as described above, as an output stage. The voltage buffer is cascade connected to an input of the digital electrical circuit.

Thus, the voltage buffer connects as an output stage of the analog electrical circuit the analog electrical circuit to the input of the digital electrical circuit. In particular, the first supply voltage and the second supply voltage are each a DC voltage. In particular, the absolute value of the second supply voltage is smaller than the absolute value of the first supply voltage.

The analog electrical circuit may comprise one or more amplifier stages. In case of more than one amplifier stage, the amplifier stages are cascade connected to each other. The one amplifier stage or the last amplifier stage of a cascade connection of amplifier stages may be connected to the voltage buffer. In particular, an output of the amplifier stage or the last amplifier may be connected to the input of the voltage buffer (the input formed by the input terminal of each circuit branch of the voltage buffer). Thus, the analog electrical circuit may comprise a cascade connection of one or more amplifier stages and the voltage buffer, wherein the voltage buffer is the output stage of the cascade connection. This cascade connection may be the cascade amplifier circuit of the second aspect. Therefore, the previous description is correspondingly valid for the cascade amplifier circuit of the second aspect. In addition, the description of the cascade amplifier circuit of the second aspect is correspondingly valid for the device of the third aspect, in particular the analog electrical circuit of the device. In an implementation form of the third aspect, the analog electrical circuit has an output impedance that matches an input impedance of the digital electrical circuit.

The device of the third aspect and its implementation forms and optional features achieve the same advantages as the voltage buffer of the first aspect and its respective implementation forms and respective optional features.

In order to achieve the device according to the third aspect of the disclosure, some or all of the implementation forms and optional features of the third aspect, as described above, may be combined with each other.

All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms of the present disclosure will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Figure 1 shows a voltage buffer according to an example of the invention;

Figure 2a shows a DC level shifter of a voltage buffer according to an example of the invention;

Figures 2b and 2c show graphs relating to the DC level shifter in Figure 2a.

Figures 3a, 3b, 3c each show a DC level shifter of a voltage buffer according to an example of the invention; Figures 4 to 7 each show a voltage buffer according to an example of the invention;

Figure 8 shows an example of an implementation of a bias circuit for the voltage buffers according to Figures 5 to 7;

Figure 9 shows an example of a setup for comparing the stages of Figures 17 and 18 and the voltage buffers of Figures 1 and 5 with each other;

Figure 10 shows a normalized transfer function over frequency for the bipolar emitter-follower (EF) stage of Figure 17, the NMOS common source (CS) stage of Figure 18 and the voltage buffers of Figures 1 and 5;

Figure 11 shows an output return loss over frequency for the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18 and the voltage buffers of Figures 1 and 5;

Figure 12 shows a 1GHz Total Harmonic Distortion (THD) versus output voltage amplitude for the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18 and the voltage buffers of Figures 1 and 5;

Figure 13 shows a table summarizing the performance of the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18 and the voltage buffers of Figures 1 and 5;

Figure 14 shows a device according to an example of the invention, the device being an electro-optical module (E/O module);

Figure 15 shows an example of a device being an electro-optical module (E/O module);

Figures 16 to 19 each show an example of connecting an output of an amplifier stage of an analog electrical circuit to an input of a digital electrical circuit, assuming that the analog electrical circuit is supplied with a first supply voltage and the digital electrical circuit is supplied with a second supply voltage being lower than the first supply voltage.

In the Figures, corresponding elements are labeled with the same reference sign.

DETAILED DESCRIPTION OF EMBODIMENTS

Figure 1 shows a voltage buffer according to an example of the invention. The voltage buffer of Figure 1 is an example of the voltage buffer according to the first aspect of the disclosure, as described above. Therefore, the above description of the voltage buffer of the first aspect is correspondingly valid for the voltage buffer of Figure 1.

According to the example of Figure 1, the voltage buffer 1 comprises one circuit branch 2. The circuit branch 2 comprises a DC level shifter 3. In addition, the circuit branch 2 comprises a transistor Tl, a resistor R1 and a current source CS1 electrically connected in series. In particular, the current source CS1 is a DC current source. As shown in Figure 1, the transistor Tl is a bipolar junction transistor (BJT). This is only by way of example and, thus, the transistor may also be differently implemented, for example by a n-type metal-oxide -semiconductor field effect transistor (NMOS FET). In the following description, it is assumed that the transistor Tl is a BJT. This description is correspondingly valid in case of another transitory type of the transistor Tl, such as a NMOS FET. The DC level shifter 3 comprises a parallel circuit of a capacitor Cl and a resistor R2. Further, the DC level shifter 3 comprises a current source CS2 connected to the side of the capacitor Cl and resistor R2 that is connected to the transistor Tl. The current source CS2 may be a tail current source. In particular, the current source CS2 is a DC current source.

The implementation of the DC level shifter 3 shown in Figure 1 is only by way of example and may be differently, as shown for example in Figure 3.

The DC level shifter 3 connects an input terminal N 1 of the circuit branch 2 to the base terminal (control terminal) of the transistor Tl. A voltage (input voltage) Vin may be provided to the input terminal Nl. The collector terminal (first terminal) of the transistor Tl is connected to a supply terminal N3 of the voltage buffer 1. A supply voltage Vdd may be provided to the voltage buffer 1 via the supply terminal N3. The resistor R1 is connected between the emitter terminal (second terminal) of the transistor Tl and the current source CS1. The current source CS1 may comprise or be formed (or be implemented) by a transistor, such as a NMOS FET (not shown in Figure 1). A node between the resistor R1 and the current source CS1 is connected to an output terminal N2 of the circuit branch 2. In particular, the node between the resistor R1 and the current source CS1 is the output terminal N2 of the circuit branch 2. As shown in Figure 1, the current source CS1 may be connected between the resistor R1 and ground. The input terminal N1 of the circuit branch 2 may be configured for being electrically connected to an output of a single- ended amplifier circuit. Optionally, the input terminal N1 of the circuit branch 2 is electrically connected to an output of a single-ended amplifier circuit (not shown in Figure 1).

The DC level shifter 3 is configured to provide a reduced voltage Vred to the base terminal (control terminal) of the transistor Tl, wherein the reduced voltage Vred is lower than a voltage Vin applied at the input terminal Nl.

According to the topology of the example of Figure 1, a DC voltage level shifter 3 is combined with a bipolar emitter-follower (EF) circuit comprising the transistor Tl, resistor R1 and current source CS1 to obtain a voltage buffer 1 featuring low DC output voltage and output impedance matching. As shown in Figure 1, the transistor Tl, thus the EF circuit, may be connected to a previous stage (amplifier stage) through the input terminal N 1 and the DC voltage level shifter 3 (exemplarily implemented by a parallel RC circuit Cl, R2 and a current source CS2). Since the resistance of the resistor R2 (level shifter resistance) may be set to a very high value, the output DC voltage Vout (providable at the output terminal N2) may be set using a very low current (sunk or provided by the current source CS2), thus practically not impacting on the overall current consumption of the voltage buffer 1. The use of the DC level shifter 3 allows relaxing the current consumption of the voltage buffer 1. Namely, the output DC voltage Vout of the voltage buffer 1 mostly depends on the voltage drop of the DC level shifter 3 equaling to the product of the current sunk or provided by the current source CS2 and the resistor R2. The use of the DC level shifter 3 allows reducing the required voltage drop across the resistor R1 (equaling to the product of the resistor R1 and the current sunk by the current source CS1) to achieve the same output DC voltage Vout. Since the resistance value of the resistor R2 may be greater than the resistance value of the resistor Rl, this reduces the overall power consumption. In addition, the use of the DC level shifter 3 allows achieving a better linearity compared to the circuit topologies discussed above with regard to Figures 17, 18 and 19.

In other words, a DC voltage level shifter is combined with a bipolar EF circuit to obtain a voltage buffer with low DC output voltage and an impedance-matched output, targeting broadband applications. The use of the DC level shifter allows to reduce the DC output voltage while negligibly impacting on the overall power consumption. By configuring or setting ( programming ) the resistor R2 the value of the reduced voltage Vred may be set. This may be done by choosing a resistor with a respective resistance. In addition or alternatively, the resistor R2 may be a resistor with a changeable (or adaptable) resistance. The greater the resistor R2 (i.e. its resistance) the lower (or smaller) may be the current sunk by the current source CS2 for achieving a particular reduced voltage Vred and vice versa. The greater the resistor R2 (i.e. its resistance) the lower the reduced voltage Vred compared to the voltage Vin at the input terminal N 1 and vice versa, when the current sunk or provided by the current source CS2 is kept constant. In addition or alternatively, the value of the reduced voltage Vred may be controlled or set by controlling the current sunk by the current source CS2. For this the resistor R2 (i.e. its resistance) may be kept constant (or fixed). In other words, the DC level shifter 3, in particular the reduced voltage Vred providable by the DC level shifter 3, may be programmed by controlling the current sunk by the current source CS2. When keeping the resistor R2 constant, the greater the current sunk by the current source CS2, the greater the voltage drop across the resistor R2 and, thus, the lower the reduced voltage Vred compared to the voltage Vin at the input terminal N 1 and vice versa.

At low frequency, the output impedance of the voltage buffer 1 is manly dictated by the resistor R1 that is connected between the emitter terminal (second terminal) of the transistor T1 and the output terminal N2. By reasonably assuming that the output impedance of the current source CS1 is much larger than 50 (the output impedance of the voltage buffer 1 is assumed to be 50 for impedance-matched output), the output impedance Z _out of the voltage buffer 1 at low frequency may be computed as: wherein gm,BjT is the transconductance of the transistor Tl. Therefore, to achieve a good output matching from low frequency, R1 is assumed to be 50 Q or in the order of 50Q.

The DC output voltage v _0Ut ,Dc of the voltage buffer 1 may be computed as: vout,DC ^{= v} in,DC ^{— V} DC, shift ^— ^BE,BJT ^— R1 ’ Ibias (7), wherein Vin,DC is a DC voltage provided at the input terminal Nl, VDC, shift is the voltage drop across the DC level shifter 3, VBE.BJT is the base-emitter voltage of the transistor Tl and Ibias is the current provided by the current source CS 1 (i.e. a bias current of the voltage buffer 1 provided by the current source CS1). The voltage drop VDC, shift across the DC level shifter 3 equals to the product of the resistor R2 and the current IDC sunk by the current source CS2 of the DC level shifter 3 (VDC, shat = R2 • IDC). This means that the output DC voltage v _0U t,Dc may easily be set by controlling the voltage VDC, shift across the DC level shifter 3, in particular across the resistor R2.

Figure 2a shows an example of an implementation of the DC level shifter 3 of the voltage buffer 1 according to Figure 1, which is in line with the one shown in Figure 1. Thus, the DC level shifter 3 is implemented by a parallel RC circuit (comprising the resistor R2 and the capacitor Cl) and a current source CS2 being a DC current source for providing a DC current I _D c- The voltage VDC, shift across the DC level shifter 3, in particular across the resistor R2, equals to the product of the resistor R2 and the current IDC provided by the current source CS2 (VDC, shift = R2 • IDC). Thus, the value of the resistor R2 may be chosen to be very high (several kQ) to reduce the current consumption of the DC level shifter 3 and, thus, the voltage buffer 1. Namely, the current IDC of the current source CS2 of the DC level shifter 3 is consequently very low. The capacitor Cl of the DC level shifter 3 serves the purpose of avoiding bandwidth limitations, since it represents a short circuit at high frequency, effectively bypassing resistor R2 of the DC level shifter 3. Figure 2b shows the effect of the capacitor Cl of the level shifter 3 on the level shifter transfer function, assuming that the output load Ci _oa d connected to the DC level shifter C3 is purely capacitive. In case there is no capacitor Cl (i.e. Cl = 0 F), the transfer function from Vx to Vy of the DC level shifter 3 is a simple low-pass fdter with a time constant equal to the product of the resistor R2 and the capacitive output load Ci _oa d (R2 • CM). On the contrary, in case there is a capacitor Cl in parallel to the resistor R2 (i.e. Cl 0 F, e.g. Cl = 1 pF) the transfer function becomes:

Vy 14-S-R2-C1

V _x l + s-R2.(Cl + Ci _oad ) (8)

In the above equation (8), the variable “s” is commonly known as the “complex frequency” variable. From the above equation (8) it can be seen that in case the capacitance of the capacitor Cl is much larger than the capacitance of the capacitive output load Ci _oa d (Cl » C _load ) the DC level shifter 3 acts as a simple all-pass fdter (i.e. VY/V _X = 1). However, to limit area occupation, the capacitor Cl of the DC level shifter 3 may be practically designed to be the capacitive output load Ci _oa d multiplied by a factor a (aCi _oa d). The factor a is greater than one (a > 1), meaning that a gain attenuation equal to a/(l + a) occurs after the frequency of the zero of the above transfer function. The attenuation versus the capacitive ratio a = Cl/C _load is reported in Figure 2c, showing that a factor a lower than or equal to 8 (a < 8) is sufficient to obtain less than 1 dB of gain loss at high frequency. An example of an alternative implementation of the DC level shifter 3 shown in Figures 1 and 2 is shown in Figure 3b. The implementation of the DC level shifter 3 of Figure 3a is the same as the one in Figures 1 and 2a. According to Figure 3b, the DC level shifter 3 comprises, in addition to the capacitor Cl and the current source CS2, a series connection of two resistors R21 and R22 instead of a single resistor R2 (as is the case for the implementation of Figure 3a). The series connection of the two resistors R21 and R22 is connected in parallel to the capacitor Cl, wherein the current source CS2 is connected to a node between the two resistors R21 and R22. The DC level shifter topology of Figure 3b allows reducing the effect of the parasitic capacitance Cpar of the current source CS2 on the overall transfer function (i.e. by isolating, at high frequency the signal path Vx-to-Vy of the DC level shifter 3 from the parasitic capacitance C _par ). Figure 3c shows, based on the DC level shifter topology of Figure 3b, an example of a possible implementation of the current source CS2 using a transistor T3, such as a NMOS device (in particular a NMOS FET). In this case, the DC current provided by the current source CS2 may be controlled by a DC voltage V _ct ri provided to the control terminal of the transistor T3 (gate terminal of the NMOS FET T3). This implementation example of the current source CS2 is also valid for any other DC level shifter topology, such as the DC level shifter topology of Figure 3a.

For further information on the voltage buffer 1 of Figure 1 reference is made to the above description of the voltage buffer according to the first aspect and to the description of Figures 2 and 3.

Figure 4 shows a voltage buffer according to an example of the invention. The voltage buffer of Figure 1 is an example of the voltage buffer according to the first aspect of the disclosure, as described above. Therefore, the above description of the voltage buffer of the first aspect is correspondingly valid for the voltage buffer of Figure 4. As shown in Figure 4, the circuit topology of the voltage buffer shown in Figure 1 may be used in a differential form. That is, the considerations done for the single-ended version of the voltage buffer (i.e. voltage buffer with a single circuit branch) shown in Figure 1 hold for the differential version of the voltage buffer shown in Figure 4.

The voltage buffer 1 of Figure 4 comprises two circuit branches 2a and 2b, wherein each circuit branch is implemented in line with the one circuit branch 2 of the voltage buffer 1 of Figure 1. Therefore, the above description of the voltage buffer 1 of Figure 1 is also valid for the voltage buffer 1 of Figure 4. In particular, the above description of the circuit branch 2 of the voltage buffer 1 of Figure 1 is correspondingly valid for each circuit branch of the two circuit branches 2a and 2b of the voltage buffer 1 of Figure 4. Thus, the transistor Tla, resistor Ria, current source CSla, DC level shifter 3a, input terminal Nla and output terminal N2a of the circuit branch 2a of the voltage buffer 1 of Figure 4 correspond to the transistor Tl, resistor Rl, current source CS1, DC level shifter 3, input terminal N1 and output terminal N2 of the voltage buffer 1 of Figure 1, respectively. The same applies to the second circuit branch 2b of Figure 4. That is, the transistor Tib, resistor Rib, current source CSlb, DC level shifter 3b, input terminal Nib and output terminal N2b of the circuit branch 2b of the voltage buffer 1 of Figure 4 correspond to the transistor Tl, resistor Rl, current source CS1, DC level shifter 3, input terminal N1 and output terminal N2 of the voltage buffer 1 of Figure 1, respectively.

The same applies for the DC level shifters 3a and 3b of the two circuit branches 2a and 2b of the voltage buffer 1 of Figure 4. That is, the resistor R2a, the capacitor Cla and the current source CS2a of the DC level shifter 3a of the circuit branch 2a of the voltage buffer 1 of Figure 4 correspond to the resistor R2, the capacitor Cl and the current source CS2 of the DC level shifter 3 of the voltage buffer 1 of Figure 1, respectively. Accordingly, the resistor R2b, the capacitor Clb and the current source CS2b of the DC level shifter 3b of the circuit branch 2b of the voltage buffer 1 of Figure 4 correspond to the resistor R2, the capacitor Cl and the current source CS2 of the DC level shifter 3 of the voltage buffer 1 of Figure 1, respectively.

As indicated in Figure 4, an input voltage Vin may be applied between the input terminal Nla of the circuit branch 2a and the input terminal Nib of the second circuit branch 2b of the voltage buffer 1. The first circuit branch 2a is configured to provide at its output terminal N2a a voltage Vout,p. The second circuit branch 2b is configured to provide at its output terminal N2b a voltage Vout,m.

The implementation of the transistors Tla and Tib as BJTs, shown in Figure 4, is only by way of example. These transistors may be differently implemented, e.g. by NMOS FETs. Further, the implementation of the DC level shifters 3a and 3b shown in Figure 4 is only by way of example. These DC level shifters 3a and 3b, shown in Figure 4, may be differently implemented, e.g. in line with the examples of Figures 3(b) and 3(c). Thus, the description of Figures 2 and 3 is correspondingly valid for each circuit branch of the voltage buffer 1 of Figure 4, in particular for each DC level shifter 3a and 3b of the voltage buffer 1 of Figure 4.

The input terminal Nla of the circuit branch 2a (first circuit branch of the two circuit branches 2a and 2b) may be configured for being connected to a first output terminal of a differential amplifier circuit. The input terminal Nib of the circuit branch 2b (second circuit branch of the two circuit branches 2a and 2b) may be configured for being connected to a second output terminal of a differential amplifier circuit. Optionally, the input terminal N la of the first circuit branch 2a is connected to a first output terminal of a differential amplifier circuit and the input terminal N lb of the second circuit branch 2b is connected to a second output terminal of a differential amplifier circuit.

For further information on the voltage buffer 1 of Figure 4 reference is made to the above description of the voltage buffer according to the first aspect of the disclosure and to the description of Figures 1, 2 and 3.

Figure 5 shows a voltage buffer according to an example of the invention. The voltage buffer of Figure 5 is an example of the voltage buffer according to the first aspect of the disclosure, as described above. Therefore, the above description of the voltage buffer of the first aspect of the disclosure is correspondingly valid for the voltage buffer of Figure 5. In particular, the voltage buffer 1 of Figure 5 corresponds to the voltage buffer 1 of Figure 4 comprising additional features. Therefore, for describing the voltage buffer of Figure 5 reference is made to the above description of Figures 1 to 4 and in the following mainly the additional features are described. In the following, the circuit branch 2a is referred to as a first circuit branch of the two circuit branches 2a and 2b and the circuit branch 2b is referred to as a second circuit branch of the two circuit branches 2a and 2b.

As shown in Figure 5, the current sources CSla and CS2b of the two circuit branches 2a and 2b each are implemented by a respective n-type metal-oxide-semiconductor field effect transistor (NMOS FET) T2a or T2b. The gate terminal of the NMOS FET T2a of the first circuit branch 2a is electrically connected via a first AC coupling 4a to the input terminal N lb of the second circuit branch 2b. The gate terminal of the NMOS FET T2b of the second circuit branch 2b is electrically connected via a second AC coupling 4b to the input terminal N la of the first circuit branch 2a.

In particular, the first AC coupling 4a and the second AC coupling 4b are each configured as a high-pass filter. As shown in Figure 5, the first AC coupling 4a may comprise a capacitor C2a electrically connected between the second circuit branch 2b (in particular the input terminal Nib) and the gate terminal of the NMOS FET T2a of the first circuit branch 2a. The second AC coupling 4b may comprise a capacitor C2b electrically connected between the first circuit branch 2a (in particular the input terminal Nla) and the gate terminal of the NMOS FET T2b of the second circuit branch 2b. Moreover, as indicated in Figure 5, the first AC coupling 4a optionally comprises a resistor R3a electrically connected between the gate terminal of the NMOS FET T2a of the first circuit branch 2a and a voltage source (not shown in Figure 5) for providing a bias voltage Vb,mos. The second AC coupling 4b optionally comprises a resistor R3b electrically connected between the gate terminal of the NMOS FET T2b of the second circuit branch 2b and the voltage source (not show in Figure 5).

In Figure 5, the transistors Tla and Tib of the two circuit branches 2a and 2b are each implemented by a BJT. This is only by way of example. Thus, these transistors Tla and Tib may be implemented by a different transistor type, for example by a NMOS FET (not shown in Figure 5). Further, the implementation of the DC level shifters 3a and 3b shown in Figure 5 is only by way of example. The topology of the DC level shifters 3a and 3b of Figure 5 corresponds to the topology shown in Figure 3a. These DC level shifters 3a and 3b may be differently implemented, for example by the DC level shifter topologies shown in Figures 3b and 3c.

As shown in Figure 5, a bipolar emitter-follower (EF) circuit and a NMOS common source (CS) circuit may be combined to form each circuit branch of the two circuit branches 2a and 2b of a voltage buffer 1 according to an example of the invention. This topology allows obtaining a voltage buffer (may also be referred to as unity amplifier stage or a unity gain stage) with low DC output voltage and impedance matched output. Optionally, with a proper design the gain of this topology (configuration) may be greater than one (Gain > 1). The bipolar EF section of the voltage buffer 1 (transistors Tla and Tib) is connected to the input terminals Nla and Nib via (or through) the respective DC level shifter 3a or 3b, while the NMOS CS section (i.e. transistors T2a and T2b) is AC coupled to the input terminals Nla and Nib.

The collector terminal (first terminal) of the transistors Tla and Tib of the two circuit branches 2a and 2b may be (directly) connected to the supply terminal N3 of the voltage buffer 1, as shown in Figure 5. The voltage buffer 1 is configured to be supplied via the supply terminal N3 with a supply voltage Vdd, in particular a regulated supply voltage. Alternatively, the collector terminal (first terminal) of the transistors Tla and Tib of the two circuit branches 2a and 2b may be connected to the supply terminal N3 of the voltage buffer 1 via a resistor, in particular a common-mode resistor, as shown in Figure 6. Such a resistor allows the transistors Tla and Tib (i.e. the bipolar junction transistors) to operate in a safe region by reducing their collector-to- emitter voltage (VCE) without affecting the differential-mode operation of the voltage buffer 1. As shown in Figure 5, the NMOS CS section, in particular each of the NMOS FETs T2a and T2b, of the voltage buffer 1 may be AC coupled to the input of the voltage buffer 1 via (or through) high-pass filters 4a and 4b. The input of the voltage buffer 1 comprises or is formed by the input terminal Nla of the first circuit branch 2a and the input terminal Nib of the second circuit branch 2b. In particular, the first high-pass filter 4a that AC couples the gate terminal of the NMOS FET T2a of the first circuit branch 2a to the input terminal Nib of the second circuit branch 2b comprises or is formed by the capacitor C2a and the resistor R3a. The second high- pass filter 4b that AC couples the gate terminal of the NMOS FET T2b of the second circuit branch 2b to the input terminal Nla of the first circuit branch 2a comprises or is formed by the capacitor C2b and the resistor R3b. Thus, the first and second high-pass filter may be a RC high- pass filter. The first and second high-pass filter may be referred to as first AC coupling and second AC coupling, respectively. The cut-off frequency of the high-pass filters 4a and 4b may be set below 1 GHz, in particular well below 1 GHz.

The gain of the NMOS CS section (comprising the NMOS FETs T2a and T2b) is negative, whereas that of the bipolar EF section (comprising the BJTs Tla and Tib) is positive. Therefore, the gate terminal of the NMOS FET T2a of the first circuit branch 2a is connected to the input terminal Nib of the second circuit branch 2b. In particular, the input terminal Nib of the second circuit branch 2b is a negative input terminal (input terminal of negative polarity) of the voltage buffer 1, as indicated in Figure 5. The gate terminal of the NMOS FET T2b of the second circuit branch 2b is connected to the input terminal Nla of the first circuit branch 2a. In particular, the input terminal Nla of the first circuit branch 2a is a positive input terminal (input terminal of positive polarity) of the voltage buffer 1, as indicated in Figure 5. In other words, the NMOS FETs T2a and T2b are driven by the same signal which drives the BJTs Tla and Tib but with opposite polarity. In particular, the NMOS FET T2a of the first circuit branch 2a is driven by a signal that drives the BJT Tib of the second circuit branch 2b, and the NMOS FET T2b of the second circuit branch 2b is driven by a signal that drives the BJT Tla of the first circuit branch 2a.

At low frequency, the output impedance is manly dictated by the two resistors Ria and Rib of the two circuit branches 2a and 2b. The resistor Ria is connected between the emitter terminal of the BJT Tla and the output terminal N2a of the first circuit branch 2a and the resistor Rib is connected between the emitter terminal of the BJT Tib and the output terminal N2b of the second circuit branch 2b. In fact, the output impedance Z _out of a circuit branch at low frequency may be computed as: wherein R1 denotes the resistor Ria or Rib, r _Oi mos is the output resistance of the NMOS FETs T2a and T2b (typically much larger than the resistors Ria and Rib) and gm.Bji is the transconductance of the BJTs Tla and Tib. Therefore, for achieving a good output impedance matching from low frequency, the resistors Ria and Rib are each 50 Q or in the order of 5 Ofl.

The DC output voltage v _0U t,Dc of a circuit branch of the voltage buffer 1 of Figure 5 may be computed as: wherein Vin,DC is a DC voltage provided at the input terminal Nla or Nib, VDC, shift is the voltage drop across the DC level shifter 3a or 3b, VBE,BJT is the base-emitter voltage of the BJT Tla or Tib and Ibias is the current provided by the current source CSla or CSlb (i.e. a bias current of the voltage buffer 1 provided by the current sources CSla and CSlb). The considerations on the DC level shifters of Figures 1 to 3 previously carried out are also valid for the voltage buffer 1, in particular the DC level shifter 3a and 3b, of Figure 5. A DC bias control loop may be implemented as exemplarily shown in Figure 8.

For further information on the voltage buffer of Figure 5 reference is made to the above description of the voltage buffer according to the first aspect of the disclosure and to the description of Figures 1 to 4.

Figure 6 shows a voltage buffer according to an example of the invention. The voltage buffer of Figure 6 is an example of the voltage buffer according to the first aspect of the disclosure, as described above. Therefore, the above description of the voltage buffer of the first aspect of the disclosure is correspondingly valid for the voltage buffer of Figure 6. In particular, the voltage buffer 1 of Figure 6 corresponds to the voltage buffer 1 of Figure 5 comprising an additional feature. Therefore, for describing the voltage buffer of Figure 6 reference is made to the above description of Figures 1 to 5 and in the following mainly the additional feature is described. As outlined already above, according to the implementation form of Figure 6, the collector terminal (first terminal) of the transistors Tla and Tib of the two circuit branches 2a and 2b is connected to the supply terminal N3 of the voltage buffer 1 via a resistor R4, in particular a common-mode resistor. Such a resistor R4 allows the transistors Tla and Tib (i.e. the bipolar junction transistors) to operate in a safe region by reducing their collector-to-emitter voltage (VCE) without affecting the differential-mode operation of the voltage buffer 1.

For further information on the voltage buffer 1 of Figure 6 reference is made to the above description of the voltage buffer according to the first aspect of the disclosure and to the description of Figures 1 to 5.

Figure 7 shows a voltage buffer according to an example of the invention. The voltage buffer of Figure 7 is an example of the voltage buffer according to the first aspect of the disclosure, as described above. Therefore, the above description of the voltage buffer of the first aspect of the disclosure is correspondingly valid for the voltage buffer of Figure 7. In particular, the voltage buffer 1 of Figure 7 corresponds to the voltage buffer 1 of Figure 5 comprising an additional feature. Therefore, for describing the voltage buffer of Figure 7 reference is made to the above description of Figures 1 to 5 and in the following mainly the additional feature is described.

The circuit topology of the voltage buffer 1 of Figure 7 differs from the circuit topology of the voltage buffer 1 of Figure 5 as described in the following. According to Figure 7, the gate terminal of the NMOS FET T2a of the first circuit branch 2a is electrically connected via the first AC coupling 4a to the emitter terminal (second terminal) of the transistor (BJT) Tib of the second circuit branch 2b. Further, the gate terminal of the NMOS FET T2b of the second circuit branch 2b is electrically connected via the second AC coupling 4b to the emitter terminal (second terminal) of the transistor (BJT) Tla of the first circuit branch 2a.

In other words, according to Figure 7, the NMOS CS section of the voltage buffer 1, in particular the NMOS FETs T2a and T2b, are driven by the emitter terminals of the bipolar EF section, in particular by the emitter terminal of the BJTs Tla and Tib. In contrast thereto, the NMOS CS section of the voltage buffer 1 of Figure 5 is driven by the input terminals Nla and Nib of the voltage buffer 1 and, thus, by a previous stage when the previous stage is connected to the input terminals Nla and Nib. The circuit topology of the voltage buffer 1 of Figure 7 allows reducing the capacitive load seen by a previous stage (when the previous stage is connected to the input terminals Nla and Nib of the voltage buffer 1) without impairing the performance. That is, the circuit topology of the voltage buffer 1 of Figure 7 allows reducing the equivalent input capacitance of the voltage buffer without impairing the performance.

The voltage buffers of Figures 5, 6 and 7 are based on BiCMOS technology because each circuit branch of the two circuit branches 2a and 2b comprises a respective bipolar junction transistor (BJT) Tla or Tib and a respective NMOS FET T2a or T2b. For example, the voltage buffer may be implemented in SiGe BiCMOS technology. As outlined already above, the BJTs Tla and Tib may be implemented by a different transistor type, for example by NMOS FETs. Thus, the voltage buffers of Figures 5, 6 and 7 may be implemented in CMOS technology. In this case, the transistors of each circuit branch may each be implemented by a NMOS FET.

For further information on the voltage buffer 1 of Figure 7 reference is made to the above description of the voltage buffer according to the first aspect of the disclosure and to the description of Figures 1 to 6.

Figure 8 shows an example of a bias circuit for the voltage buffers according to Figures 5 to 7. In particular, Figure 8 shows a DC bias control scheme for controlling a bias current provided by the respective current source CSla or CSlb of each circuit branch 2a or 2b of the voltage buffers 1 according to Figures 5 to 7 and a bias current provided by the respective current source CS2a or CS2b of the respective DC level shifter 3a or 3b of each circuit branch 2a or 2b.

The voltage buffer 1 may comprise a circuit part for controlling a current sunk by the respective DC level shifter 3a or 3b of each circuit branch such that the average voltage of an output voltage provided by the output terminal N2a of the first circuit branch 2a and an output voltage provided by the output terminal N2b of the second circuit branch 2b equals to a reference output voltage Vref. The average output voltage may be or may define the common-mode output voltage of the voltage buffer 1. The circuit part comprises an operation amplifier 5, wherein the output of the operation amplifier 5 is electrically connected to a control terminal of the respective current source CS2a or CS2b of the respective DC level shifter 3a or 3b of each circuit branch. According to Figure 8, the respective current source CS2a or CS2b of the respective DC level shifter 3a or 3b is implemented by a NMOS FET T3a or T3b and, thus, the control terminal is the gate terminal of the NMOS FET T3a or T3b. This implementation of the respective current source CS2a or CS2b is only by way of example and, thus, it may be differently implemented. The non-inverting input terminal of the operation amplifier 5 is electrically connected via a first resistor R5 to the output terminal N2a of the first circuit branch 2a and via a second resistor R6 to the output terminal N2a of the second circuit branch 2b (not shown in figure 8). The inverting terminal of the operation amplifier 5 is electrically connected to a voltage source (not shown in Figure 8) for providing the reference output voltage Vref. In particular, the circuit part may be a DC control loop.

The voltage source, to which the respective resistor R3a or R3b of the first AC coupling 4a and second AC coupling 4b is electrically connected, may comprise a current mirror. For example, the voltage source, to which the respective resistor R3a or R3b of the first AC coupling 4a and second AC coupling 4b is electrically connected, may be implemented by a current source CS3 electrically connected to the drain terminal of aNMOS FET T4. The drain terminal of the NMOS FET T4 is electrically connected to the gate terminal of the NMOS FET T4. The respective resistor R3a or R3b of the first AC coupling 4a and second AC coupling 4b is electrically connected to the gate terminal of the NMOS FET T4.

To track process-voltage-temperature (PVT) variations, a DC control loop comprising the operation amplifier 5 and the resistors R5 and R6 may be employed to sense the average output voltage via two resistors (i.e. the common-mode output voltage) and to control the current sunk by the respective DC level shifter 3a or 3b such that the respective output voltage V _ou t,p or V _O ut,m equals to the reference output voltage Vref (V _ou t,p = Vref or V _O ut,m = Vref). In this way, the DC output voltage is also made programmable. For the respective current source CSla or CSlb of the respective circuit branch 2a or 2b a respective NMOS device T2a or T2b (e.g. a NMOS FET) may be used with a simple current mirror that set the bias current of the respective circuit branch 2a or 2b.

The description of Figure 8 is valid for each of the voltage buffers of Figures 5 to 7. The description of Figure 8 is correspondingly valid for describing a bias control scheme of the voltage buffers of Figures 1 and 4.

In the following, the advantage of the voltage buffer according to the first aspect of the disclosure compared to the bipolar emitter-follower (EF) stage of Figure 17 and the NMOS common source (CS) stage of Figure 18 is described based on Figures 10 to 13. This is done by comparing the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5 with each other. To take into account the effect of a previous stage in terms of linearity, bandwidth and DC voltages, a driver is connected as an input stage to the input, in particular the one or two input terminals, of the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5. Figure 9 shows an example of a setup for comparing the stages of Figures 17 and 18 and the voltage buffers of Figures 1 and 5 with each other. As shown in Figure 9, a driver (stage) 6 is connected to an input of a further stage 7. The further stage 7 may be changed to be the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5.

For a fair comparison, the overall gain of the driver 6 and the further stage to which the driver 6 is connected to (i.e. gain of driver 6 plus gain of further stage 7) is kept constant for all of the above described four case (i.e. the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5). The bipolar EF stage of Figure 17 and the voltage buffer of Figure 1 each feature a 6 dB gain attenuation. Therefore, the resistance of the resistors Ra _eg of the associated driver stage 6 (see Figure 9) is reduced so as to double the driver gain (this is not done in the other two cases, which do not exhibit any gain attenuation). The output DC voltage is set to 0.5 V for all of the four cases. The current consumption of the NMOS CS stage of the circuit of Figure 18 is chosen such that the NMOS CS stage gain is equal to 1 (0 dB). The comparison is carried out considering different performance metrics: transfer function, power consumption, linearity, bandwidth and output impedance matching.

In Figures 10 to 12, the slope with triangles corresponds to the bipolar EF stage of Figure 17, the slope with circles corresponds to the NMOS CS stage of Figure 18, the slope with diamonds corresponds to the voltage buffer of Figure 1 and the slope with squares corresponds to the voltage buffer of Figure 5.

Figure 10 shows a normalized transfer function over frequency for the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5. The bipolar EF stage of Figure 17 suffers from a poor bandwidth due to the large output parasitic capacitance contributed by the bias current source (which has to provide about 20 mA bias current to reduce the output DC voltage down to 0.5 V). Due to the DC level shifter 3 of the voltage buffer 1 of Figure 1, the voltage buffer of Figure 1 achieves a much smaller current consumption. This smaller current consumption allows reducing the size of the current source CS1, thus reducing its parasitic capacitance, broadening the bandwidth of the voltage buffer 1 of Figure 1 with respect to the bipolar EF stage of Figure 17. The NMOS CS stage of Figure 18 exhibits a comparable bandwidth to the voltage buffer of Figure 1. The voltage buffer of Figure 5 has the largest bandwidth among the four cases.

Figure 11 shows an output return loss over frequency for the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5. Due to the large bias current, the current source in the bipolar EF stage of Figure 17 features a rather small output resistance, which seriously degrades the output return loss starting from low frequency already. Due to the reduced power consumption of the voltage buffer of Figure 1 (higher output impedance and smaller parasitic capacitance of the current source CS1, as previously mentioned), such circuit topology ensures a better output impedance matching. The voltage buffer of Figure 5 exhibits the broadest impedance matching up to even above 100 GHz.

Due to its push-pull architecture, the voltage buffer 1 of Figure 5 also guarantees superior linearity compared to the NMOS OS stage of Figure 18. Further, the voltage buffer 1 of Figure 5 is capable of withstanding a much larger output signal swing with respect to all of the other topologies (as visible from the total harmonic distortion plot shown in Figure 12). Figure 12 shows a 1 GHz Total Harmonic Distortion (THD) versus output voltage amplitude for the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5. In Figure 12, the output voltage amplitude is presented by the peak-to-peak differential output voltage amplitude Voutppd. Due to the small resistive output impedance of the current source of the bipolar EF stage of the circuit of Figure 17, the bipolar EF gain is even lower than -6 dB, thus degrading further the linearity of the previous stage connected to the input of the bipolar EF stage. In contrast, as previously mentioned, the (bias) current source CS1 of the voltage buffer of Figure 1 has a larger output impedance (i.e. having been down-sized thanks to the presence of the DC level shifter 3) and therefore its gain is about -6 dB (and not less), which helps achieving a better overall linearity.

The table of Figure 13 summarizes the performance of the four cases (i.e. the bipolar EF stage of Figure 17, the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 and the voltage buffer of Figure 5). Compared to the bipolar EF stage of Figure 17 and the NMOS CS stage of Figure 18, the voltage buffer of Figure 1 ensures low DC output voltage with no penalties in term of linearity and bandwidth while consuming less current. The best performance may be achieved by the voltage buffer of Figure 5 (as indicated in the Table of Figure 13) and the voltage buffers of Figures 6 and 7, which are differential circuits.

A BiCMOS technology (such as SiGe BiCMOS technology) is used for the voltage buffers of Figures 5 to 7. This technology (in particular SiGe BiCMOS technology) is suited for very high frequency applications (several tens of GHz). However, the same circuit concepts can be extended to other IC technologies, such as (but not limited to) CMOS technologies. In particular, the bipolar EF section (i.e. the BJT T1 in the single-ended version of the voltage buffer shown in Figure 1 and the BJTs Tla and Tib in the differential version of the voltage buffer shown in Figures 4 to 7 may be replaced by NMOS devices (e.g. NMOS FETs) without introducing significant penalty in the performance.

Figure 14 shows an example of a device according to the third aspect of the disclosure. In the example, the device is an electro-optical module (E/O module). The above description of the device of the third aspect is correspondingly valid for the device shown in Figure 14.

The device 101 (E/O module) shown in Figure 14 may comprise an analog electrical circuit 102 (e.g. an amplifier circuit) supplied with a first supply voltage and a digital electrical circuit 103 supplied with a second supply voltage that is lower than the first supply voltage. The first supply voltage may be 3.3 V or above and the second supply voltage may be IV or below. The analog electrical circuit 102 and the digital electrical circuit 103 may be implemented in different technologies. The analog electrical circuit 102 may be referred to as an analog section and the digital electrical circuit 103 may be referred to as a digital section. The analog electrical circuit 102 may be an analog chip. The digital electrical circuit 103 may be a digital chip. The analog electrical circuit 102 comprises a voltage buffer 1 as an output stage. The voltage buffer 1 is a voltage buffer according to the first aspect of the disclosure, in particular a voltage buffer according to any one of Figures 1 and 4 to 7. The voltage buffer 1 is cascade connected to an input 103c of the digital electrical circuit 103. That is, the output (comprising one output terminal in case of a single-ended topology or two output terminals in case of a differential topology of the voltage buffer) of the voltage buffer 1 is electrically connected to the input 103c of the digital electrical circuit 103.

Optionally, the device 101 comprises at least one photo diode (PD) 104 electrically connected to an input 102b of the analog electrical circuit 202 of the device 101. The device 101 may comprise at least one amplifier stage 102a, e.g. in the form of at least one transimpedance amplifier (TIA). The at least one PD 104 is connected to an input of the at least one amplifier stage 102a. The digital electrical circuit 103 may comprise an analog-to-digital converter (ADC) 103a and a digital signal processor (DSP) 103b. In case the device 101 comprises two or more amplifier stages 202, these amplifier stages are connected to each other by a cascade connection. As shown in Figure 14, the input of the at least one amplifier stage 102a is connected to or is the input 102b of the analog electrical circuit 102. The output of the voltage buffer 1 is connected to or is the output 102c of the analog electrical circuit 102.

In the light of the above, the first aspect of the disclosure and the Figures 1 to 13 disclose a voltage buffer with impedance matched-output and a low output DC voltage (< 1 V) suitable to DC-coupled solutions. This voltage buffer is particularly tailored to fully-integrated high- frequency broadband amplifiers where high linearity, impedance-matched output and low-DC output voltage are required, such as (but not limited to):

Broadband transimpedance amplifiers (TIAs) for optical communications;

Broadband drivers for optical communications;

Broadband amplifiers for wideband RF transceivers.

That is, the aforementioned voltage buffer according to the disclosure is configured for connecting an output of a broadband TIA stage for optical communications, a broadband driver stage for optical communications and a broadband amplifier stage for wideband RF transceivers to the input of a further stage, such as a digital electrical circuit.

The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed subject-matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.