Title:
VOLTAGE HISTOGRAM GENERATION
Document Type and Number:
WIPO Patent Application WO/2019/022825
Kind Code:
A3
Abstract:
An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling path to propagate a first signal at a first propagation speed and a second signaling path to propagate a second signal at a second propagation speed. The first propagation speed is slower than the second propagation speed, and both speeds are voltage-dependent. The multiple delay stages also include a respective time-of-arrival (TOA) detection circuit for each respective delay stage. The respective TOA detection circuit generates a respective stage timing signal indicative of a relative arrival time between the first and second signals at the respective delay stage. The multiple counters are respectively coupled to the multiple delay stages and have respective counter values. The respective counter values are incremented responsive to the respective stage timing signal.
Inventors:
COUTTS RYAN MICHAEL (US)
SOLKI SHAHIN (US)
PENZES PAUL IVAN (US)
SOLKI SHAHIN (US)
PENZES PAUL IVAN (US)
Application Number:
PCT/US2018/033975
Publication Date:
May 16, 2019
Filing Date:
May 22, 2018
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
H03K5/19
Domestic Patent References:
| WO2013039624A1 | 2013-03-21 |
Foreign References:
| US9459314B1 | 2016-10-04 | |||
| US20130293281A1 | 2013-11-07 | |||
| EP0547349A2 | 1993-06-23 | |||
| US7750305B2 | 2010-07-06 | |||
| US20110060975A1 | 2011-03-10 | |||
| US20070033448A1 | 2007-02-08 | |||
| US20160217872A1 | 2016-07-28 | |||
| GB2285373A | 1995-07-05 |
Attorney, Agent or Firm:
SAUNDERS, Keith W. (US)
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