MEMORY SYSTEMS

BACKG.RO U I>

jOOOt} An embedded, non-volatile memory system may receive & fsrst sn ply voltage VCC and a second supply voltage VCCQ item a host. Different hosts may supply the seeoasd supply vdiage VCCQ at different levels. For exam le, s»t«e hosts rosy supply the second supply voltage at 3.3 Volts lM Volte, while ether hosts may suppl the econd supply voltage at 1.2 Volts, In order to be compatible with different hosts and the possible different levels at which, a host may s»pply the seeottsi supply voltage VCCQ _S . embedded non-volatile me or s stems have beers configured with hard-wired configurations pi as ami/or diiferesst substrate designs, which are costly and difiieull o manage togistfoal!y. A less costly detection r»echa¾kra that ca detect various levels of the second supply voltage VCCQ a«d thai docs siot requite additional cofrritgnration pins different su strate designs ma be desirable.

|ftO02J In ad itions, embedded non-volatile memo y s stems may include analog circuitry configured to deliver powe m4 clock gnals to a core, m well, as perform other limctiorjs... The aoalog eireuiiry may recei ve a supply voltage ff m a host s stem with which It cos.nm«»ica1e Cwrettt co figurations of the analog circuitry may be robwst (i. e., their expos re to inherent noisiness of the supply voltage is minimal) as well as compatible with current le vels of the $« pl voltage. However, Ate to change* in host t chn logy, some host systems may supply the su ply voltage at le els lower tha the cu rent levels.. Current aaslog circuitry co»¾umtlo»s may not be compatible with these lower supply voltage levels. As analog eircnitry coafi ufatton that is compatible with different levels at whic different h sts ma supply the suppl voltage ω the analog ehetiitry may be desirable.

:t BRIEF DESCRIPTION OF THE DRAWINGS

[0003J The accompanyin d a ings* whi .are l«coiporsied in aad const&tie a part of litis spsciifcad n ilkstrais va ous aspects of tlte strveniioii md together with the description, serve to explain ts principles. Wherever eorave«ient _f she sam refe ence nu bers will foe used tht»iighoui the drawings to refer to die sa e or lite dements.

(00041 Figure I is a block diagram: of a» e ample e!ecfroaic syst m &8i .iadttdes a fomt s stem. and embedded multi-media card (eMMC) system of an. apparatus.

(0005| Figure 2 is a block diagram of circuit eam eaents of anal circuitr of the eMMC sysiem of Figure 1 that may be use to provide a core sup ly voltage and a core olta e stabitoto stg to cor© logic circuitry of the eMMC system,

[ 0MJ Figure 3 s a flow chart of m example method of supplying a core supply voltage aad a core volta e stabilizati n signal to c re logic circuitry of n eMMC system,

[ 07J Figure 4 is a bloc k diagram: efaa* example a an ement of various example eireidt compotients of analog circuitry a»d eircuU compos^ersts of core logic circuitry of the eMMC system, of F gure 1,

(00081 Figure 5 is a flow chart of an example method ofeonfigHriag components of analog circuitry of SR eMMC system in a high p we mode md a low power mode.

(0009| Figure 6 is a block diagram ai example anangemeat m which the circuit: eompmertts of analog circuitry are included in a single suppl voltage domain,

.DETAILED DESCRIPTION OF PRESENTLY PREFERRED EMBODIMENTS (OOIOJ Overview

[0 111 The following embo ments describe memory systems, devices _* a«d related methods ibr using a ost eloefe signal, s conflgtrre a e se regulator in a desired mods of operation. The following embodimeats also describe memory s s ems _* de ces, and related met ods for asalag e&ewlry rr ngements thai include multiple suppl voltage domains m ieh circuit c m onents of analog circuitry of the e MC s stems may be configured.

[Θ0Ι2Ι lit 8 Tim embodiment, apparatus may iocfttde COB? logic circuitry, host c ock detection circuitry, and a core regulator. The host clock detection circuitry may be configured to detect a host clock signal The core regulator m y be coftfEg red to receive a stippiy voltage, and supply a core supply voltage ¾a»d on th supply voltage to lite core tagie eiretiitry. The core regulator may e configured to supply the core suppl voltage as a regulated votege or an nregulated voltage based on the detection of the tot dock signal (00 | its a second embodiment, a metltod stay include; receiving, with a core regulator, a host supply voltage from a host system; detecting, with tot clock detection citcultry, a p esence of a host clock signal mi a host clock line; and sup l i g, with the core regulator, a co e suppl voltage as a regulated voltage or an tmregnlated vol age to cons? logic ekenftry based or? detecting the resence of the host clock signal.

| ^' 0014| In some example m odimen s,, the tost dock detection circuitry may semi a nottficaii n to host: supply voltage level detection circuitry in res onse to the detection of the host clock signal The host supply voltage level, defection circuitry may detect the level of the supply voltage in. response to receipt of the E¾otii catsorf _s j¾}d eoafigure the core regulator to su l the core supply voltage as either the regulated voltage of the unregulated voltage based on the de ected level of the supply voltage,

[<MH 5| In some example embodiments, hos supply voltage level detection circuitry may generate a control signal that configur s the core regulator to supply the core suppl voltage m the regulated voltage, and send die control si n l to the core regulator.

[0016] In some exam le ensbodimentsi, host Interface e eoitry may receive the host clock signal on a host clock line daririg a pr deteomaed time period, aad rece ve a. sjwhronimti command upon expiration of the predeterntined thne period. The host: clock detection e caitry may detect the host clock signal on the host clock line within Else pr^etan ne time period

00171 to some example eratwSiaents,. power on defection circuitry ma send a uots csttou to the core logic circuitry based m the detection of the host clock signal _* which

^• may rad cal? that the le el of the supply vol Sage is stable.

ftto SJ In some example embodiments, when the detected level of the mpply voltage corresponds to a first p edete««i«ed voltage level, feast supply voltage evel detection circuitry may genera e nd output a co regulator control signal so that the core regulator is configured to output t e core s pply voltage as me regulates! voltage, md hen the detected level of the suppl voltage c rresp n s to a seeos¾d predetermined vol (age level the host sapply voltage level detect on circuitry may ene ate sod o t ut the core r gulator control signal so that the core regulator Is configured to output the core supply voltage as the uaregulated voltage,

M1 | In some embodiments, m output of the core regulator is in a floating or high mpedance stale prior to being configured to supply the core supply voltage as the regulated voltage or the unregulated voltage.

(MMf Its some embodim nts, at least one second regulator may be configured to suppl at least one second supply voltage to at least one of; delay locked loop rcuttty, phase locked loop drcuitry, or a physical layer terfaee of the core logic circuitry. The- at least one second regulator may be configured to supply the at least one second supply voltage as either a regulated voltage or ass unregulated voltage to the core logic circuitry based on the detection of the h st clock signal.

fWilf .¾ a third ei«feodimeut» an apparatus may include core logic circuity and analog circuitry. The analog circuit y may include; first voltage doma n circuitry e ni tred to eceive a first host supply voltage fr m a hos system m both a first power mode and a sec nd ^• power mode. The first voltage domain cire-u tty rosy include first regulator circuitry configured to supply a first regulator su pl voltage to the sore Jogfc eipsuitry. The analog circtsity ma a include second voltage domain -circuitry configured its receive a second o-sA suppl voltage -from the host system in the second power mode but not in the first power ^• mode. The second voltage domain circuitry may include at least oae of: second regulator circuitry configured to sappry at test one second .re ulato supply vol age to the core logic eiretutry or clock eneration circuitry configured to suppl a clock signal t the cote logic circuitry.

(0022} to some sample embodiments, t e second regulator circuity may be configured to supply the at test one second regulate supply voltage to- at tes o e of: delay locked loop circ«¾ry, phase locked loop circuitry, or a physical layer interface of &e cote logic circuitry. The first voltage domain circuitry ma further include; bandgap generator circuitry c nfigured to generate a tefeene-e vo tap based on the first host supply voltage, and supply tlte re&teac olta e to the first regulator circuitry, l te first regulator -circuitry ma be configured to generate the first regulator sispply voltage based on receipt of both the first host supply voltage and the reference voltage. The first voltage domain circuitry may also include charge pump circuitry, and pre-regulator circuitry. The charge ptimp circuitry may he cots figured to enerate & charge pump voltage based on the first host supply voltage, and supply the charge pump voltage to the pre-ts-gutotor circuit ine pre-regulator circuit may be configured to generate a pre-regulator voltage based, on. the charge pump voltage, and supply the s sgwiat r voltage to the bandgap g nerator circuitry,

[Θ 231 In some example embo iments, p ocessing eia-u tey of the core logic circuitry may fee configured to defect that the analog circuitry is to switch from the first power mode to the sec nd p wer mode, and in spm to the detection, disable the second voltage domain circuitry while keeping the first vol tage dotnaia circuit enabled

3 fW f .¾ some exam le embodiments, the second voifage domain, circakry may include at least one of analog testiag circuitry or ?acess- |tege em raiwre sensor cireiuiry,

[0025! some example the non--val»tiJe memor systesi ma be as. embedded multi-media card.

| 2&| Other embo ments are possible, and each o f the ^mb dimeas can be used alone o.r together in c mbnati n. Accordingly, various embodiments will now be described, with, reference to the attached dawings.

(0028} As meatloaed in the baekgroaad seetion above, some host sysems may supply m embedded tmilti-medta card (eMMC) systm with a su ply voltage VCCQ ai 3,3 V or L8 V, while other host s stms ma supply the eMMC system with the su ply voltage YCCQ at a lower oltage, such as 1,2 V, The following emhodi«je¾ts describe memory s sems, devic s, atid related metods for using a host eiock signal to detentsine hen to detect a level of the supply voltage VCCQ is order to configure a core regulator in. a desired mode of o|jet»fc«. The follo n embodiments also describe systems, devices, apparatuses, and related methods for analog circuitry arran ements that include multiple supply voltage domains ia which circuit components of analog circuitry of the eMMC systems may be confgured*

f®029j ig, 1 is block dagam of an electronic system 100 feat includes; a host system 1.02 and an embedded multi-media c rd (eMMC) system 1 4. The eMMC system 104 may be arty e ory device or storage odule thai is configured o operate i» accordance with an eMMC standard or speciicatioa, such as a IE.D.EC Solid State Technology Association Embedded Mu!ii-Media Card Electrical Standard (hereafter referred to as toe "j ^' EOEC eMMC Standard") _* The host system 1.02 may be any electronic system or device that is confi ed to c mmaskale and/or operate with the eMMC system 104. |W30f As shown in Fig. i , the sMMC system ! 04 r«ay iachide no»~v®taiile memory 10\ wlfch may hekide a uralit of n u-voatiie memory ele«ie»ts or cells, each configured to store ne o awt¾ bids of data. The nou-voJatie memogy eiemeats or cells may e aay suitable nonvolatile me or cells, su h as NAND Hash inesnoiy oells and/or NOR flash ^• memory cells its a two di ensdnnat andor three dimemional configuration. The memory mite may take tb© f m. of .solid-stale (e.g., lash) memory cells and can be ene-titne jrogtamm-abte, few-fee programma le, or maay-time programmable,

(Θ0311 The sMMC system ! 04 may also me¾sk core l gic cratry 108 that perfoms me oy a«wmg«*ne«t ftoctbas lot the storage of data in the nonvolatile memor 106, Ex le- memor management fimeliotss m y iochsde, but not limited to, communicating wit the host system 102, me lading receiving, handling, atxi .responding to ost equests or ommands, such, as read, write, erase, and status reqwe¾/coj»ma«d rece ed fmm tfee host s stem 102; ibnuattmg the aoiwoiatile memory 1 61<& ensure k is p ratng property;

mapping out bad memory cells; allocating s re cells to be substituted for oe tailed ce¾ am! tran&Hioaing tie eMMC system 104 between different sate , operation mode, and/or power eens nintk»n modes, In o eaton, when the host s stem 102 needs to read data from or write data to the ami-volatile memory *βί>, it ma commsntcttle with the core logic cireaMry 108. If the h st system 102 provides a logical address to which data is to be i¾ad/ nits¾ the o».t¾ lo c eireaaiy 1 1 may convert the logical address received from the host s stem 102 to a physical address in the nonvolatile- .memory 106. Other memory »¾anages*e»: functions may inclade« bm arc riot limited to, ea leveling {distributing writes to avoid wearing oat specific blocks of memory that would otherwise be repeatedly written to) and garbage collection C after a block in full, moving only the valid pages of data to a new block, m ike Ml. block cart be erased nd reused). IW321 .¾ addition, the eMMC system 1 4 may include a m mory iatertaes (1 F) ! that provides latetisce etweea the ewe logic circuitry 108 a«d the mm- volatile memory 106. The logic circuitry 108 raay be conitgwed to communicate data aad c msaaads ill the aomvolatUe memor \Q$ via the . emo y interface 110 to store data in ami/or .read data from the non-volatile memor 106. The eMMC system KM m also bscisifc a host interface 1 12 to cotmminicste with the host s stem 102, Tie host interlace 112 .may e coupled to a communkttAions bm 1.1.4 on which the asterfaee 1.1.2 sends and receives signals to and item the b st system 102. The host interface 112 may include driver ctremtry eo figared to generate the si nals, such as by p lli g ti to a high level and pullfag down to a low level vo tages m the li nes of the et»»tmsnk».tioM hiss 11.4,

|iMBSJ The commBakati ims i 14 may tnchtde a host d ck line CL¾OS H which the .host system 102 tntsy send a ^' host clock si nal to the eMMC system 1.04; data Macs DAT|7:0J (i.e., eight data lines DATO to DAT?) m which the host sys em 102 s d the e MC s stem 104 may eoKum iikat data, si nals with each other; and a command line CMD on which the host system 1.02 mil the eMMC system 1 4 may eommunk&te eomma»d signals and responses with each other. The data signals may include data that the host system 102 wants stored in or read item the eMMC system 104. Command signals sent item the host s stem 102 may iststeet or equest that the eMMC system 104 perform some act on saeb as perforin operation,, transits on into a certain stats, or res on with requested inf rm ti n, as examples. The response signals sent from the eMMC system .104 may acknowledge receipt of the command signals, indicate that the Instructed actioB. is p rformed, or include the .re uested t»l¼m»iksj, as e amples. The host clock si pat may set the freqyeaey of the com unic ti ns bus 1 1 and/or control the data flow by providing the tisses and/or rates at which the clock and data signals may fee sampled by the eMMC system 04.

S IW3 J The eMMC s stem ! 04 may also irselade analog eircridry 1.16 t at p vides a lur lity f regulator supl voltages to the eore logic circuitry 10S _:5 including a core wp≠y voltage, 1st addition, the analog circuitry 116 disuitry may rovide a bse clock si nal CL i Si;, one or more p c s^vl^^tem ratare (FVT) s nals,, md a core voltage stabilization sgnal VDD_CO E_0K indicating hethe ths? core su ply voltage is at a stable level The core logic circuiry 1 8 may mad one or more control signals to the analog circuitry · to cottflgwre, pro ram, enable, andor disable various components of the analog etrctiir 11.6, Farther details of She analog circuitry 116 are escribed bel w.

(0035| Accorttiag to the JEDEC eMMC Standard, the eMMC system 104 iay be configured, to operate in a plurality of diSereni. operation modes, md in each mode, be configured, m one or more states. The operation modes may include a device identification mode daring which the host s sem 02 m&y eset the eMMC system 10 , validate an o fit a voltage nage md access mode with the eMMC sysem 104, arid identify the eMMC system 104 md assign a Relative Devke Address C CA) to the eMMC system 1 4, In addition, the opeation -modes may include a data transfe raodte in which, the eMMC system is ready to handle host c mm nds associated w ith the transfer of data, such as host read, and write commands, auditor perform data storage and/or transfer operations. Is some eMMC c n%umtkm&, the eMMC s stem 14 m.sy be also eanfigttted to operate m a boot mode, during which the host system 102 may read certain boot date from the eMMC s stem 104.. Other operadon modes may be possible, snd n. general, the eMMC system 104 may be initialized in the device identification mode sad/or in the boot mode before it enters tato e data transfer mode.

[ 0MJ efoe: the eMMC system 104 enters into ihe operation, modes, the eMM s stem 104 may perfcem an Initial power up process (or power cycle) wit the host system TO, DtiriHg, the power u pj ce&s, the best system 102 may begin supplyng a plurality of supply voltages to t e eMMC syst m 104 for the com oneuts of the eMMC system 104 to operate. The pbrslty of supply votages; ma mc ide a first supply voltage VCC sappijed m a first suppl Urn I \M and a s cond supply voltage VCCQ supplied m a second supply lin 120. As sh wn w Fig, 1 , he first su ply voltage VCC may be sent to the non-vohutle mem ry 106 nd the memoy interface 11 . in addition, for some example configurations of he eMMC s stem 104. as described in fttriher detail below and deno dotted arrow 122, die ftm swpply voltage VCC may also e supplied to the nalog ciic iliy 1.16. Additonall , the secoad sup l voltage VCCQ ma be sent to the host interface 1 2 and to the analo c c iry 16.

[0O37| The host system 1 2 may foe configured to supply each of the first sup ly voltage VCC a»d the second su l voltage VCCQ at levels conrespottdiog to oae of a plurality of predetermined voltage levels, .Example predetermined voltage levels, may include 33 Volts (V), 1.8 V.1,2 V, although other red termined voltage levels may he ossi le, in addition, each of the *edetmm∞ voltage le vels may be associ ted with aud/or be within an.

associated voltage rang havtag a pre etermine mini um level and a ^deermine

.maximum level, Depeading on the configuration of the host system J 0:2, di&ere host s stems 2 ma supply at least the -second supply voltage VCCQ at different levels. To i!hsstmte, some e am le host sstems 102 may supply the sec nd supply voltage VCCQ at a level corresponding to the 3,3 V level of the LS V level while othe example host systems. 1.02 may supply the second supply voltage VCCQ at a level corresponding to a lower predetermined voltage level, such as 12 V.

As described m farther detail below, a core regulator of the analog circuitry 116 may receive and he powered by the second supply voltage ^' VCCQ. Upon receipt- of the econ snppl voltage VCCQ, the eote regulator may generate the core supply oltage and supply the core supply voltage to the cor logic ebmstsy. The core supply voltage ma be a re eated voltage sn that S¾s core re ulator may be configured to mainta n the core supply voltage at 8 target voltage level and/or within a target voltage rauge. The COM; rep ator may incfede m operational m lifier (op-einp) or ot er similar circuitry to generate sod regulate ^• the core supply voltage. Such egulator circuitry may require a .sufBeietuly large voltage drop or difference between S e level of the sscossc! sup l voltage ^' VCCQ being input to the core regulator and lie tar et level of the co e supply voltage «g output to order for the regulator circuitry to operate pro erl or as desired. As such, if the le el of the second supply voltage VCCQ is mileiemly greater than the ta get level of the cor supply voltage, then a voltage drop or difference be een the n u aud output of the core regulator may be sufficiently !arp enough for i core .regulator to ict on or operate properly, fo this situation, w en the voikge drop is sufficiently large, the core .regulator may be eorrfigared to o erate normally to gen rate a regulated core supply voltage. Alternati ely, if the level of the seeontl supply voltage VCCQ fa sufficiently class to the target level of the core s ly voltage such that the voltage- drop or ife aee bet eeo the input and output of the core .regulator is too small for the core regulator to ftmciioo or operate properly, the secortd supply l age VCCQ that is supplied to the core regulator's inpu may be bypassed directly to the cots regulator's oatpat without the core regulator performing any reguiai u. That is, the cere regulator may output its cote supply voltage as ass unregulated voltage.

(0O3 | hi orde for the core regulator to be capable of handin different levels at which different host systems 102 may supply the second supply voltage VCCQ to the eMMC s stem 104, the core .regulator may he oon%»rab3e in b th a regulation mode and a bypass m de in. the regulation, mode, the core regulator im be e n!lgured to output a regulated voltage, in the bypass mode, the cere regulator may be configured to output an unregulated voltage. As described in furthe detail below, the analog circuitry 1 16 may be configure to detect he level of the second supply voltage VCCQ In order to determine whether toil configure the care regulator m the regulation mode or the bypass -mode. The analog cire»ltry I lf> rmy further fee configure to determine when to detect the, level based on detecti n of presesee of the boss clock signal being coaununicate . on $te host clock line CLKJWT of the coramanicatioTO bm 1 4. The analog circu itry 1 16 may further use detection, of the host eloek signal to send the- core voltage stabilisation signal VDDjCORE _w 0K.

gIMMOJ Fig, 2 shows a block diagram of cirentt components of t e analog circuitry 1.16 thst ma be ased to provide a core supply voltage VDD _. CORE and a core voltage st¾bifetitto« signal VDD_CORE_0K to the core logic cironhy 108, The e«re logic circuitry I OS *aay recei e the eore stippty oltage VDD_CORE a d the core voltage stabifatkai sig al VDD CORE _.. OK. The core logic circuitry 108 ma be powered ith the core su pl voltage VDD _. CORE in order to perform ts memor m&nagemenl factions-. Conversely, without being powered with the ewe supply voltage VDDjCQRE- the core logic circuitry ltt8 mm not e able to perfo m its memory mana ement ftneti m

|@Q41J The core voltage sta i¾atic« signal may function as a reset sl ial t¾at configures the core logic ekew try 1 8 mars active mode or » set mode,, la the active mode, the core logic circuitry 108 may be responsive to host commands. Alternatively, in the reset mode, the c re logic circuitry 108 may be unresponsive t» host commands, if the core voltage stahilk ion sigoal VDD. CORE. OK. indicates thai lite core supply voltage VDD...CORE is stable, then the core logic circuitry 1 OS may be configured in the active mode and be responsive to host commands. Alternatively, if the core voltage stabilisation signal VDD _^ CORE _^ O ind cates thai the core supply voltage is not stable (or testa le}, then the core logic clrenitry 108 raay be configured in the reset mode and be unres onsive to host comm nds

[$942- J The analog circuitry 1 16 may include a o e regulator 202 that U configured to generate .sod provide he core suppl voltage VCC _^ CORB to the core logic circuitry I OS,

n The analog circuitry i 16 may also inc ud power on detection circuitry 204 t t is c nfi ured to generate mid provide the core witege stabili^t oB signal VDDjCX)REjQK>

|0Μ3| The analog circuitry U6 ma fart er luc-lade additional circuitry that Instructs or identifies to the core regulator 202 and the power ow detection circuitry 204· when, at what level, and or how to be configured in order for the core regulator 202 to generate and rovide the co e suppl voltage VDDjCORE ami for the power on detection circuitry 204 to enerate and rovide fee core voltage stabilisation si nal VDD _. CORE _.. OK, T e additional circuitry ma Include feast clock detection circintry 206 is configured to detect the p esen e or absence of the host clack s gnal on the tot clock hoc CIKHOST _* whic in M may be m indication that he host system 102 has sent the host clock, si nal and or that the host. Interface 112 has rece ved the host clock signal horn the host system 1 2, Additionally, the analog eirenihy i 10 ^" may kcktde VCCQ detection circ itry im configured to detect a level of the second 8«pply voltage VCCQ. As s own in Fig, 2, each of the ecre regulator 202, the power a detection circuit 20 , the nest clock detection eitcuitty 206, and the VCCQ detectio dreeitfy 208 may he configured to receive the second s a pl voltage VCCQ to perform their respective functions.

( &044J During the power up process, the host system 102 may begin sup lyi the first and second supply voltages VCC, VCCQ to the eMMC system 10 . Initially, the levels of the first and second supply voltages VCC, VCCQ ma begin *%«ip½g op from β V (or some other initial voltage level).. When, the tot s stem 1.02 detects that the second supply voltage VCCQ as reached or ramped op lo s mi iauaitt level associated with the predetermined voltage level at which the second snpply voltage VCCQ is to be supplied, the host system 102 ma begin sending the host clock signal on the hos clock line CL ^' BOST to the host interface ϊ 1.2. The host s stem. 102 may then watt a predetermined, time period while sending the host clock, signal, O ee the pr ^etwnined time period. expires, the host s stem 102 &y

B s nd to he eMMC system 104 m initial synchronisation command CMD 1 to start aegotjating the operation voltage range at whic the fiost system ! 02 d the eMMC system 104 are to comtmuwcate signals on the com nmcaiioas bus, ί 14. The ptedetesmfeed m period, o herwise referred to as a sequence length, is the lon est of: am millisecond (I nis), 74 dock eyeks of the host clock signal, a supply ramp-«p time, or a boot operation period duri g which t e s C system 104 am be to the boot mode, Aceoi¾S«gl>% the tos system 102 may ait a minimu of I me from the time it begins ssmli g. the host dock signal before sending the h synchronisation comma d CMD1.

f 00451 Since the hos sys em { 02 taay not begin s n ing the h st clock si nal unit! the second mp≠y voltage VCCQ has reached the associated tnmimum level, then detection of the .host clock signal may indicat (hat t e mmimum level has beers, reached, which, m turn ma indie-ate an appropriate time to detect the level of the sec ond suppl voltage VCCQ to determine whether to set the e«ie regulat 202 in the legolatlon mode or the bypass mode. Otherwise stated, if presence of the test d ck si nal m the host clock line not yd been detected, t en the second supply voltage VCCQ may not yet have reached o mmped up its minimum level, which ma indicate thai it is too soon to detect the ievd of the second supply voltage VCCQ hi order to determine whether to set the core regulator in the regulation ode of the bypass m de.

(004&) As shown to Fig. 2, in mm example configuration,, the host clock detection circuitry 206 may have an input 210 eonpled to the host dock line CL _¾ OS _T to detect presenc or absence of the host dock signal on the host clock line CL¾osr.r÷ Other example configurations may he ossible. For example, the host clock detection circu try 206 may receive the host clock signal from the host interlace 1 12, as denoted ^' by dotted arrow 212, in order to pe form the etecti ,. |W471 When the host clock detection circuitry 206 detects t e host dock si nal the- host clock detection eire¾|try 206 asay notify the VCCQ detection circuitry 208 of the detection The host clock detection dreuitry 206 may do s by seadiog a notiikaiioa sjgaal

VCCQJ AUD to the VCCQ detection circuitry 208, sach as by tmnsUioning a level of the ^ratification si nal V CQ _^ VALID being utput fejra ¾ low lev l to a high level, or vice ve*m. The host clock detection dreuitry 20 ma tndude my of various circuit

coafigumt ns to efect r mc® of the host clock si nal on the host clock line€L¾¾ , In one mspk, the host clock detection circuitry 206 ma include counter drsuitry that detec s clock cycles s d cotmts the ¾ iaber of clock c cles it detects. When the number of cl ock cycles teaches a threshold OMJtbe , the counter circttttiy may etermine that a host clock signa is pmmiit md d the »oUilcatioa signal VCCQ _.. VALID to the VCCQ detection eireairry 208, la another example, ths host clock detection eireairry 206 «¾ay kelade edge detector dredtry configured to detect rising and ar falling edges order to detect presence of the host ctock signal If a number of edges detected by the edge detector dretatry .reaches a threshold numbe , then, the edge detector circaitry may etermine that a host clock si nal k resent and mud the riotifieaiSan signal VCCQ.. VALID to the VCCQ detection eircaitry 2 8, Other circuit configsiratioas for the host clock, deiectioa circuitry 206 may be possible.

(00 81 ¾ res onse to receipt of the notification signal VCCQ.. V ALID, the VCCQ detection circuitry 208 may de-tors tse to detect the level of the second su l voltagfc VCCQ and. detect what that level is. Based on the detected level, the VCCQ detection circuitry 7M may determine whether to configure she C PS regulator 202 in the regulation mode or the by ss mode. In particular, if the detected level of the second supply voltage VCCQ indicates, {hat the voltage drop or difference between the level of she second supply voltage VCCQ and * target level of ths core supply voltage VDDjCttRE is s cloiily large eaoagh for the core regulator 202 to properly fancttoa, then the VCCQ detection circuitry 208 rosy

IS dete mine to eesft ure tie cone regulator 202 in toe regiiaifert raode _* Alternatively, If She detected level of the seso«d supply voltage VCCQ indicates hai the voltage drop or difTemtce between the level of the second supply voltage VCCQ and the target level of e core supply -voltage YDD_C0RE is too small for the co-re regulator 202 to properly fraction, then the ^" VCCQ detection circuitry 208 may determine to configure the core regulator 202 m the bypass mode. Based the determination, the VCCQ detect on etaitry 208 may output a control signal VCCQ JBV to the core .regulator 202 thai configures the core regulator 202 in either ihe eg l tion mode or the bypass mode.

f0t | As ait iltustetron. In one esat tp e contlgatatat, the target level of the ewe supply voltage VDD _.. C0R1 may e= 1.2 V. For hos configurations where the host s stem 1.02 sends ihe second supply voltage VCCQ at LE V or greater, the voltage dro or difference ma be la ge n u tor the core ulator 202 io operate properly. As suc , ft sna be desirable for the core regulator 202 to operate hi the regulation mode an monitor the level of th core supply voltage VDD CORE to .maintain the level wttfem a voltage rasige such that the core sup l voltage VDD CORE is a regulated voltage. Alternatively, voltage levels lower than LB V may provide too small of a voltage drop for the core regulator 202 to properly function. As such, up n receipt of a second supply voltage VCCQ that is less than 1, 8 V, the core regulator 202 ma operate k the bypass mede in which the core regulator 202 directly sends the second supply voltage VCCQ to its output and outputs the second supply voltage VCCQ as the core supply voltage VDD CORE without performing assy regulation. That is, in the bypass m de:, the core regulator 202 may not monitor the level of the core supply vol tage VDDJ20RE to .nuantain. the level within the voltage range. la this way, in the bypass mode, the core supply voltage VDD CORE being output (i.e. _s the second supply voltage VCCQ) is art unregulated voltage. Accordingl , during power up, if the VCCQ detection eifcuiny 3 8 detects the level of the second supply voltage VCCQ to oe I J V or greater, the VCCQ d fection cireukry M ^' M may mtfmX the control signal VCCQ JMV at a level or in a way that conf gures the core regulator 202 i the regnlalion m k, Alternatively, f the VCCQ detection circuitry 208 detects the level of the second supply voltage VCCQ to be less than I M V, the VCCQ detection. circuitry 208 msy output the control si nal VCCQ-HV at a level or in a way that configures the core regulator 202 in the bypass mode _*

|M5QJ M mpou to receipt of the control signal. VCCQ _. ί IV, the core .re ulator 202 may eoafigure itself to either the regulation mode or m the bypass mode and begs n su l in the cor supply voltage VDD_CORE according to the mode in which it is configured, fa the reguMot* mode, ths core o¾platot 202 may employ feedback to sxtottftor the level of the sore supply voltage VDD CORE in order to maintain the level of the core supply ltag

VDDjCORE at a coa iaat level and/or within a voltage range, in this way, the core regulato 2t>2 supplies she core supply voltage VDDjCORE as a regulated ltage. In the bypass mods, feedback may not he employ swea thai the le vel of the cote supply voltage

VDDjCORE is not moaiiored to be maintained at constant level att&or within a voltage .range. In this way, the core egulator 2Q2 su lies the core suppl voltage VD.DjCORE as art unregulated voltage. Also, i» some example configurations _* prior to receipt of the control signal VCCQJR.V, the output of the core regulator 202 may be to. a high impedance or floating state,

{0OS1J in addition or alternatively, regulating fee second suppl voltage VCCQ to generate the core supply voltage VDDjCORE may include reducing a noise c m onent of the secon supply voltage VCCQ aad ar generating the co e supply voltage VDD j ORE to have a higher power supply rejection, ratio (PSRR) than the second supply voltage VCCQ. The second supply voltage VCCQ may have so undesirably high noise c m onent for varioas reasons, such as due to switching performed y s itching egulators of the host system 1 2 t generate the second supply voltage VCCQ, high a id low vol tage level s itching performed by ths host interface circuit 1 1 , and/or changes in cu ent draw on ths, c municati s s 1 14 aod or on ooe or oth of the supply lines 1 IS, 120. Other reassess ma be possible, Reducing she m m p t of the second supply v ltage VCCQ ma mprove or optimise performance of the core logic circuitry 108,

|ftftS2| In a ition, m s me example configurations, regulating the s cond supply voltage

VCCQ may include steppmg-dowit the level of the seeand supply voltage YCCQ -Le„ the level of the core saspply voltage VDD_OORE is lower fha« the level of the seeond su pl voltage VCCQ. For example, If the level of the s c nd su l voltage VCCQ \s X ,8 V, md the target level of the core supply voltage VDD.CORE h 1.2 , then tegulatmg the second swp ly voltage VCCQ to generate the core supply vo age VDD _. CORE may include stssppingHio ti the lew! of the sec nd su pl voltage VCCQ from 1.8 {& 1,2 V,

W53| Alternati vely, if the core regulator 202 is con%ured m the b ass mo e, thsai. the core regulator 202 may the secoad supply voltage VCCQ It is receiving at Its input diree to its output without peribrosog regulation. As such, in the bypass mode, the cere .regulator 202 does not monitor the level of the core s voltage VBD _.. COR1 to maintain the level at a constant level or within a voltage mage, the noise component of the core supply voltage VDDjCG ^' E ½ not reduced compared to die noise component of the second su pl voltage VCCQ, and the level of the core supply voltage VDD .CORE is not stepped-do n fr m the level of the second su ply voltage VCCQ..

|8054j in addition to contlgnring the core regulator 202 in either the .regnla&n mode or the bypass mode, the VCCQ detection circuitry 208 may isstruei the power oa detection circuitry 204 when lo send the core voltage habitation signal VDDjCOREjO . hs second sup ly voltage VCCQ reaching the associated mmhmnn value may indicate that the seeofid supply voltage VCCQ, and in tana the core supply voltage VD.DjDO.Ri3, Is at » stable level for the core logic circuitry to operate. Since the host system. 102 sends the hos clock

IS signal once the second supply voltage VCCQ reaches the associated minimum level, then the time at which ie host clock sign l s comiminkrated he host clock Hoe CLKR^}- ma be an appropriate time at whic to notify the core logic circuitry 108 thai fee core supply voltage 3D ..CO.RE is stable. As siseh, when the VCCQ detection circuitry 20S receives t e notification signal VCCQ JV ALfD irons the host clock et c io clrcnnry 206 that the host dock si nal h bei g communicate , the VCCQ d tection eiretntry 08 may enable the power on deleeiioa eireihfcry 204 to send the core voltage stabilisation signal. VDDjCOREjDK to the core logic drarito 108,

(©055j to the examp e con ¾ ration shown in Fig. 2, the control si nal VCOQ_HV sed to configure the core egulator 202 1» the regulator and bypass modes may also be used to enable the wer o defection ekoiHty 204, As show in Fig. 2, the core regulator 202.may also su pl the core supply voltage YD.D_CORE to the power on detection ei«¾¾ry 204. When tine power OR detection circuitry 204 is enabled in resp nse to eceipt of the c ntrol grsaf VCCQ..MV, then when lie power on detecti n ekeaitry 204 senses the core strppiy voltage VDDjCORE from t e core esistor 202, t e po er no detection eireoiiry 204 may determine thai it is t me to notify the core logic circaitry I OS that the core supply voltage VODjCG ^' B is at a stable level to tum the power on detection eirenitry 204 may send the core voltage stabilization signal VDDjCORE _OK to the core logic citciatty 108, s ch as by transitioning the level of the cor voltage stabilization signal VDD .CORE . OK from a low level to a high level or vice verm. In response to .receipt of the eore voltage stabilization signal VDD... CORE.. OK, the core logic circuitry 108 may accept and allow itself to be powered by the core supply vol tage VDD..CO RE,.

|W56| Alter the eore logic cirenitry 10S- ers: up, the core logic eireuhry 1 (M may notify the host in erface 1 1.2 that the core logic circuitr 108 has p e ed^ snch s$ by sendin a notification signal or mes age to he lost Interface 1 12, as shown by the arrow 214 m Fig _* 2. Upon receipt and/or detection of the m»til1catioa» the host i erftee 1 12 may send a si n l or message to the host system 102, s»eh as by us n the e masd ¾e CM ^' P a-od/or o»e mo e of TO data lines DA |7; ]v to indicate iat the core logic csrctdtry I OS Is ready to coramanieate Uh the host system 102 mdfar process host eonsraands.

|ftftS7| Fig. 3 is a flo w chart of an example method 00 of suppl ing a c ore supply voltage arid a core voltage stabilisation signal to core logic eiretatey of an eMMC system. At block 302, Ihc eMMC system may begin receiving a first sup ly voltage VCC and a second sup ly voltage VCCQ from a host system, At block 30 _s . She eMMC system may begin receiving a h»st clock signal iwm the h ast s s em on a last clock line of a eon mnMcattoos bus, 'He host clock signal may be eceived by at leas a hos interfa e of the eMMC s stem. As previously described, the host system ay begin settdirsg the host clock signal when h det cts that the second supply voltage VCCQ has reached a mitiimera level associated with a p eds srmmed voltage level at wh ch the seeo supply voltage ^' VCCQ is to be su plied M58J At block 306, host clock detection circuitry of the eMMC system ma detect _. res ttce of the host clock signal mi the host clock line. In some exam le methods, the best clock detection circuitry may detect the presence of the clock signal by being directly coupled to the host clock lias and receiving the hos elock signal when it is present la other example ftiedttsds, the host dock detection circuitry a detect t he prsseoes of t he c lock sigiial by receipi of the host clock sig al or some other signal indicative of receipt of the clock signal from the host interface. Additionally, at block.306,. in. respons to detecting the presen e of the h st clock signal, the mi clock detection clicojtry may notily VCCQ detection circuitry of the detectiofs of the host clock signal.

[005$! At block 30% the VCCQ detection circuitry rosy receive the tjoiificatloa irons the host clock detection circnitiy, and ¾ es nd determine to etect the level of the second sttpply voltage VCCQ It is receiving, and delect what that level, is, At block 31.0, the VCCQ detection circuitry may dete mine whether to configure a core regulator in a regulation m de or i« a bypass mode based on the deteeted le vel of the second s ppl voltage VCCQ, As fweviously descri e^ if he level of the second supply voltage VCCQ k high eno g - such ^• thai a difference or voiiage drop between the- detected level and a target level of the core su pl voltage is large enough for the core re ulator to properly o er te _* ften the VCCQ ttetetion circuitry may 6et mm- to cordigore the c e regulator in the .re ulation mode. Altero.ative.ly, if the le el of the second supply voiiage VCCQ is at a level such, that the diff rence or voltage drop bet een the detecte level n a targ t level of the cote supply voltage is too mil for the core repiator to properly operate, fees the VCCQ deteet os elteaMry may determine to configure the core regulator in tte bypass m de.

\<Wmi At block 312, the VCCQ detection circuitry may send a control signal at a evel or in a way th indicates the mod its which the regulator is to be configured according to the tfetermioatloe, Additionally, at block 312, the VCCQ detect lost drcdtry rasy se«d art enable signal to power on detection dreuiiry that enable* the power on detection circuitry to send, lie cote voltage stabili¾aU.on signal to the core logic dtc itry,

[0 61} At black 314, the core regulator may receive the control signal and. in res onse, be configured in. either the -.regulatian mode or the bypass mode. In addition _* at block 314, the core regulator ma begin generating and supplying the core supply voltage in &t¾o anee with the mode in which it is. configured. At block 316, the power n detection circuitry ma receive the enable signal from the VCCQ detection circuitry and become enabled.

Additionally, at block 316, hen enabled and upon senstug the core suppl voltage from the core regulator, the power on detection circuitry may output to the core voltage abil Nation signal to the cose logic circuitry to indicate: that she core supply voltage is stable.

[00611 .Referring back to Fig, 1, after the power up process and the device becomes iraualiK-ed during the device identification and/or boot modes, the eMMC system 104 may e»ter into the data, transfer ^' mode, as previously described. When operating in the data transfer mod , the eMMC s stem J.04 may be eoot!gursd in a plurality of states mvo! mg the act ve traas-ffer f data, tticladtaf a transfer state, a b s-test stale, a seading-dala state, a receive-data state, and a rogtstmming state. In tbe data toa ter tnode, the eMMC system 104 may also be configured in a st nd y mode, in which the eMMC s stem 104 ^sta s by" at ans to he configured to one of tbe s ates u olving tbe ac ive transfer of ata.

Additionally, the eMMC system 1.04 may be configured a sleep slate, m which power c nsum ti h mimmimi or at le s lower than when operating in the other slate* while operating In the data tr nsfer mode. When in the sleep state, the eMMC s stem 11)4 may be responsive to a limited number of eom.nt3ixte sent by the tost s stem 102, such as only a sleep awake command CMD5 that transitions the eMMC system between the sleep state ami the standby st te, and a reset command CMD0 that resets the eMMC system 1.04. fa ad ition when the eMMC system 1 4 is ia the sleep state, the eMMC 104 may receive the sec nd supply voltage VCCQ but not the first su pl vo tage YCC f m the best system I 02, whereas the other states, the eMMC s stem 104 may receive both the first supply volt ge VCC and the second sup l voltage VCCQ,

(ΘΘ63 ^' ! Fsg. 4 shows a block diagram of an exam le arrangement of various circuit components of the analog tireuitry J t o, as well m components of me c re logic circuitry I0§ in more detail. The core logic circuitry 1 8 may include processing circuitry 402. which may be configured to perform the memory management inactions of the core logic circuitry 108, The processing cjtecaitry 46:2 ma include hardware or » cotn tasitoa of hardware and software. For example, She procetfsing circuitry 402 may mclnde a central processing unit,, an application specific integrated circuit (ASIC), a field programmable gate array (FPQA a digital logic circuit, an analog circuit, a combination of discrete drcaks, gates, or arty other t e of hardware* or a combination thereof

n [ 6 ^' | The core logic einjr try 108 may aim include memory 404, which may include volatile memor (eg,, radom access memory (RAM)), non-volatile memory (e.g., read-onl emory (ROM)}, or a com inati n thereoC The memor 404 ros s are soft a e or firmware instructions and or certain data strtietures, such as address translation data stoci e thai t e processing circuitry 402 may ccess and/or and execute to perform at least some of its memory mgs mm fractions. Additionally, ihe mem r 404 ma te porarily store data that is to be iransferred to and stored in the nonvolatile memory 106 such as in .response to a h st write command, and/or that was retr eved fr m the non-volatile memory 106 and is to be sent to the ^' host system 102, such as m res o se o a host read eotnnsand. (00651 ¾ cote logic eiretrftrv 108 may a so include delay-locked loop (DLL) crreuhty 406, phase-locked Imp (PLL) eireuUt 408, and a physical layer interface (PHY) 410, The DLL circaitry 406 may be nsed for clocking to tramfer data between the non-volatile memory 106 and the memory interface 10, The PLL circuitry 408 may generate different docks with diffeent clock rates or frequencies for components of the processing chcnltry 402 that operate in difeest d ck domains. T e physical layer interface 410 may provide aft electrical Interface between the host mterfaee 112 (F g, 1 } and the proc ssin circuitry 402, (00661 i» the example arrangement s e n in Fig. 4, the circuit eomponestts of the analog eireaitry 116 may be arranged or configured into one of a p!araifty fdiffee su l voltage doma ns, including a first supply voltage VCC domain 412 and second supply voltage VCCQ domain 414, The circuit components arranged in the first supply voltage domain 412 may b configured to recei ve a»d½r o erate based on the first supply voltage VCC, and the cactdt components arranged in the second su ly voltage VCCQ domain 414 may be configured to receive and/or operate based on the second supply voltage VCCQ.

[00671 For the example arrangement sho n in Fig. 4, whether a circuit component of the analog circuitry 1 16 is in the first supply voltage domain 412 or the second supply voltage dorsiairt 41 ma depend oa hether that dmrit component operaes or s powered on when the eMMC system 104 is w the steep state, Those elreuli compwrrts thai do no operate and/or are oof powered on daring the sleep state ma he ©oaligwed I» the fist supply voltage domain 412, mid those circut eompoaenis: that do operate aud½r are owered oa during the sleep state may he configured in S e secon su ply voltage domain 41.4,

immi !n fwta detail, t e first sup ly oltage dotraia 412 may include- a DLL .^galator 416, a PLL regulator 418, a PHY re ulato 20, analog testing eiretutry 422., PVT sensor eiretdtry 424, md clock generation (or osel «r> cicus try 426, The DLL regulator 4.16 may he configured to supply a DLL re ulator supply voltage VDDJ5LL to the DLL circuitry 406 to p we the DLL circuitr 406, Similarly, he PLL regulator 418 may be configured to s»pply a LL regulator supply vol ta s VDD_PLL o the PLL circuitry 08 to po e she PLL circuitry 08, and the PHY gulao 420 ma he configured to supply a PHY regulator su ly volt e VDD_PHY to the physical, ittterfitce circuitry 4Ϊ0 to power the- pbys!e&I i terfoee circuitry 10, In the ex mple con uration shown itt Fig, 4, each of the regulators 416, 4.18, 420 ma be configured to receive the first supply voltage VCC md generate iheir respecti ve regulator supply voltages based on the .first supply voltage VCC, Additionally, the care gk circuitry I08 _s . such, as by using th.e rocess.iag drenitry 402, m y be configured to setid -eoatrol si EiaM DLL. Reg.. Crstrl, PLL _^ Eeg _^ Cnii PBYJtegjCsttti to respective DLL, PLL, and PHY reguators 16, 418, 420 to enable- and disable the respective DLL, PLL, and PHY regulators 416, 4.8, 420, When enabled, the PLL, DLL, and PHY regulators 406, 408, 410 ma be able to supply ther respective reul tor supply voltages, and when disabled* he PLL, DLL, md PflY regulate 406, 1, 410 ma he disabled s»d½ anab!e to supply their respecti e regulator supply voltages.

The analog testing elreuitry 422 may be used for totln-g or debuggiug. The analog testing eireuitry uss indude intiitiplexer (MUX) circuitry that ma be wafigared

74 and/or switched to a plurality of different states m order to test or debng other components of the analog ekcoitry f Id, The core logic circuitry !0¾, ¾se: as by usin the rocessing etrostlry 2, may send a control signal es C ld to the analog testing circuitr 422 o configure the anafcsg testing oirantty 422 in a desired one of Hs different states.

|ftft?t)| The PVT sensor circuitry 424 ma include one or mare sensors that sense one or mot - process, voltage, o.r temperature raroete durittg operation. The PVT mt circuitry 424 may communicate PVT orana&on to tfee core logic ciruiUry 108, such to the processing circu ry 402 and/or tie FIX circuitry 408, which, n tens ma use that inforrtutttro to ptimise performance. For ex mp . based m. sensed temperafttre, voltage, a»d- ^? - - s e ss information received, front i¾e PVT sensor circuitry 424, the rocessing circuitry 412 and/or tic FIX drcisftry 408 may detetsnirte to increase, decrease, or maintain the clock rates of fine or more clock signals being generated and used for clocking its order to process data. The core logic eiretstay 108„ s ch as by tssmg the processing ckeoitry 02, may send a sensor easbfe/disafefe signal Sensor JEn to enable a»d disable the PVT sensor cirenhry 424.

(00711 Th clock generation or oscillator eitcttitr 426 may foe configured to generate a base- clock signal CL¾ _A ss. which may be su p ed to and used by the process sag cirenftry 402, die DLL circuitry 406, and/or the FLL circuitry 408 hi order for those circuities 402 _s 406. 08 to operate and perform their respective r½ict torn. The core lo k circuitry 108, sodi as by using die rocessing circuitry 402. may serai a clock enable/disable signal Ok En to enable and disable the clock generation circuitry 426,

(00721 .Dario^ he sleep state _* the p ocessing circuitry 402 ma not ope ate or process data on any clock pulses and/or ootnajanicate date to the host system i 0 . As swek dating the sleep state, the clock generation circuitry 426 may he disabled since the base clock signal CL s _& se that it generat s may not he u ed by the core iogie circuitry J 08. Likewise, since clock signals generated by the DLL circuitry 406 aad the PLL clrc tiiity 408 may not he nsed d rin the slee state, the DLL aa>d PLL regulators 416, 418 may be disabled dnrirsg the sleep state a order to po er dtm¾ the DLL and PLL cireaitries 06, 0& ddition ll , the p ysical interface- 410 ma sot be in operation daring the sleep state* and so the PHY regulator 420 may be disabled. Further, me analog testing circuitry 422 and the FVT sensor eiresliry 424 m y be used cmy &i wit the pore logic eirowkr ! O when the core logic efetitry 1 8 is acti ve arid the processing eiradtry 402 is operating on clock pulses, but may not be used, when die core logic drcuitry 1.08 is m tbe sleep state, Accordingly, dtitipg ibe sleep state, ttte analog testiag circuitry 422 and the PVT sensor dreultry 424 ma be disabled, (0073 ^' f In addition, as shows* I» Fig, 4, the fet su p voltage domain 412 may fteher itfclittie a fet pre-reguls ot 4 8. As previously descri ed, one fttneiioti of a. egulator when eneratin ts regulated output voltage may be to decrease the noise component (or increase tie power supply rejection ratio (PSR )j of the input supply voltage it k receiving. Since the DLL, PLL, sad PHY regulators 416, 418, 420 themselves perform regulate!, a p e^ kt r to reds.ee the noise com onent of the fet suppl voltage VCC ma not be needed for those c mponen s of the .first supply voltage domain 412.. However, in order to m imize ihe performance of the other, non-regulator coa¾JO»mts of the first supply voltage domain 412 (i.e., the analo te ting _s PVT senso , mid clock generation circttttries 422, 424, 42« the first sup ly voltage VCC may fet be regulated before it is supplied to those components.

Accordingly, the first prs-reguktor 428 may be eorfigored in the first supply voltage domain 412 to receive the first supply voltage VCC, enera e a first pre-regukted. voltage Vpreregl based oa. Ifee first supply volta e VCC _* s d supply the fet - e- egulated voltage Vpreregl to each of the analog testing, FVT sensor, and clock generation circuitries 422, 424, 426,

[ 074| The second supply voltage domain 414 may include a core regulate 430 arid p wer ora detection, circuitry 432, The core regulator 430 and power on detection circuitry 432 of the examp e arrangement t r the analog circuitry 116 s s and described with reference to Fig. 4 may be- the same as or simitar to the core regulator 202 and power on detectiors circuitry 20 shown and des ri ed wit r fe ence to f ig- 2> Referring particularly the configuration in Fig. 4, the core .regulator 430 may be configured to supply a cote suppl v l tage VDDjCORE, which tmy be used to power all or at least some of the circui e-omnoraents of the rocessing eirenitry 402 and the memory 404. The core logic circuitry ϊ 0 , such as by m g he p.focesst«g circuitry 402, may send a control signal C<>i»J¾eg. Cntfl to the core regulator 430 to enable- and disable the core regulator 430, In addition-, previously dss ri ed with reference to Fig. 2, the power on detection* circuitry 432 tmy provide the proessstag cirewitry 402 with a core voltage stsbiJtotat signal

VDD _. COME _. OK ¾dieadng ha the level of he core supply voltage VDD _. CORE Is sta le. The core logic circuitry 108, such as by using the rocessing circuitry 402, may scud a e-ontro! si nal. POR_Prgm to the power o detection circuitry 432 m order to calib ate the power on detection irctdtry 432. in particular, depending on different c :rc»a¾s¾aeeis, the predetermioed lev l at which the core r gula or 430 m to su pl the eot¾ s ppl voltage V DD _... CO E ma be diffeent at different periods of time- in operation. To dete.tt»i«e whether the level of the core supply voltage VDD CORE is stabl e, the power on detection circuitry 432 may be configured to com are the level of the core supply vohage VDDjCORE with a reference level The control gml PO _^ Prgm may be used to set the reference level in accordance with the redetermin d level at which the core regulator 430 is to supply he core supply voltage VDD CORE. For example, if circumstances c bassge suc that, the core regulator 430 is to output ihe core supply voltage VDD _J CORE at a higher level, then the control si nal PCdl * ro may be adjusted to increase the reference level used by the power on detection eire dry 432.

[00 51 .During he sleep sta e, at least » ortion o f the processing circuitry 402 may remaiu active or powered on in. order to be T&po cve to a siee ¼wafce command CMD5

17 recei ed from the h st system 102 that instructs dte processing circuitry 402 te Cnmsitio the eMMC system 104 from the sleep state to the standby state anto a reset coramaa CMDO to reset the eMMC system 104, In order for the processing circuitry 402 to .remain act v , core regulator 430 may remain active md provide the sor supply voltage VD.D_CORE to the core logic en¾n¾ry I OS in ths sleep state- Additionally, since the core logic r uitry 108 may want to fcuo to the core supply voltsge VDD _. CORE it is receiving white in the ste state is stable, then she power detection circuitry 18 may also remain active and provide Ac core voltage «ta iJi¾»to signal VOD_CO ^' E JDK to the core logic eirenitty ί 08 daring t s steep state.

[CH)76j As sho n in Fig, 4, the core regulator 430 may receive the seco d supply voltage VCCQ to generate e eo*e supply voltage VBD _.. COR.E, However, (fee second supply ^• oltage VCCQ may be too noisy for optimal ofiertftkwj of the- power on detection dre Ktry 432, and so fattier than receive tic second supply voltage VCCQ,. the power as detection circuitry 432 may receive a regulated voltage Vptereg2 from a second pre-reguiator 434 configured in the secon supply votoge domain 414, which may be coa s g^red to generate the regulated voltage Vprereg2 based on the second supply voltage VCCQ,

(Θ07Τ| As previously described. in order for a regulator to operate properly, the volta e d op or difference between the input voltage and the output ta e has to be sufficiently large. So to. an eMMC s stem 104 having ibe example analog circuitry arrangement shown in Fig. 4 can be compati ble with a host system 1 2 that sends the second supply voltage VCCQ at a level here the voltage dro between the second supply oltage: VCCQ and the regulated voltage Vprereg2 is too small, the sseeoud supply voltage domain 14 may include a charge pump 436 conifgnred to increase the level of the second swpply voltage VCCQ t provide a sufficiently large voltage drop. In particular, the charge pump 436 may receive the second supply voltage VCCQ and. generate a change pum voltage Vcp b sed on the secesd

23 suppl voltage VCCQ. -he charge pump 43 may be eon%n¾xl to generate the c arge pump voltage Yep at a level t at is shout ne m& i>rse-b¾if (1,5) tsm s the level of ^* the second supply votiage VCCQ, although other coattg atfous a e possible, ^' The charge pump 436 may supply the charge mp voltage Yep to the second pre-regalstor 434, and the second pre-regn!ator 434 may generate the regulated voltage Vpmreg2 based on the charge p mp voltage Vcp.

|W781 Additionally, the analog citculi components in the both Ihe first mid second stmply voltage domains 12, 14 may use a reference voltage to perform their resp c i e functions, Irs the e&aat ls an ngement shown in Fig. 4» a baudgttp iteta o 438 may he included In t e second mp≠y voltage domain 14 and eo«!!g«red to enerate au s*¾>ply a reference voltage Vfcg to each of the DLL regulator 416, the FIX egister 418, tia PHY regulator 420, the analog testing circuitry 422, the PVT sensor circuitry 424, he clock generation circuitry 426, the core regulator 430, and he power on detection circuitry ^' 432. The himeigap egulato 434 ma e configured in the second p ly voltage domain 414 rafter than, in the first su pl voltage domait* 412 since rite core regulator 430 and the power on etection circuitry 432 .may remain active and operational in the sleep state. An shown in Fig. 2, the b&ndgap generator 438 may receive the regulated voltage Vprereg2 from the second p∑s-regukfor 434, and general the reference voltage Vbg based on the regulated voltage Vpreteg2,

{007f| Vari us example arrangements that partition analog ci cuit com onents of the analog c irc uitry 1 16 hao multiple, different supply voltage domai s other than the example rrangeme t shown in Fig, 4 ma be ossible. In general the secon supply voltage doisuin VCOQ 4.14 may include at least the core regulator 414 that is configured to keep the portion of the core logic eiretutry 1 8 active or powered on daring the sleep state In order for that p rt on to he responsi e to host eom.ma.ods that the host system. J 02 ma send when the eMMC system 104 is the sleep state, in addition,. In general, the tmi swppJy voltage d<»¾iam 12 ma include at least one analog circu com onent thai is not needed to be operational during the ste state.

gtMISf l In alternative ex mple s*r » en*ent¾ all of the circuit c m onents of the analog e¼¾i¾r I J 6 may fee included is a single supply voltage donaam, such as the second supply ^• oltage VCCQ d raam 414. The nruliiple dornarn arrangement of the analog circuitry 116 sfeowrt in Pig- 4, eompaie to a single dotnain ajmsgensent, may provide more robust soludos¾ for performance, spec ically in terms of power supply .rejection ratio (PSRE), For exam le, as aies rted, th host s s em 102 (Fig, J ) may h configured to sup l each of the fi st supply voltage VCC smd the second supply voltage VCCQ at levels c«« «§ oi fI« to one of a ptamlily of pt¾detemtraed voltage levels., such m 3,3, 1,8, arid L2 ¥, These levels tmy be differs**! for different host system eodigurations and or the different modes of operation. For the single domain arraugernertt, where the DLL, regulator 16, the PLL regulator 418, sad or the PHY regulator 43) ate configured is? the VCCQ domain 414, if the second supply voltage VCCQ is stippled at a lower of the poss ble voltage levels (e.g., L2 V) the DLL, PLL, as¾d ΪΉΥ regulators 416, 418, 420 may be configured la the pass mode and their .respective outputs would o be regulated. Additionally, the analog testing, PVT sensor, and clock generation efccnitries 422, 24, 26 ma be operating without receiving the first pre- regulated voltage Vpreregl frora the first pte-isg i&ter 428, instead, they may he leedvtag the second supply voltage VCCQ to operate, resulting in degraded perfonaanee of those eircaaries. By separating the circuit components of the analog circuitry .116 into two supply voltage dot»at»s, where the DLL, PLL. and PHY .regulators 16, 418, 420, and the analog testing, PVT sensor, and. clock generation circuitries 422, 424, 426 are configured trt the first Sttpply voltage VCC doma n 412 rather than irt die seeood suppl voltage ^" VCCQ domain 414, a more robust analog IF solution may be achieved for sup ort ng e various voltage levels e g„ 1,2 V, 1 ,8 V, a»d 3,3 V) oftfee first and secorai suppl voltag s VCC wd VCCQ. la addition, the con.%uratk s o s? m Fig. 4 does not res ire any external discrete com onen s and has m nimal. Im act m die size aid stadby current Other or additional advantages or benefits of the example multiple domain &H¾ngeraeat shown In Fig, 4 may be possible,

|ftft$lj Fig. 5 sho s a flow chart of an example method 500 of configuring m onent of analo circuitr of an eM C system a high powe mode and a lo w power mode. The high power mode may he a power co s mption mode associated with the eMMC system, being in a standby state or & stale m. which the eMMC system h actively transferring d ta, and the low power mode may be a power eonswmpt n m de associated with the eMMC system being m a sleep shite, In addition or alternatively, the high power mode may be power consumption mode in which (he eMMC system receives more supply voltages .from a host system than when i the low power mode. For xam l , in the high power mode, the eMMC system may r ceiv two sup l voltages from the host s stem, and in the low po er mode, the eMMC system may rece ve one supply voltage fmm the host system,

j 1*182} At Hock.502, the eMMC system ma be confi ured in the high _. power mode and .receive a first supply voltage and a second supply voltage from the host, system. The fi st supply voltage may be supplied to components of the analog circuitry that do not operate in the lo power mode. Exam le components of the analog circuitry that receive the first supply voltage may include one or more of a PLL regulator,, a DLL regtdato a ^' PHY regulator, analog testing drexsitry, PVT sensor circuitry, and clock generation circuitry. E ample componetsls of the analog circuitry that receive the second supply voltage may include one or more of a core regulator and power on. detection circuitry,

|O083f The core re ul tor may generate a core supply voltage and supply the core sup l voltage to core logic eis ¾|try. In som example methods, the core regulator may generate the core suppl voltage based on the sec nd suppl voltage and a reference voltage. The reference voltage raay be generated and sappMed. by a bandgap generator. To generate the reference voltage, a charge pump ma receive the second supply voltage a»d sefate a charge pum voltage te d on the second sup l voltage. The chatge p»i»p may s«pply the charge pump voltage to a pre-rej ktor, which tnay generate a regulated voltage based on. the charge pump voltage., The pre-reg nktor may sapply the regulated v ltage to a baadgap generate, wMeii may \\m the regulated voltage to enerate the re!torsee voltage,

IWUMl At block 504 ptoeessiitg circuitry of the core logic eire tr of the e MC system may receive a eomraand to enter ½to the tew power mode. In some example methods, the command ma be a s!eep/awate eonirnand that ins ucts the processin eireoitry to transition the eMMC s stem from being in a standby state to a sleep state, At Mock 506, m response to receiving the eonimaad, the processing circuitry ma s nd one or mote disable si n ls to the eireaii eotnponetrts receiving the first supply voltage. In response to receiving the disable signals, the com onents receiving the first su pl voltage may become disabled ami longer perform their respective fnaetieM. fa additton, at block 506, the cessin titcuitry may not send any disable signals to the c mp ents receiving the second supply voltage, Aceordmgly, the components . eceding the second supply voltage may remain enabled or active whets the processing circtatry receives the command to enter Into the low power m de. (0O8S| At block SOS, after disabling the components receiving the first supply voltage, the processing circaitry ma send a response back to the bast system indicating that, the eMMC system Is ready to eater into the low power mode. At block 510, after sending the response to the host system, ike eotnpoaents configured to recei ve the first supply volisge may stop receiving the first supply voltage ll« the host system, while the compone ts configured to receive the second supply voltage may eo raite receiving the second up l voltage Ism the host system. By confmomg to receive second su pl voltage, the core ^• regulator ma eontinae to supply a core supply voltage to at least a _. portion, of the processing circuitry $ m the host system that h straeis the eMMC system to ester into the high power mode. Additionally, by eoat iung to receive the sec nd supply oltage Ihe power oa detection, circuitry may coaiiaue to o rate to aotiiy the rocess ng circuitry that ihe care supply voltage is stable.

|M>MJ At M ck 5 Ϊ 2, the host systera may de^mwue that \l ants he eMMC system to eatt mi® the high ower mode sad begsa seadirtg the first supply volta to the eMMC ^' s s em. Accordingly,, at block.5 2, the coaitpoaents of the eMMC s stem configure to rec i e the first supply voltage raay begin r ceivin the first supply voltage. The campoaeats confi ured to receive the secottd suppiy voltage may eontsmte recei ing tie second supp voltage from the host system.

At block 514, the rocessing circuitry m y receive a comman to eater into the high power mode., ia mm example meth ds, ihe eotaaiaad may be a sleep-awake e mmvS that tasiraets the ocessin eiremitry to traositioa the eMMC system ftorn being is the sleep state to the stsadb state. At block 516, m response to reeelviag the command, the processing circuitry am send o»e or mo e enable s gaals io the circuit eotapoaeais configured to receive the first supply voltage, Ϊ» res onse to receiving the enable signals, the components receiving the firs supply voltage m b come enabled to perform their respective fUoet oHs, In addition, at block 514, the processing circuitry tmy not end any enable signals to the com onents receiving the second supply voltage since those com onent are already en&ble t Accordingly, the components receiving the second supply voltage may aiata enabled or active whea the ptocessisg circuitr receives the command to eater m o the high power raode.

fWSii At block 518, after enabling die eomponeats eceiving the first supply voltage, the pr e ssfB ciremtry may & res onse back to the host system indicating thai the eMMC system has catered iaio the high po er mode. The i¾spoase rosy ma be aa indication, to the host system that the e C system s ready to perform activities in the high power roods, s ch as high p» er dais, transfer*

[0089J In the examp e method 508, he eMMC system traasitieas fe>∞ the high ower ns de to he low power mode, am! the hack to the high power mode- In other example methods, She eMMC system may transition from the low power mode to the high po er m de and e back to the low o er mode: only from the high power mod© to t e low _. power mode; only from Iks low power mode to I e high power mode or, general, tmnshion. from the low power mode ihe igh po er m de or vice vraa any number of times by performing s me or all of the operations described In Fig. 5.

[00901 Additionally, the circuit configuration of ihe analog circuit 11 shown in Fig, 2 and the eire ah eon%«raiion of the analog c rcuitry 116 shown m Fig,.4 may or ma s t he impktate«ted together. For configtmtiioos where they a e implemente together, the host eloek detection circuitry 206 and the VCCQ detecti n tircoitty 208 i y he configured in the second simp y voltage domain 414,

|MMg in addition or fsliematively, ihe host clock detection circuitry 206 and the VCCQ detection eireniiry 208 ma he configured with analog circuitry arrangements or configurations of as eMMC system 104 than the one shows;, in. Fig, 4, including

configurations ki which the analog eifeintry c mponents are not divided into different supply voltage domains, but rather in which they all receive the same supply voltage, such as the second supply voltage VCCQ,

[00921 Fig, h sh s a h!oek diagram of another example arrwtgeraeat in which all of ihe ctrcnit components of the aaa g esreuitry 1 16 (or at least those included in the arrangement shown in Fig, 4) a e inelndsd in a single sepply voltage VCCQ domain 614. Also shown a being included m. the VCCQ domain 614 are the h st clock detection circuitry 206 a the VCCQ detection, circuitry 208. The host clock detection, clmtitry 206 and i e VCCQ deteetiora eire-ukryM ^' M may he configured to o erate in the same ay as previously descri ed, with reference to Fi g, 2, For the arrangement shows? m Fg. „ in $M to sending the control signal VCC-Q JiY to fee eo:re relator 430 and the ower os detection, circuitry 432, the VCCQ detection dreaifey 2QS may also send he control si nal VCCQJIV to each ofifee DLL regwlaior 416, the PLL re ul tor 418, the FHY regulator 420, arid the first pre-rcgaiator 28, each of which may also be configured to op eraie hi a regulation mode and a pass .mode. As previously described with respect to Fig..2, based o« (he .level, of (he second supply oltage VCCQ detected by the VCCQ detection, circaitty 208, the VCCQ etec on circuitr 208 tmy output the eaattol signal VCCQJHV to set eac h of the regulators- 416, 418, 20, 428, 430 m either the regulation mee or in (he bypass mode. Other ways in which (he tos clock detection circuitry 206 and the VCCQ detection circuity 208 may be implemented with analog circuitry 1.16 in order to set one or more re ulators of he analog circuitry ! 1.6 in sillier the re ulat n mode or the by ass mode based on the oss clock signal may be possi le,

\W) addition, although the above eMMC s st m con%uratio«s and met o s are described with reference to m eMMC system cootlgnred to eommnskesite m accordance- with a J ^' EDEC eMMC Standard, similar configurations aad methods ma also be implemented with itos- Oi ule memor sysierns other ihaa eMMC s stems, including reinov&ble, solid state drive, card-based, or other e bedded m m y systems, Additionally, similar eantlguraiious and .methods may be implemented with electronic systems, devices, or apparatuses other ihm. aoR- oistile memory sstems, inclu n tese that may commuo!cate with a host system/device, receive power sop-ply ltges and a host clock signal from the host s siem'dewe.

|M f It is inte ded that the foregoing detailed description be understood as m i!tamtion of selected forms (feat the t»ve»do.o can take asd uoi as a definition f the

3S invention. It h only tb following c ms, cl»<3i«g all equivalents.,, that are intende to def e the scope of the clak-ned invention. Finally, it. should be noted t¾8t awy aspect of any of he used ¾to«e or in com inat with ne .mother.